From 4c03501d54d50d24b8018d229c999571c7704178 Mon Sep 17 00:00:00 2001
From: Samuel Dolt <samuel.dolt@netmodule.com>
Date: Wed, 26 Apr 2023 13:36:37 +0200
Subject: [PATCH] add support for cn9130-cf-pro and cn9130-bldn-mbv

Code was taken from Solidrun cn913x_build repository:
- https://github.com/SolidRun/cn913x_build.git

From a patch posted on this issues:
- https://github.com/SolidRun/cn913x_build/issues/5

And from patch from the CoreOS repository
---
 .gitignore                           |   1 +
 arch/arm/dts/Makefile                |   2 +
 arch/arm/dts/cn9130-bldn-mbv.dts     | 478 +++++++++++++++++++++++++++
 arch/arm/dts/cn9130-cf-pro.dts       | 428 ++++++++++++++++++++++++
 arch/arm/dts/cn9130-cf-solidwan.dts  | 382 +++++++++++++++++++++
 arch/arm/dts/cn9130-som.dtsi         |  98 ++++++
 arch/arm/dts/cn9131-bldn-mbv.dts     |  48 +++
 arch/arm/dts/cn9131-bldn-mbv.dtsi    | 223 +++++++++++++
 arch/arm/dts/cn9131-cf-solidwan.dts  |  50 +++
 arch/arm/dts/cn9131-cf-solidwan.dtsi | 214 ++++++++++++
 configs/sr_cn913x_cex7_defconfig     | 117 +++++++
 11 files changed, 2041 insertions(+)
 create mode 100644 arch/arm/dts/cn9130-bldn-mbv.dts
 create mode 100644 arch/arm/dts/cn9130-cf-pro.dts
 create mode 100644 arch/arm/dts/cn9130-cf-solidwan.dts
 create mode 100644 arch/arm/dts/cn9130-som.dtsi
 create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dts
 create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dtsi
 create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dts
 create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dtsi
 create mode 100644 configs/sr_cn913x_cex7_defconfig

diff --git a/.gitignore b/.gitignore
index 3a4d056edf..54c0c31a96 100644
--- a/.gitignore
+++ b/.gitignore
@@ -108,3 +108,4 @@ __pycache__
 
 # moveconfig database
 /moveconfig.db
+ubootefi.var
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 337bee7e1e..ec594a7c0c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -287,6 +287,8 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-8040-puzzle-m801.dtb		\
 	cn9130-db-A.dtb				\
 	cn9130-db-B.dtb				\
+	cn9130-cf-pro.dtb     \
+	cn9130-bldn-mbv.dtb   \
 	cn9131-db-A.dtb				\
 	cn9131-db-B.dtb				\
 	cn9132-db-A.dtb				\
diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
new file mode 100644
index 0000000000..3d41db33a9
--- /dev/null
+++ b/arch/arm/dts/cn9130-bldn-mbv.dts
@@ -0,0 +1,478 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-som.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+	model = "Belden CN9130 based SOM and Carrier MBV-A/B";
+	compatible =  "solidrun,cn9130-bldn-mbv", "marvell,cn9130-db",
+		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
+		"marvell,armada-ap806-quad", "marvell,armada-ap806",
+		"marvell,armada70x0";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		spi0 = &cp0_spi1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cp0_gpio0;
+		gpio2 = &cp0_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cp0 {
+		config-space {
+			sdhci@780000 {
+				vqmmc-supply = <&cp0_reg_sd_vccq>;
+				vmmc-supply = <&cp0_reg_sd_vcc>;
+			};
+			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "ap_mmc_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp_sd_vcc";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				status = "okay";
+			};
+			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "cp0_sd_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci1-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
+                        };
+
+		};
+		gpio@440100 {
+			p24 {
+				gpio-hog;
+				gpios = <24 GPIO_ACTIVE_HIGH>;
+				output-high;
+				line-name = "switch_reset";
+			};
+		};
+	};
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+	/* MPP Bus:
+	 * SDIO  [0-10, 12]
+	 * UART0 [11,19]
+	 */
+		/*   0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 1 0 0 0 0 0 0 3 >;
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+        vqmmc-supply = <&ap_reg_mmc_vccq>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+/*
+&cp0_uart1 {
+        status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_uart1_pins>;
+	u-boot,dm-pre-reloc;
+};
+*/
+
+/****** CP related configuration  ******/
+
+&cp0_pinctl {
+	/* MPP Bus:
+	*	[0-1] 	SMI MDC/MDIO
+	*	[2-3]	UART1 TX/RX
+	*	[4-5]	UART1 RTS/CTS - NC on carrier board
+	*	[6-8]	PTP
+	*	[10-11] SPD Strap - GPIO
+	*	[12-16]	SPI1
+	*	[17-26]	Boot straps - GPIO
+	*	[35-36]	I2C1
+	*	[37-38]	I2C0
+	*	[40] 	RCVR CLK - NC
+	*	[41]	VHV_EN - GPIO
+	*	[43]	SD CARD DT
+	*	[44-55]	RGMII
+	*	[56-61]	SDIO
+
+	***** GPIOs connected to CPLD******
+	* 	[28]	RESET_VSC8504_PHY
+	*	[31]	CPLD_RESET_VSC8254_PHY
+	*	[32]    INT_RELEASE
+	*	[33]	CPLD_STATUS_INT
+	*	[34]	CPLD_PWR_INT
+	*	[39]    RESET_EMMC
+	*	[42]	CPLD_DONE
+	*	[43]	CPLD_PROG_N
+
+
+	*/
+		   /*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = <	0xa 0xa 8   8   6   6   9   9   9   0
+			0   0   3   3   3   3   3   0   0   0
+			0   0   0   0   0   0   0   0   0   0
+			0   0   0   0   0   2   2   2   2   0
+			2   0   0   1   1   1   1   1   1   1
+			1   1   1   1   1   1  0xe 0xe 0xe 0xe
+			0xe 0xe 0 >;
+};
+
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+	/* on som */
+	eeprom0: eeprom@53 {
+                compatible = "atmel,24c64";
+                reg = <0x53>;
+                pagesize = <0x20>;
+        };
+	/* on carrier */
+	eeprom1: eeprom@50 {
+                compatible = "i2c-eeprom";
+                reg = <0x50>;
+                pagesize = <0x16>;
+        };
+
+};
+
+&cp0_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	clock-frequency = <100000>;
+	rtc: rtc@68 {
+                reg = <68>;
+		compatible = "dallas,ds1339";
+                /*connected to rtc DS1339U-33+*/
+	};
+	i2c-switch@e6 {
+                compatible = "nxp,pca9543";
+                reg = <0xe6>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+		i2c_sfp0: i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*connected to sfp cp0_eth0*/
+		};
+		i2c_sfp1: i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /*connected to sfp cp1_eth1*/
+		};
+	};
+	temp_sns:temp_sense@40 {
+		reg = <40>;
+
+	};
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_sdhci_pins
+		     &cp0_sdhci_cd_pins>;
+	bus-width = <4>;
+	status = "okay";
+	no-1-8-v;
+	max-frequency = <25000000>;
+};
+
+/* SPI NOR  */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi1_pins
+		     &cp0_spi1_cs1_pins>;
+	reg =	<0x700680 0x50>,	/* control */
+		<0x2000000 0x1000000>,	/* CS0 */
+		<0x2000000 0x1000004>,	/* CS1 */
+		<0 0xffffffff>,		/* CS2 */
+		<0 0xffffffff>;		/* CS3 */
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor", "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_SGMII2>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_PEX1>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
+
+&cp0_sata0 {
+	status = "disabled";
+};
+
+&cp0_usb3_0 {
+	status = "disabled";
+};
+
+
+&cp0_utmi0 {
+        status = "okay";
+};
+&cp0_utmi1 {
+        status = "okay";
+};
+
+&cp0_ethernet {
+        status = "okay";
+};
+
+
+/* SRDS #0 - PCIe X1 mPCIe #0 */
+&cp0_pcie0 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/* SRDS #1 - SGMII connected to VSC8584 1GbE PHY */
+&cp0_eth2 {
+        status = "okay";
+//        phy = <&cp0_vsc_phy19>; //address 0x0011001
+        phy-mode = "sgmii";
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "sfi";
+	compatible = "sff,sfp";
+
+	/* for SFP direct connectivity */
+//	i2c-bus = <&i2c_sfp0>;
+//	mod-def0-gpio = <&cp0_gpio0 27 GPIO_ACTIVE_LOW>;
+
+	/* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+//	phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+/* SRDS #3 - SGMII connected to VSC8584 1GbE PHY */
+
+&cp0_eth1 {
+	status = "okay";
+//	phy = <&cp0_vsc_phy18>; //address 0x0011000
+	phy-mode = "sgmii";
+//	phy = <&cp0_phy0>; //  only for testing on cf-solidwan - to be removed for final dtb  
+};
+
+/* SRDS #4 - Extenssion conector */
+&cp0_pcie1 {
+	num-lanes = <1>;
+	status = "okay";
+};
+
+/* SRDS #5 - Extenssion connector */
+&cp0_pcie2 {
+	num-lanes = <1>;
+	status = "okay";
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+	status = "disabled";
+        pinctrl-0 = <&cp0_mdio_pins>;
+
+	/**  only for testing on cf-solidwan - to be removed for final dtb */
+/*	cp0_phy0: ethernet-phy@0 {
+                marvell,reg-init = <3 16 0 0x1017>;
+                reg = <0>;
+        };
+	cp0_phy1: ethernet-phy@0 {
+                marvell,reg-init = <3 16 0 0x1017>;
+                reg = <0>;
+        };
+*/
+
+};
+
+&cp0_gpio0{
+	phy_vsc8504_phy_reset { 
+		gpio-hog;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "phy_vsc8504_phy_reset";
+	};
+	phy_vsc8254_phy_reset { 
+                gpio-hog;
+                gpios = <31 GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "phy_vsc8254_phy_reset";
+        };
+};
+
+&cp0_gpio1{
+	cpld_int_release {
+                gpio-hog;
+                gpios = <0 GPIO_ACTIVE_HIGH>; //MPP32
+                output-high;
+                line-name = "cpld_int_release";
+        };
+	cpld_status_int {
+                gpio-hog;
+                gpios = <1 GPIO_ACTIVE_HIGH>; //MPP33
+                output-high;
+                line-name = "cpld_status_int";
+        };
+	cpld_pwr_int {
+                gpio-hog;
+                gpios = <2 GPIO_ACTIVE_HIGH>; //MPP34
+                output-high;
+                line-name = "cpld_pwr_int";
+        };
+	cpld_reset_emmc{
+                gpio-hog;
+                gpios = <7 GPIO_ACTIVE_HIGH>; //MPP39
+                output-high;
+                line-name = "cpld_reset_emmc";
+        };
+	cpld_done {
+                gpio-hog;
+                gpios = <10 GPIO_ACTIVE_HIGH>; //MPP42
+                input;
+                line-name = "cpld_done";
+        };
+	cpld_prog_n {
+                gpio-hog;
+                gpios = <11 GPIO_ACTIVE_HIGH>; //MPP43
+                output-high;
+                line-name = "cpld_prog_n";
+	};
+};
+
+&cp0_pinctl {
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+	bank-name ="cp0-110";
+
+	cp0_i2c0_pins: cp0-i2c-pins-0 {
+		marvell,pins = < 37 38 >;
+		marvell,function = <2>;
+	};
+	cp0_i2c1_pins: cp0-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+                marvell,pins = < 44 45 46 47 48 49 50 51
+                                52 53 54 55 >;
+                marvell,function = <1>;
+	};
+	cp0_sdhci_pins: cp0-sdhi-pins-0 {
+		marvell,pins = < 56 57 58 59 60 61 >;
+		marvell,function = <14>;
+	};
+	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+		marvell,pins = < 43 >;
+		marvell,function = <1>;
+	};
+	cp0_spi1_pins: cp0-spi-pins-0 {
+		marvell,pins = < 13 14 15 16 >;
+		marvell,function = <3>;
+	};
+	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+		marvell,pins = < 12 >;
+		marvell,function = <3>;
+	};
+	cp0_mdio_pins: cp0-mdio-pins {
+                marvell,pins = < 0 1 >;
+                marvell,function = <10>;
+        };
+	cp0_ptp_pins: cp0-ptp-pins {
+		marvell,pins = < 6 7 8 >;
+		marvell,function = <9>;
+	};
+	cp0_uart1_pins: cp0-uart1-pins {
+                marvell,pins = < 2 3 >;
+                marvell,function = <8>;
+        };
+};
diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
new file mode 100644
index 0000000000..dae7a75076
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-pro.dts
@@ -0,0 +1,428 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-cex7-A.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+	model = "SolidRun CN9130 based SOM ClearFog Pro";
+	compatible = "solidrun,cn9130-cf-pro", "marvell,cn9130-db",
+		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
+		"marvell,armada-ap806-quad", "marvell,armada-ap806",
+		"marvell,armada70x0";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		spi0 = &cp0_spi1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cp0_gpio0;
+		gpio2 = &cp0_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cp0 {
+		config-space {
+			sdhci@780000 {
+				vqmmc-supply = <&cp0_reg_sd_vccq>;
+				vmmc-supply = <&cp0_reg_sd_vcc>;
+			};
+			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "ap_mmc_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp_sd_vcc";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				status = "okay";
+			};
+			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "cp0_sd_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+		};
+		gpio@440100 {
+			p24 {
+				gpio-hog;
+				gpios = <24 GPIO_ACTIVE_HIGH>;
+				output-high;
+				line-name = "switch_reset";
+			};
+		};
+	};
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+	/* MPP Bus:
+	 * SDIO  [0-10, 12]
+	 * UART0 [11,19]
+	 */
+		/*   0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 1 0 0 0 0 0 0 3 >;
+/*	ap_emmc_pins: emmc-pins-0 {
+		marvell,pins = < 0 1 2 3 4 5 6 7
+				8 9 10 12 >;
+		marvell,function = <1>;
+	};*/
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+        vqmmc-supply = <&ap_reg_mmc_vccq>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+/****** CP related configuration  ******/
+
+&cp0_pinctl {
+	/* MPP Bus:
+	*	[0-1] 	SMI MDC/MDIO
+	*	[2-3]	UART1 TX/RX
+	*	[4-5]	UART1 RTS/CTS
+	*	[6-8]	PTP
+	*	[10-11] GPIO - SPD Strap
+	*	[12-16]	SPI1
+	*	[17-26]	GPIO - Boot straps
+	*	[27-34]	GPIO
+	*	[35-36]	I2C1
+	*	[37-38]	I2C1
+	*	[39] 	GPIO
+	*	[40] 	RCVR CLK
+	*	[41]	GPIO VHV_EN
+	*	[43]	SD CARD DT
+	*	[44-55]	RGMII
+	*	[56-61]	SDIO
+	*/
+		   /*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = <	0xa 0xa 8   8   6   6   9   9   9   0
+			0   0   3   3   3   3   3   0   0   0
+			0   0   0   0   0   0   0   0   0   0
+			0   0   0   0   0   2   2   2   2   0
+			2   0   0   1   1   1   1   1   1   1
+			1   1   1   1   1   1  0xe 0xe 0xe 0xe
+			0xe 0xe 0 >;
+};
+
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+
+	/*
+	 * PCA9655 GPIO expander, up to 1MHz clock.
+	 *  0-CON3 CLKREQ#
+	 *  1-CON3 PERST#
+	 *  2-
+	 *  3-CON3 W_DISABLE
+	 *  4-
+	 *  5-USB3 overcurrent
+	 *  6-USB3 power
+	 *  7-
+	 *  8-JP4 P1
+	 *  9-JP4 P4
+	 * 10-JP4 P5
+	 * 11-m.2 DEVSLP
+	 * 12-SFP_LOS
+	 * 13-SFP_TX_FAULT
+	 * 14-SFP_TX_DISABLE
+	 * 15-SFP_MOD_DEF0
+	 */
+	expander0: gpio-expander@20 {
+		/*
+		 * This is how it should be:
+		 * compatible = "onnn,pca9655", "nxp,pca9555";
+		 * but you can't do this because of the way I2C works.
+		 */
+		compatible = "nxp,pca9555";
+		gpio-controller;
+		#gpio-cells = <2>;
+		reg = <0x20>;
+
+		pcie1_0_clkreq {
+			gpio-hog;
+			gpios = <0 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "pcie1.0-clkreq";
+		};
+		pcie1_0_perst {
+			gpio-hog;
+			gpios = <3 GPIO_ACTIVE_LOW>;
+			output-low;
+			line-name = "pcie1.0-perst";
+		};
+		pcie2_0_clkreq {
+			gpio-hog;
+			gpios = <4 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "pcie2.0-clkreq";
+		};
+		usb3_ilimit {
+			gpio-hog;
+			gpios = <5 GPIO_ACTIVE_LOW>;
+			input;
+			line-name = "usb3-current-limit";
+		};
+		usb3_power {
+			gpio-hog;
+			gpios = <6 GPIO_ACTIVE_HIGH>;
+			output-high;
+			line-name = "usb3-power";
+		};
+		pcie2_0_w_disable {
+			gpio-hog;
+			gpios = <8 GPIO_ACTIVE_LOW>;
+			output-low;
+			line-name = "pcie2.0-w-disable";
+		};
+
+		pcie2_0_gnss_disable {
+			gpio-hog;
+			gpios = <9 GPIO_ACTIVE_LOW>;
+			output-low;
+			line-name = "pcie2.0-gnss-disable";
+		};
+
+		m2_devslp {
+			gpio-hog;
+			gpios = <11 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "m.2 devslp";
+		};
+	};
+
+	/* 24AA025UID */
+	carrier_eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+		pagesize = <8>;
+	};
+
+	/* M24C02-WMN6TP */
+	som_eeprom@53 {
+		compatible = "atmel,24c02";
+		reg = <0x53>;
+		pagesize = <16>;
+	};
+};
+
+&cp0_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	clock-frequency = <100000>;
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_sdhci_pins
+		     &cp0_sdhci_cd_pins>;
+	bus-width = <4>;
+	status = "okay";
+	no-1-8-v;
+};
+
+/* SPI NOR  */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi1_pins
+		     &cp0_spi1_cs1_pins>;
+	reg =	<0x700680 0x50>,	/* control */
+		<0x2000000 0x1000000>,	/* CS0 */
+		<0x2000000 0x1000004>,	/* CS1 */
+		<0 0xffffffff>,		/* CS2 */
+		<0 0xffffffff>;		/* CS3 */
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor", "spi-flash";
+		reg = <0>;
+		/* On-board MUX does not allow higher frequencies */
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_SATA1>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_PEX1>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
+
+/* SRDS #0 - SATA1 on ahci0 on M.2 slot */
+&cp0_sata0 {
+	status = "okay";
+};
+
+/* SRDS #1 - USB 3.0 host */
+&cp0_usb3_0 {
+	status = "okay";
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "sfi";
+	compatible = "sff,sfp";
+	i2c-bus = <&cp0_i2c1>;
+	los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+	mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
+	tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+	tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+	maximum-power-milliwatt = <2000>;
+};
+
+/* SRDS #3 - 1GE PHY over SGMII */
+&cp0_eth1 {
+	status = "okay";
+	phy = <&phy1>;
+	phy-mode = "sgmii";
+};
+
+/* SRDS #4 - PCIe on mini PCIe connector */
+&cp0_pcie1 {
+	num-lanes = <1>;
+	marvell,reset-gpio = <&expander0 2 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* SRDS #5 - mini PCIE slot */
+&cp0_pcie2 {
+	num-lanes = <1>;
+	marvell,reset-gpio = <&expander0 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+	status = "okay";
+	pinctrl-0 = <&cp0_mdio_pins>;
+	phy0: ethernet-phy@0 {
+		marvell,reg-init = <3 16 0 0x1a4a>;
+		reg = <0>;
+	};
+	phy1: ethernet-phy@1 {
+		marvell,reg-init = <3 16 0 0x1a4a>;
+		reg = <1>;
+	};
+};
+
+&cp0_gpio1 {
+	phy_reset { /* Release switch reset */
+		gpio-hog;
+		gpios = <27 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&cp0_ethernet {
+	status = "okay";
+};
+
+/* 1GE PHY over RGMII */
+&cp0_eth2 {
+	status = "okay";
+//	phy = <&phy0>;
+	phy-mode = "rgmii-id";
+};
+
+&cp0_pinctl {
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+	bank-name ="cp0-110";
+
+	cp0_i2c0_pins: cp0-i2c-pins-0 {
+		marvell,pins = < 37 38 >;
+		marvell,function = <2>;
+	};
+	cp0_i2c1_pins: cp0-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+                marvell,pins = < 44 45 46 47 48 49 50 51
+                                52 53 54 55 >;
+                marvell,function = <1>;
+	};
+	cp0_sdhci_pins: cp0-sdhi-pins-0 {
+		marvell,pins = < 56 57 58 59 60 61 >;
+		marvell,function = <14>;
+	};
+	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+		marvell,pins = < 43 >;
+		marvell,function = <1>;
+	};
+	cp0_spi1_pins: cp0-spi-pins-0 {
+		marvell,pins = < 13 14 15 16 >;
+		marvell,function = <3>;
+	};
+	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+		marvell,pins = < 12 >;
+		marvell,function = <3>;
+	};
+	cp0_mdio_pins: cp0-mdio-pins {
+                marvell,pins = < 40 41 >;
+                marvell,function = <10>;
+        };
+};
diff --git a/arch/arm/dts/cn9130-cf-solidwan.dts b/arch/arm/dts/cn9130-cf-solidwan.dts
new file mode 100644
index 0000000000..c26bb15af9
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-solidwan.dts
@@ -0,0 +1,382 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-cex7-A.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+	model = "SolidRun CN9130 based SOM ClearFog SolidWAN ";
+	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+		     "marvell,cn9030", "marvell,armada-ap806-quad",
+		     "marvell,armada-ap806", "marvell,armada70x0";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		spi0 = &cp0_spi1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cp0_gpio0;
+		gpio2 = &cp0_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cp0 {
+		config-space {
+			sdhci@780000 {
+				vqmmc-supply = <&cp0_reg_sd_vccq>;
+				vmmc-supply = <&cp0_reg_sd_vcc>;
+			};
+			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "ap_mmc_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp_sd_vcc";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				status = "okay";
+			};
+			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "cp0_sd_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci1-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
+                        };
+
+		};
+		gpio@440100 {
+			p24 {
+				gpio-hog;
+				gpios = <24 GPIO_ACTIVE_HIGH>;
+				output-high;
+				line-name = "switch_reset";
+			};
+		};
+	};
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+	/* MPP Bus:
+	 * SDIO  [0-10, 12]
+	 * UART0 [11,19]
+	 */
+		/*   0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 1 0 0 0 0 0 0 3 >;
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+        vqmmc-supply = <&ap_reg_mmc_vccq>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+/*
+&cp0_uart1 {
+        status = "okay";
+	pinctrl-names = "default";
+        pinctrl-0 = <&cp0_uart1_pins>;	
+	u-boot,dm-pre-reloc;
+};
+*/
+
+/****** CP related configuration  ******/
+
+&cp0_pinctl {
+	/* MPP Bus:
+	*	[0-1] 	SMI MDC/MDIO
+	*	[2-3]	UART1 TX/RX
+	*	[4-5]	UART1 RTS/CTS
+	*	[6-8]	PTP
+	*	[10-11] GPIO - SPD Strap
+	*	[12-16]	SPI1
+	*	[17-26]	GPIO - Boot straps
+	*	[27-34]	GPIO
+	*	[35-36]	I2C1
+	*	[37-38]	I2C1
+	*	[39] 	GPIO
+	*	[40] 	RCVR CLK
+	*	[41]	GPIO VHV_EN
+	*	[43]	SD CARD DT
+	*	[44-55]	RGMII --> GPIOs
+	*	[56-61]	SDIO
+	*/
+		   /*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = <	10  10  8   8   6   6   0   0   0   0
+			0   0   3   3   3   3   3   0   0   0
+			0   0   0   0   0   0   0   0   0   0
+			0   0   0   0   0   2   2   2   2   0
+			0   0   0   0   0   0   0   0   0   0
+			0   0   0   0   0   0  0xe 0xe 0xe 0xe
+			0xe 0xe 0 >;
+};
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+	eeprom0: eeprom@53 {
+                compatible = "atmel,24c64";
+                reg = <0x53>;
+                pagesize = <0x20>;
+        };
+};
+
+&cp0_i2c1 {
+	/* connected to SFP0*/
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	clock-frequency = <100000>;
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_sdhci_pins
+		     &cp0_sdhci_cd_pins>;
+	bus-width = <4>;
+	status = "okay";
+	no-1-8-v;
+};
+
+/* SPI NOR  */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi1_pins
+		     &cp0_spi1_cs1_pins>;
+	reg =	<0x700680 0x50>,	/* control */
+		<0x2000000 0x1000000>,	/* CS0 */
+		<0x2000000 0x1000004>,	/* CS1 */
+		<0 0xffffffff>,		/* CS2 */
+		<0 0xffffffff>;		/* CS3 */
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor", "spi-flash";
+		reg = <0x0>;
+		/* On-board MUX does not allow higher frequencies */
+		spi-max-frequency = <20000000>;
+	};
+	spi-flash@1 {
+                #address-cells = <0x1>;
+                #size-cells = <0x1>;
+                compatible = "jedec,spi-nor";
+                reg = <0x1>;
+                /* On carrier MUX does not allow higher frequencies */
+                spi-max-frequency = <20000000>;
+        };
+
+
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_SGMII2>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_USB3_HOST1>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
+
+&cp0_ethernet {
+        status = "okay";
+};
+
+/* SRDS #0 - PCIe X1 Gen3 M.2 Slot */
+&cp0_pcie0 {
+	num-lanes = <1>;
+	status = "okay";
+//	pinctrl-0 = <&cp0_pci0_reset_pins>;
+//	marvell,reset-gpio = <&cp0_gpio0 6 GPIO_ACTIVE_LOW>; //MPP6
+};
+
+/* SRDS #1 - 1GbE SGMII */
+&cp0_eth2 {
+        status = "okay";
+        phy-mode = "sgmii";
+        phy = <&cp0_phy1>;
+     //   phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
+};
+
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "sfi";
+	compatible = "sff,sfp";
+	i2c-bus = <&cp0_i2c1>;
+	los-gpio = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
+	mod-def0-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; //MPP32
+	tx-disable-gpio = <&cp0_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
+	tx-fault-gpio = <&cp0_gpio0 31 GPIO_ACTIVE_HIGH>; //MPP31
+	maximum-power-milliwatt = <2000>;
+};
+
+/* SRDS #3 - 1GE PHY over SGMII */
+&cp0_eth1 {
+	status = "okay";
+	phy = <&cp0_phy0>;
+	phy-mode = "sgmii";
+//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
+};
+
+/* SRDS #4 - USB 3.0 host on M.2 connector */
+&cp0_usb3_1 {
+	status = "okay";
+	vbus-supply = <&cp0_reg_usb3_vbus1>;
+};
+&cp0_utmi0 {
+        status = "okay";
+};
+&cp0_utmi1 {
+        status = "okay";
+};
+/*
+&cp0_usb3_0 {
+        status = "okay";
+	vbus-supply = <&cp0_reg_usb3_vbus0>;
+};
+*/
+
+/* SRDS #5 - mini PCIE slot */
+&cp0_pcie2 {
+	num-lanes = <1>;
+	status = "okay";
+//      pinctrl-0 = <&cp0_pci2_reset_pins>;
+//      marvell,reset-gpio = <&cp0_gpio0 8 GPIO_ACTIVE_LOW>; //MPP6
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+	status = "okay";
+	pinctrl-0 = <&cp0_mdio_pins>;
+	cp0_phy0: ethernet-phy@0 {
+		marvell,reg-init = <3 16 0 0x1017>;
+		reg = <0>;
+	};
+	cp0_phy1: ethernet-phy@1 {
+		marvell,reg-init = <3 16 0 0x1017>;
+		reg = <1>;
+	};
+};
+
+&cp0_pinctl {
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+	bank-name ="cp0-110";
+
+	cp0_i2c0_pins: cp0-i2c-pins-0 {
+		marvell,pins = < 37 38 >;
+		marvell,function = <2>;
+	};
+	cp0_i2c1_pins: cp0-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp0_sdhci_pins: cp0-sdhi-pins-0 {
+		marvell,pins = < 56 57 58 59 60 61 >;
+		marvell,function = <14>;
+	};
+	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+		marvell,pins = < 43 >;
+		marvell,function = <1>;
+	};
+	cp0_spi1_pins: cp0-spi-pins-0 {
+		marvell,pins = < 13 14 15 16 >;
+		marvell,function = <3>;
+	};
+	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+		marvell,pins = < 12 >;
+		marvell,function = <3>;
+	};
+	cp0_mdio_pins: cp0-mdio-pins {
+                marvell,pins = < 0 1 >;
+                marvell,function = <10>;
+        };
+	cp0_pci0_reset_pins: pci0-reset-pins {
+		marvell,pins = < 6 >;
+                marvell,function = <0>;
+        };
+	cp0_pci2_reset_pins: pci2-reset-pins {
+                marvell,pins = < 8 >;
+                marvell,function = <0>;
+        };
+	cp0_uart1_pins: cp0-uart1-pins {
+                marvell,pins = < 2 3 >;
+                marvell,function = <8>;
+        };
+};
diff --git a/arch/arm/dts/cn9130-som.dtsi b/arch/arm/dts/cn9130-som.dtsi
new file mode 100644
index 0000000000..f218b4613a
--- /dev/null
+++ b/arch/arm/dts/cn9130-som.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* Device Tree file for the SolidRun cn1930 based com express type 7, cp0  */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-common.dtsi"
+#include "armada-ap807.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET		(0xf2000000)
+#define CP110_SPACE_SIZE		(0x02000000)
+#define CP110_BASE			(CP110_BASE_OFFSET + \
+						(CP110_NUM * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface)	((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG		(0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME			cp0
+#define CP110_NUM			0
+#define CP110_PCIEx_CPU_MEM_BASE(iface)	((iface == 0) ? 0xc0000000 : \
+					 (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_BUS_MEM_BASE(iface)	(CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+#include "cn9130-db-dev-info.dtsi"
+
+/ {
+	model = "SolidRun CN9130 based SOM";
+	compatible =	"marvell,armada70x0", "marvell,armada-ap806-quad",
+			"marvell,armada-ap806", "marvell,cn9030";
+
+	cp0 {
+		config-space {
+			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp0-xhci0-vbus";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				startup-delay-us = <100000>;
+				regulator-force-boot-off;
+			};
+
+			cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp0-xhci1-vbus";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5000000>;
+				startup-delay-us = <100000>;
+				regulator-force-boot-off;
+			};
+			cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 {
+				compatible = "regulator-fixed";
+				regulator-min-microamp = <900000>;
+				regulator-max-microamp = <900000>;
+				regulator-force-boot-off;
+			};
+
+			cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 {
+				compatible = "regulator-fixed";
+				regulator-min-microamp = <900000>;
+				regulator-max-microamp = <900000>;
+				regulator-force-boot-off;
+			};
+		};
+	};
+};
+
+&cp0_utmi0 {
+	status = "okay";
+};
+
+&cp0_utmi1 {
+	status = "okay";
+};
+
+&cp0_usb3_0 {
+	status = "okay";
+};
+
+&cp0_usb3_1 {
+	status = "okay";
+};
+
+&cp0_gpio1 { /* Not functional in u-boot */
+	phy_reset { /* Release carrier board phy reset */
+		gpio-hog;
+		gpios = <12 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
new file mode 100644
index 0000000000..74322805db
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9131-bldn mbv-a/b */
+#include "cn9130-bldn-mbv.dts"
+#include "cn9131-bldn-mbv.dtsi"
+
+/ {
+	model = "Belden CN9131 based Platform";
+	compatible =  "solidrun,cn9131-bldn-mbv", "marvell,cn9130-db",
+		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
+		"marvell,armada-ap806-quad", "marvell,armada-ap806",
+		"marvell,armada70x0";
+};
+
+&cp1_comphy {
+	/* Serdes Configuration:
+	*	Lane 0: PCIe0 (x1)
+	*	Lane 1: USB3
+	*	Lane 2: ETH PORT 10GE
+	*	Lane 3: NC
+	*	Lane 4: PCIE1 X1
+	*	Lane 5: PCIe2 X1
+	*/
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+	};
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+	phy3 {
+		phy-type = <COMPHY_TYPE_SATA1>;
+	};
+	phy4 {
+		phy-type = <COMPHY_TYPE_PEX1>;
+	};
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dtsi b/arch/arm/dts/cn9131-bldn-mbv.dtsi
new file mode 100644
index 0000000000..afd63d8ba6
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dtsi
@@ -0,0 +1,223 @@
+/*
+* Copyright (C) 2020 SolidRun ltd.
+*
+* SPDX-License-Identifier:    GPL-2.0
+* https://spdx.org/licenses
+*/
+
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1  */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME                     cp1
+#define CP110_NUM                      1
+#define CP110_PCIE_MEM_SIZE(iface)     (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface)        (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface)        (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+/ {
+       model = "Belden CN9131 based MBV-A/B";
+       compatible = "marvell,cn9131-db";
+
+       aliases {
+               gpio3 = &cp1_gpio0;
+               gpio4 = &cp1_gpio1;
+               fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
+               fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
+       };
+	cp1 {
+                config-space {
+                        cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                        };
+                        cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                        };
+
+                        cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+                                compatible = "regulator-fixed";
+                                regulator-min-microamp = <900000>;
+                                regulator-max-microamp = <900000>;
+                                regulator-force-boot-off;
+                        };
+                };
+        };
+};
+
+&cp1_ld_efuse0 {
+       status = "disabled";
+};
+
+&cp1_ld_efuse1 {
+       status = "disabled";
+};
+
+&cp1_i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cp1_i2c1_pins>;
+       status = "okay";
+       clock-frequency = <100000>;
+};
+
+&cp1_utmi0 {
+        status = "okay";
+};
+&cp1_utmi1 {
+        status = "okay";
+};
+
+&cp1_usb3_0 {
+        status = "disabled";
+};
+
+&cp1_xmdio {
+        status = "okay";
+        pinctrl-0 = <&cp1_xmdio_pins>;
+	cp0_sfi_phy8: ethernet-phy@8 {
+                reg = <8>;
+        };
+	cp1_sfi_phy9: ethernet-phy@9 {
+                reg = <9>;
+        };
+};
+
+&cp1_mdio {
+        status = "okay";
+        pinctrl-0 = <&cp1_mdio_pins>;
+        cp0_vsc_phy18: ethernet-phy@18 {
+                reg = <18>;
+        };
+	cp0_vsc_phy19: ethernet-phy@19 {
+                reg = <19>;
+        };
+};
+
+
+&cp1_pinctl {
+       compatible = "marvell,mvebu-pinctrl",
+                    "marvell,cp115-standalone-pinctrl";
+       bank-name ="cp1-110";
+
+       /* MPP Bus:
+	*	[3:2]	xmdio
+	*	[5:4]	mdio
+	*	[36:35]	i2c1
+	*	[43:40]	rs232
+	*/
+               /*      0    1    2    3    4    5    6    7    8    9 */
+       pin-func = <    0x0  0x0  0xa  0xa  0xa  0xa  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0	0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x2  0x2  0x0  0x0  0x0
+                       0x7  0x7  0x7  0x7  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0 >;
+
+	cp1_i2c1_pins: cp1-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp1_xmdio_pins: cp1-xmdio-pins-0 {
+               marvell,pins = < 2 3 >;
+               marvell,function = <10>;
+	};
+	cp1_mdio_pins: cp1-mdio-pins-0 {
+               marvell,pins = < 4 5 >;
+               marvell,function = <10>;
+        };
+	cp1_uart1_pins: cp1-uart1-pins-0 {
+               marvell,pins = < 40 41 42 43 >;
+               marvell,function = <7>;
+        };
+};
+
+/* SATA0  */
+&cp1_sata0 {
+       status = "disabled";
+};
+
+&cp1_ethernet {
+        status = "okay";
+};
+
+/* SRDS #0 - PCIe Extenssion card */
+&cp1_pcie0 {
+	pinctrl-names = "default";
+        num-lanes = <1>;
+        status = "okay";
+	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+};
+
+/* SRDS #1 - USB Extenssion card */
+&cp1_usb3_0 {
+        status = "okay";
+        vbus-supply = <&cp1_reg_usb3_vbus0>;
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp1_eth0 {
+        status = "okay";
+        phy-mode = "sfi";
+        compatible = "sff,sfp";
+
+        /* for SFP direct connectivity */
+//      i2c-bus = <i2c_sfp1>;
+//      mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
+//	compatible = "sff,sfp";
+//	maximum-power-milliwatt = <2000>;
+
+        /* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+        phy = <&cp1_sfi_phy9>; //address 0x01001
+
+};
+
+/* SRDS #3 - not in use */ 
+
+
+/* SRDS #4 - mPCIe */
+&cp1_pcie1 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/* SRDS #5 - mPCIe */
+&cp1_pcie2 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/*************** definitions of addresses for cp0 eth ports ************/
+
+&cp0_eth0 {
+        status = "okay";
+	phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+&cp0_eth1 {
+        status = "okay";
+        phy = <&cp0_vsc_phy18>; //address 0x0011000
+};
+
+&cp0_eth2 {
+        status = "okay";
+        phy = <&cp0_vsc_phy19>; //address 0x0011001
+};
+
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dts b/arch/arm/dts/cn9131-cf-solidwan.dts
new file mode 100644
index 0000000000..95c3aec3c5
--- /dev/null
+++ b/arch/arm/dts/cn9131-cf-solidwan.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9131-cex7-A */
+
+#include "cn9130-cf-solidwan.dts"
+#include "cn9131-cf-solidwan.dtsi"
+
+/ {
+	model = "Belden CN9131 based Platform";
+	compatible =	"marvell,cn9131-db", "marvell,armada-ap806-quad",
+			"marvell,armada-ap806";
+};
+
+&cp1_comphy {
+	/* Serdes Configuration:
+	*	Lane 0: PCIe
+	*	Lane 1: SATA
+	*	Lane 2: USB3
+	*	Lane 3: SGMII 
+	*	Lane 4: XFI
+	*	Lane 5: SGMII
+	*/
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <COMPHY_TYPE_SATA0>;
+	};
+	phy2 {
+		phy-type = <COMPHY_TYPE_USB3_HOST1>;
+	};
+	phy3 {	
+		phy-type = <COMPHY_TYPE_SGMII1>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+	phy4 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+                phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+	phy5 {
+		phy-type = <COMPHY_TYPE_SGMII2>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+
+	};
+};
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dtsi b/arch/arm/dts/cn9131-cf-solidwan.dtsi
new file mode 100644
index 0000000000..5f2ee49850
--- /dev/null
+++ b/arch/arm/dts/cn9131-cf-solidwan.dtsi
@@ -0,0 +1,214 @@
+/*
+* Copyright (C) 2020 SolidRun ltd.
+*
+* SPDX-License-Identifier:    GPL-2.0
+* https://spdx.org/licenses
+*/
+
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1  */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME                     cp1
+#define CP110_NUM                      1
+#define CP110_PCIE_MEM_SIZE(iface)     (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface)        (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface)        (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+       model = "SolidRun CN9131 based SolidWan";
+       compatible = "marvell,cn9131-db";
+
+       aliases {
+               gpio3 = &cp1_gpio0;
+               gpio4 = &cp1_gpio1;
+               fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
+               fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
+       };
+
+	cp1 {
+                config-space {
+                        cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+//                                pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+                        };
+			cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+//                                pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+                                compatible = "regulator-fixed";
+                                regulator-min-microamp = <900000>;
+                                regulator-max-microamp = <900000>;
+                                regulator-force-boot-off;
+//                                gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+                        };
+                };
+        };
+};
+&cp1_ld_efuse0 {
+       status = "disabled";
+};
+
+&cp1_ld_efuse1 {
+       status = "disabled";
+};
+
+&cp1_i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cp1_i2c1_pins>;
+       status = "okay";
+       clock-frequency = <100000>;
+};
+
+
+&cp1_utmi0 {
+        status = "okay";
+};
+&cp1_utmi1 {
+        status = "okay";
+};
+/*
+&cp1_usb3_1 {
+        status = "okay";
+	vbus-supply = <&cp1_reg_usb3_vbus1>;
+};
+*/
+&cp1_pcie0 {
+       pinctrl-names = "default";
+       status = "okay";
+       num-lanes = <1>;
+               /* non-prefetchable memory */
+   	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+//        pinctrl-names = "default";
+//        marvell,reset-gpio = <&cp1_gpio0 29 GPIO_ACTIVE_LOW>;
+};
+
+&cp1_pinctl {
+       compatible = "marvell,mvebu-pinctrl",
+                    "marvell,cp115-standalone-pinctrl";
+       bank-name ="cp1-110";
+
+       /* MPP Bus:
+	*	[1:0]	UART0
+	*	[29:2]	NC
+	*	[30:29] GPIO - M.2 Power off
+	*	[32:31]	NC
+	*	[34:33] SFP GPIOs
+	*	[36:35] I2C
+	*	[38:37]	SMI
+	*	[41:40]	UART1
+	*	[48:42]	NC
+	*	[50:49] SFP GPIOs
+	*	[62:51]	NC
+	*/
+               /*      0    1    2    3    4    5    6    7    8    9 */
+       pin-func = <    0x8  0x8  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x2  0x2  0x7  0x7  0x0
+                       0x7  0x7  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0 >;
+
+	cp1_uart0_pins: cp1-uart0-pins-1 {
+               marvell,pins = < 0 1 >;
+               marvell,function = <8>;
+        };
+	cp1_uart1_pins: cp1-uart1-pins-1 {
+               marvell,pins = < 40 41 >;
+               marvell,function = <7>;
+        };
+		
+	cp1_i2c1_pins: cp1-i2c-pins-1 {
+               marvell,pins = < 35 36 >;
+               marvell,function = <2>;
+	};
+
+	cp1_mdio_pins: cp1-mdio-pins {
+                marvell,pins = < 37 38 >;
+                marvell,function = <7>;
+        };
+
+
+};
+
+&cp1_mdio2 {
+        status = "okay";
+	pinctrl-0 = <&cp1_mdio_pins>;	
+        cp1_phy0: ethernet-phy@0 {
+        	marvell,reg-init = <3 16 0 0x1017>;
+	        reg = <0>;
+        };
+        cp1_phy1: ethernet-phy@1 {
+		marvell,reg-init = <3 16 0 0x1017>;
+                reg = <1>;
+        };
+};
+
+/* SATA0  */
+&cp1_sata0 {
+       status = "okay";
+};
+
+&cp1_ethernet {
+        status = "okay";
+};
+
+&cp1_eth0 {
+        status = "okay";
+        phy-mode = "sfi";
+	compatible = "sff,sfp";
+        i2c-bus = <&cp1_i2c1>;
+        los-gpio = <&cp1_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
+        mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
+        tx-disable-gpio = <&cp1_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
+        tx-fault-gpio = <&cp1_gpio1 17 GPIO_ACTIVE_HIGH>; //MPP49
+        maximum-power-milliwatt = <2000>;
+};
+
+/* SERDES 3 SGMII */
+&cp1_eth1 {
+        status = "okay";
+        phy-mode = "sgmii";
+        phy = <&cp1_phy0>;
+//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
+};
+
+/* SERDES 5 SGMII */
+&cp1_eth2 {
+        status = "okay";
+        phy-mode = "sgmii";
+        phy = <&cp1_phy1>;
+//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
+};
+
+/* M.2 LTE USB */
+&cp1_usb3_0 {
+        status = "okay";
+	vbus-supply = <&cp1_reg_usb3_vbus0>;
+};
+
+
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
new file mode 100644
index 0000000000..e730b31bf1
--- /dev/null
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3f0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x3e0000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="cn9130-db-A"
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_SYS_LOAD_ADDR=0x800000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_RBXOS_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_SYS_PBSIZE=1051
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_MVEBU_MMC_BOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ARP_TIMEOUT=200
+CONFIG_NET_RETRY_COUNT=50
+CONFIG_AHCI_MVEBU=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MVPP2=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_PHY=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_ENV_ERASEENV=y
+CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
+CONFIG_I2C_EEPROM=y
+CONFIG_CMD_TLV_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_CMD_WDT=y
+# CONFIG_WATCHDOG is not set
+CONFIG_WDT=y
+CONFIG_WDT_SBSA=y
+# Custom
+CONFIG_BZIP2=y
+CONFIG_GZIP=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_VERSION_VARIABLE=y
