From 70b50e2ac9671cbda2e9efd7ebef37eec66b8332 Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Thu, 7 Jul 2022 21:59:29 +0300
Subject: [PATCH] uboot: add support bldn-mbv

Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
---
 arch/arm/dts/cn9130-bldn-mbv.dts  | 477 ++++++++++++++++++++++++++++++
 arch/arm/dts/cn9131-bldn-mbv.dts  |  46 +++
 arch/arm/dts/cn9131-bldn-mbv.dtsi | 223 ++++++++++++++
 3 files changed, 746 insertions(+)
 create mode 100644 arch/arm/dts/cn9130-bldn-mbv.dts
 create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dts
 create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dtsi

diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
new file mode 100644
index 0000000000..9e10eab008
--- /dev/null
+++ b/arch/arm/dts/cn9130-bldn-mbv.dts
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-som.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+	model = "Belden CN9130 based SOM and Carrier MBV-A/B";
+	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+		     "marvell,cn9030", "marvell,armada-ap806-quad",
+		     "marvell,armada-ap806", "marvell,armada70x0";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		i2c0 = &cp0_i2c0;
+		i2c1 = &cp0_i2c1;
+		spi0 = &cp0_spi1;
+		gpio0 = &ap_gpio0;
+		gpio1 = &cp0_gpio0;
+		gpio2 = &cp0_gpio1;
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	cp0 {
+		config-space {
+			sdhci@780000 {
+				vqmmc-supply = <&cp0_reg_sd_vccq>;
+				vmmc-supply = <&cp0_reg_sd_vcc>;
+			};
+			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "ap_mmc_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+				compatible = "regulator-fixed";
+				regulator-name = "cp_sd_vcc";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				status = "okay";
+			};
+			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+				compatible = "regulator-gpio";
+				regulator-name = "cp0_sd_vccq";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+				enable-active-high;
+				states = <1800000 0x1
+					3300000 0x0>;
+			};
+			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+                                compatible = "regulator-fixed";
+                                regulator-name = "cp0-xhci1-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                                gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
+                        };
+
+		};
+		gpio@440100 {
+			p24 {
+				gpio-hog;
+				gpios = <24 GPIO_ACTIVE_HIGH>;
+				output-high;
+				line-name = "switch_reset";
+			};
+		};
+	};
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+	/* MPP Bus:
+	 * SDIO  [0-10, 12]
+	 * UART0 [11,19]
+	 */
+		/*   0 1 2 3 4 5 6 7 8 9 */
+	pin-func = < 1 1 1 1 1 1 1 1 1 1
+		     1 3 1 0 0 0 0 0 0 3 >;
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+        vqmmc-supply = <&ap_reg_mmc_vccq>;
+        bus-width = <8>;
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+/*
+&cp0_uart1 {
+        status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_uart1_pins>;
+	u-boot,dm-pre-reloc;
+};
+*/
+
+/****** CP related configuration  ******/
+
+&cp0_pinctl {
+	/* MPP Bus:
+	*	[0-1] 	SMI MDC/MDIO
+	*	[2-3]	UART1 TX/RX
+	*	[4-5]	UART1 RTS/CTS - NC on carrier board
+	*	[6-8]	PTP
+	*	[10-11] SPD Strap - GPIO
+	*	[12-16]	SPI1
+	*	[17-26]	Boot straps - GPIO
+	*	[35-36]	I2C1
+	*	[37-38]	I2C0
+	*	[40] 	RCVR CLK - NC
+	*	[41]	VHV_EN - GPIO
+	*	[43]	SD CARD DT
+	*	[44-55]	RGMII
+	*	[56-61]	SDIO
+
+	***** GPIOs connected to CPLD******
+	* 	[28]	RESET_VSC8504_PHY
+	*	[31]	CPLD_RESET_VSC8254_PHY
+	*	[32]    INT_RELEASE
+	*	[33]	CPLD_STATUS_INT
+	*	[34]	CPLD_PWR_INT
+	*	[39]    RESET_EMMC
+	*	[42]	CPLD_DONE
+	*	[43]	CPLD_PROG_N
+
+
+	*/
+		   /*   0   1   2   3   4   5   6   7   8   9 */
+	pin-func = <	0xa 0xa 8   8   6   6   9   9   9   0
+			0   0   3   3   3   3   3   0   0   0
+			0   0   0   0   0   0   0   0   0   0
+			0   0   0   0   0   2   2   2   2   0
+			2   0   0   1   1   1   1   1   1   1
+			1   1   1   1   1   1  0xe 0xe 0xe 0xe
+			0xe 0xe 0 >;
+};
+
+
+&cp0_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c0_pins>;
+	status = "okay";
+	clock-frequency = <100000>;
+	/* on som */
+	eeprom0: eeprom@53 {
+                compatible = "atmel,24c64";
+                reg = <0x53>;
+                pagesize = <0x20>;
+        };
+	/* on carrier */
+	eeprom1: eeprom@50 {
+                compatible = "i2c-eeprom";
+                reg = <0x50>;
+                pagesize = <0x16>;
+        };
+
+};
+
+&cp0_i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_i2c1_pins>;
+	clock-frequency = <100000>;
+	rtc: rtc@68 {
+                reg = <68>;
+		compatible = "dallas,ds1339";
+                /*connected to rtc DS1339U-33+*/
+	};
+	i2c-switch@e6 {
+                compatible = "nxp,pca9543";
+                reg = <0xe6>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+		i2c_sfp0: i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*connected to sfp cp0_eth0*/
+		};
+		i2c_sfp1: i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /*connected to sfp cp1_eth1*/
+		};
+	};
+	temp_sns:temp_sense@40 {
+		reg = <40>;
+
+	};
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_sdhci_pins
+		     &cp0_sdhci_cd_pins>;
+	bus-width = <4>;
+	status = "okay";
+	no-1-8-v;
+	max-frequency = <25000000>;
+};
+
+/* SPI NOR  */
+&cp0_spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&cp0_spi1_pins
+		     &cp0_spi1_cs1_pins>;
+	reg =	<0x700680 0x50>,	/* control */
+		<0x2000000 0x1000000>,	/* CS0 */
+		<0x2000000 0x1000004>,	/* CS1 */
+		<0 0xffffffff>,		/* CS2 */
+		<0 0xffffffff>;		/* CS3 */
+	status = "okay";
+
+	spi-flash@0 {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		compatible = "jedec,spi-nor", "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&cp0_comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_SGMII2>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+
+	phy3 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+                phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy4 {
+		phy-type = <COMPHY_TYPE_PEX1>;
+	};
+
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
+
+&cp0_sata0 {
+	status = "disabled";
+};
+
+&cp0_usb3_0 {
+	status = "disabled";
+};
+
+
+&cp0_utmi0 {
+        status = "okay";
+};
+&cp0_utmi1 {
+        status = "okay";
+};
+
+&cp0_ethernet {
+        status = "okay";
+};
+
+
+/* SRDS #0 - PCIe X1 mPCIe #0 */
+&cp0_pcie0 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/* SRDS #1 - SGMII connected to VSC8584 1GbE PHY */
+&cp0_eth2 {
+        status = "okay";
+//        phy = <&cp0_vsc_phy19>; //address 0x0011001
+        phy-mode = "sgmii";
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+	status = "okay";
+	phy-mode = "sfi";
+	compatible = "sff,sfp";
+
+	/* for SFP direct connectivity */
+//	i2c-bus = <&i2c_sfp0>;
+//	mod-def0-gpio = <&cp0_gpio0 27 GPIO_ACTIVE_LOW>;
+
+	/* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+//	phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+/* SRDS #3 - SGMII connected to VSC8584 1GbE PHY */
+
+&cp0_eth1 {
+	status = "okay";
+//	phy = <&cp0_vsc_phy18>; //address 0x0011000
+	phy-mode = "sgmii";
+//	phy = <&cp0_phy0>; //  only for testing on cf-solidwan - to be removed for final dtb  
+};
+
+/* SRDS #4 - Extenssion conector */
+&cp0_pcie1 {
+	num-lanes = <1>;
+	status = "okay";
+};
+
+/* SRDS #5 - Extenssion connector */
+&cp0_pcie2 {
+	num-lanes = <1>;
+	status = "okay";
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+	status = "disabled";
+        pinctrl-0 = <&cp0_mdio_pins>;
+
+	/**  only for testing on cf-solidwan - to be removed for final dtb */
+/*	cp0_phy0: ethernet-phy@0 {
+                marvell,reg-init = <3 16 0 0x1017>;
+                reg = <0>;
+        };
+	cp0_phy1: ethernet-phy@0 {
+                marvell,reg-init = <3 16 0 0x1017>;
+                reg = <0>;
+        };
+*/
+
+};
+
+&cp0_gpio0{
+	phy_vsc8504_phy_reset { 
+		gpio-hog;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "phy_vsc8504_phy_reset";
+	};
+	phy_vsc8254_phy_reset { 
+                gpio-hog;
+                gpios = <31 GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "phy_vsc8254_phy_reset";
+        };
+};
+
+&cp0_gpio1{
+	cpld_int_release {
+                gpio-hog;
+                gpios = <0 GPIO_ACTIVE_HIGH>; //MPP32
+                output-high;
+                line-name = "cpld_int_release";
+        };
+	cpld_status_int {
+                gpio-hog;
+                gpios = <1 GPIO_ACTIVE_HIGH>; //MPP33
+                output-high;
+                line-name = "cpld_status_int";
+        };
+	cpld_pwr_int {
+                gpio-hog;
+                gpios = <2 GPIO_ACTIVE_HIGH>; //MPP34
+                output-high;
+                line-name = "cpld_pwr_int";
+        };
+	cpld_reset_emmc{
+                gpio-hog;
+                gpios = <7 GPIO_ACTIVE_HIGH>; //MPP39
+                output-high;
+                line-name = "cpld_reset_emmc";
+        };
+	cpld_done {
+                gpio-hog;
+                gpios = <10 GPIO_ACTIVE_HIGH>; //MPP42
+                input;
+                line-name = "cpld_done";
+        };
+	cpld_prog_n {
+                gpio-hog;
+                gpios = <11 GPIO_ACTIVE_HIGH>; //MPP43
+                output-high;
+                line-name = "cpld_prog_n";
+	};
+};
+
+&cp0_pinctl {
+	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+	bank-name ="cp0-110";
+
+	cp0_i2c0_pins: cp0-i2c-pins-0 {
+		marvell,pins = < 37 38 >;
+		marvell,function = <2>;
+	};
+	cp0_i2c1_pins: cp0-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+                marvell,pins = < 44 45 46 47 48 49 50 51
+                                52 53 54 55 >;
+                marvell,function = <1>;
+	};
+	cp0_sdhci_pins: cp0-sdhi-pins-0 {
+		marvell,pins = < 56 57 58 59 60 61 >;
+		marvell,function = <14>;
+	};
+	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+		marvell,pins = < 43 >;
+		marvell,function = <1>;
+	};
+	cp0_spi1_pins: cp0-spi-pins-0 {
+		marvell,pins = < 13 14 15 16 >;
+		marvell,function = <3>;
+	};
+	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+		marvell,pins = < 12 >;
+		marvell,function = <3>;
+	};
+	cp0_mdio_pins: cp0-mdio-pins {
+                marvell,pins = < 0 1 >;
+                marvell,function = <10>;
+        };
+	cp0_ptp_pins: cp0-ptp-pins {
+		marvell,pins = < 6 7 8 >;
+		marvell,function = <9>;
+	};
+	cp0_uart1_pins: cp0-uart1-pins {
+                marvell,pins = < 2 3 >;
+                marvell,function = <8>;
+        };
+};
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
new file mode 100644
index 0000000000..d10c7f032e
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9131-bldn mbv-a/b */
+#include "cn9130-bldn-mbv.dts"
+#include "cn9131-bldn-mbv.dtsi"
+
+/ {
+	model = "Belden CN9131 based Platform";
+	compatible =	"marvell,cn9131-db", "marvell,armada-ap806-quad",
+			"marvell,armada-ap806";
+};
+
+&cp1_comphy {
+	/* Serdes Configuration:
+	*	Lane 0: PCIe0 (x1)
+	*	Lane 1: USB3
+	*	Lane 2: ETH PORT 10GE
+	*	Lane 3: NC
+	*	Lane 4: PCIE1 X1
+	*	Lane 5: PCIe2 X1
+	*/
+	phy0 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+	};
+	phy1 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+	};
+	phy2 {
+		phy-type = <COMPHY_TYPE_SFI0>;
+		phy-speed = <COMPHY_SPEED_10_3125G>;
+	};
+	phy3 {
+		phy-type = <COMPHY_TYPE_SATA1>;
+	};
+	phy4 {
+		phy-type = <COMPHY_TYPE_PEX1>;
+	};
+	phy5 {
+		phy-type = <COMPHY_TYPE_PEX2>;
+	};
+};
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dtsi b/arch/arm/dts/cn9131-bldn-mbv.dtsi
new file mode 100644
index 0000000000..afd63d8ba6
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dtsi
@@ -0,0 +1,223 @@
+/*
+* Copyright (C) 2020 SolidRun ltd.
+*
+* SPDX-License-Identifier:    GPL-2.0
+* https://spdx.org/licenses
+*/
+
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1  */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME                     cp1
+#define CP110_NUM                      1
+#define CP110_PCIE_MEM_SIZE(iface)     (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface)        (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface)        (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+/ {
+       model = "Belden CN9131 based MBV-A/B";
+       compatible = "marvell,cn9131-db";
+
+       aliases {
+               gpio3 = &cp1_gpio0;
+               gpio4 = &cp1_gpio1;
+               fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
+               fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
+       };
+	cp1 {
+                config-space {
+                        cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                        };
+                        cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
+                                compatible = "regulator-fixed";
+                                pinctrl-names = "default";
+                                regulator-name = "cp1-xhci0-vbus";
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                startup-delay-us = <100000>;
+                                regulator-force-boot-off;
+                        };
+
+                        cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+                                compatible = "regulator-fixed";
+                                regulator-min-microamp = <900000>;
+                                regulator-max-microamp = <900000>;
+                                regulator-force-boot-off;
+                        };
+                };
+        };
+};
+
+&cp1_ld_efuse0 {
+       status = "disabled";
+};
+
+&cp1_ld_efuse1 {
+       status = "disabled";
+};
+
+&cp1_i2c1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&cp1_i2c1_pins>;
+       status = "okay";
+       clock-frequency = <100000>;
+};
+
+&cp1_utmi0 {
+        status = "okay";
+};
+&cp1_utmi1 {
+        status = "okay";
+};
+
+&cp1_usb3_0 {
+        status = "disabled";
+};
+
+&cp1_xmdio {
+        status = "okay";
+        pinctrl-0 = <&cp1_xmdio_pins>;
+	cp0_sfi_phy8: ethernet-phy@8 {
+                reg = <8>;
+        };
+	cp1_sfi_phy9: ethernet-phy@9 {
+                reg = <9>;
+        };
+};
+
+&cp1_mdio {
+        status = "okay";
+        pinctrl-0 = <&cp1_mdio_pins>;
+        cp0_vsc_phy18: ethernet-phy@18 {
+                reg = <18>;
+        };
+	cp0_vsc_phy19: ethernet-phy@19 {
+                reg = <19>;
+        };
+};
+
+
+&cp1_pinctl {
+       compatible = "marvell,mvebu-pinctrl",
+                    "marvell,cp115-standalone-pinctrl";
+       bank-name ="cp1-110";
+
+       /* MPP Bus:
+	*	[3:2]	xmdio
+	*	[5:4]	mdio
+	*	[36:35]	i2c1
+	*	[43:40]	rs232
+	*/
+               /*      0    1    2    3    4    5    6    7    8    9 */
+       pin-func = <    0x0  0x0  0xa  0xa  0xa  0xa  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0	0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x2  0x2  0x0  0x0  0x0
+                       0x7  0x7  0x7  0x7  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
+                       0x0  0x0  0x0 >;
+
+	cp1_i2c1_pins: cp1-i2c-pins-1 {
+		marvell,pins = < 35 36 >;
+		marvell,function = <2>;
+	};
+	cp1_xmdio_pins: cp1-xmdio-pins-0 {
+               marvell,pins = < 2 3 >;
+               marvell,function = <10>;
+	};
+	cp1_mdio_pins: cp1-mdio-pins-0 {
+               marvell,pins = < 4 5 >;
+               marvell,function = <10>;
+        };
+	cp1_uart1_pins: cp1-uart1-pins-0 {
+               marvell,pins = < 40 41 42 43 >;
+               marvell,function = <7>;
+        };
+};
+
+/* SATA0  */
+&cp1_sata0 {
+       status = "disabled";
+};
+
+&cp1_ethernet {
+        status = "okay";
+};
+
+/* SRDS #0 - PCIe Extenssion card */
+&cp1_pcie0 {
+	pinctrl-names = "default";
+        num-lanes = <1>;
+        status = "okay";
+	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+};
+
+/* SRDS #1 - USB Extenssion card */
+&cp1_usb3_0 {
+        status = "okay";
+        vbus-supply = <&cp1_reg_usb3_vbus0>;
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp1_eth0 {
+        status = "okay";
+        phy-mode = "sfi";
+        compatible = "sff,sfp";
+
+        /* for SFP direct connectivity */
+//      i2c-bus = <i2c_sfp1>;
+//      mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
+//	compatible = "sff,sfp";
+//	maximum-power-milliwatt = <2000>;
+
+        /* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+        phy = <&cp1_sfi_phy9>; //address 0x01001
+
+};
+
+/* SRDS #3 - not in use */ 
+
+
+/* SRDS #4 - mPCIe */
+&cp1_pcie1 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/* SRDS #5 - mPCIe */
+&cp1_pcie2 {
+        num-lanes = <1>;
+        status = "okay";
+};
+
+/*************** definitions of addresses for cp0 eth ports ************/
+
+&cp0_eth0 {
+        status = "okay";
+	phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+&cp0_eth1 {
+        status = "okay";
+        phy = <&cp0_vsc_phy18>; //address 0x0011000
+};
+
+&cp0_eth2 {
+        status = "okay";
+        phy = <&cp0_vsc_phy19>; //address 0x0011001
+};
+
