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Pull request #6: Feat/marvell bsp 

Merge in ICO/coreos from feat/marvell-bsp to master

* commit 'da856bdcd702efbf565381d4111803776ce69b1d':
  Add support for CN9130-CEX7
  feat: add meta-belden-marvell-bsp layer
This commit is contained in:
Patrick Vogelaar 2022-10-18 15:21:38 +02:00
parent 73a6546bc2 da856bdcd7
commit 33ec98c9b2
48 changed files with 112441 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
layers/meta-belden-coreos/classes/coreos-image.bbclass
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@ -42,7 +42,8 @@ IMAGE_LINGUAS ?= " "
inherit image
# Enable some feature by default
IMAGE_FEATURES += "read-only-rootfs"
# TODO. Commented out becaus it caused Problems. Need proper fixing.
# IMAGE_FEATURES += "read-only-rootfs"
# Add some extra space, as done in core-image-minimal
IMAGE_ROOTFS_EXTRA_SPACE:append = "${@bb.utils.contains("DISTRO_FEATURES", "systemd", " + 4096", "", d)}"

244
layers/meta-belden-coreos/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc Normal file
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@ -0,0 +1,244 @@
DESCRIPTION = "Trusted Firmware-A"
LICENSE = "BSD-3-Clause & MIT"
PACKAGE_ARCH = "${MACHINE_ARCH}"
inherit deploy
SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;name=tfa;branch=master"
UPSTREAM_CHECK_GITTAGREGEX = "^v(?P<pver>\d+(\.\d+)+)$"
SRCREV_FORMAT = "tfa"
COMPATIBLE_MACHINE ?= "invalid"
# Platform must be set for each machine
TFA_PLATFORM ?= "invalid"
# Some platforms can have multiple board configurations
# Leave empty for default behavior
TFA_BOARD ?= ""
# Some platforms use SPD (Secure Payload Dispatcher) services
# Few options are "opteed", "tlkd", "trusty", "tspd", "spmd"...
# Leave empty to not use SPD
TFA_SPD ?= ""
# Variable used when TFA_SPD=spmd
TFA_SPMD_SPM_AT_SEL2 ?= "1"
# SP layout file location. Used when TFA_SPD=spmd and TFA_SPMD_SPM_AT_SEL2=1
TFA_SP_LAYOUT_FILE ?= ""
# SPMC manifest file location. Used when TFA_SPD=spmd and TFA_SPMD_SPM_AT_SEL2=1
TFA_ARM_SPMC_MANIFEST_DTS ?= ""
# Build for debug (set TFA_DEBUG to 1 to activate)
TFA_DEBUG ?= "0"
S = "${WORKDIR}/git"
B = "${WORKDIR}/build"
# mbed TLS support (set TFA_MBEDTLS to 1 to activate)
TFA_MBEDTLS ?= "0"
# sub-directory in which mbedtls will be downloaded
TFA_MBEDTLS_DIR ?= "mbedtls"
# This should be set to MBEDTLS download URL if MBEDTLS is needed
SRC_URI_MBEDTLS ??= ""
# This should be set to MBEDTLS LIC FILES checksum
LIC_FILES_CHKSUM_MBEDTLS ??= ""
# add MBEDTLS to our sources if activated
SRC_URI:append = " ${@bb.utils.contains('TFA_MBEDTLS', '1', '${SRC_URI_MBEDTLS}', '', d)}"
# Update license variables
LICENSE:append = "${@bb.utils.contains('TFA_MBEDTLS', '1', ' & Apache-2.0', '', d)}"
LIC_FILES_CHKSUM:append = "${@bb.utils.contains('TFA_MBEDTLS', '1', ' ${LIC_FILES_CHKSUM_MBEDTLS}', '', d)}"
# add mbed TLS to version
SRCREV_FORMAT:append = "${@bb.utils.contains('TFA_MBEDTLS', '1', '_mbedtls', '', d)}"
# U-boot support (set TFA_UBOOT to 1 to activate)
# When U-Boot support is activated BL33 is activated with u-boot.bin file
TFA_UBOOT ??= "0"
# UEFI support (set TFA_UEFI to 1 to activate)
# When UEFI support is activated BL33 is activated with uefi.bin file
TFA_UEFI ??= "0"
# What to build
# By default we only build bl1, do_deploy will copy
# everything listed in this variable (by default bl1.bin)
TFA_BUILD_TARGET ?= "bl1"
# What to install
# do_install and do_deploy will install everything listed in this
# variable. It is set by default to TFA_BUILD_TARGET
TFA_INSTALL_TARGET ?= "${TFA_BUILD_TARGET}"
# Requires CROSS_COMPILE set by hand as there is no configure script
export CROSS_COMPILE="${TARGET_PREFIX}"
# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application
CFLAGS[unexport] = "1"
LDFLAGS[unexport] = "1"
AS[unexport] = "1"
LD[unexport] = "1"
# No configure
do_configure[noexec] = "1"
# Baremetal, just need a compiler
DEPENDS:remove = "virtual/${TARGET_PREFIX}compilerlibs virtual/libc"
# We need dtc for dtbs compilation
# We need openssl for fiptool
DEPENDS = "dtc-native openssl-native"
DEPENDS:append:toolchain-clang = " compiler-rt"
# CC and LD introduce arguments which conflict with those otherwise provided by
# this recipe. The heads of these variables excluding those arguments
# are therefore used instead.
def remove_options_tail (in_string):
from itertools import takewhile
return ' '.join(takewhile(lambda x: not x.startswith('-'), in_string.split(' ')))
EXTRA_OEMAKE += "LD=${@remove_options_tail(d.getVar('LD'))}"
EXTRA_OEMAKE += "CC=${@remove_options_tail(d.getVar('CC'))}"
# Verbose builds, no -Werror
EXTRA_OEMAKE += "V=1 E=0"
# Add platform parameter
EXTRA_OEMAKE += "BUILD_BASE=${B} PLAT=${TFA_PLATFORM}"
# Handle TFA_BOARD parameter
EXTRA_OEMAKE += "${@'TARGET_BOARD=${TFA_BOARD}' if d.getVar('TFA_BOARD') else ''}"
# Handle TFA_SPD parameter
EXTRA_OEMAKE += "${@'SPD=${TFA_SPD}' if d.getVar('TFA_SPD') else ''}"
# If TFA_SPD is spmd, set SPMD_SPM_AT_SEL2
EXTRA_OEMAKE += "${@'SPMD_SPM_AT_SEL2=${TFA_SPMD_SPM_AT_SEL2}' if d.getVar('TFA_SPD', True) == 'spmd' else ''}"
# Handle TFA_DEBUG parameter
EXTRA_OEMAKE += "${@bb.utils.contains('TFA_DEBUG', '1', 'DEBUG=${TFA_DEBUG}', '', d)}"
# Handle MBEDTLS
EXTRA_OEMAKE += "${@bb.utils.contains('TFA_MBEDTLS', '1', 'MBEDTLS_DIR=${TFA_MBEDTLS_DIR}', '', d)}"
# Uboot support
DEPENDS += " ${@bb.utils.contains('TFA_UBOOT', '1', 'u-boot', '', d)}"
do_compile[depends] += " ${@bb.utils.contains('TFA_UBOOT', '1', 'u-boot:do_deploy', '', d)}"
EXTRA_OEMAKE += "${@bb.utils.contains('TFA_UBOOT', '1', 'BL33=${DEPLOY_DIR_IMAGE}/u-boot.bin', '', d)}"
# UEFI support
DEPENDS += " ${@bb.utils.contains('TFA_UEFI', '1', 'edk2-firmware', '', d)}"
EXTRA_OEMAKE += "${@bb.utils.contains('TFA_UEFI', '1', 'BL33=${RECIPE_SYSROOT}/firmware/uefi.bin', '', d)}"
# TFTF test support
DEPENDS += " ${@bb.utils.contains('TFTF_TESTS', '1', 'tf-a-tests', '', d)}"
EXTRA_OEMAKE += "${@bb.utils.contains('TFTF_TESTS', '1', 'BL33=${RECIPE_SYSROOT}/firmware/tftf.bin', '',d)}"
# Hafnium support
SEL2_SPMC = "${@'${TFA_SPMD_SPM_AT_SEL2}' if d.getVar('TFA_SPD', True) == 'spmd' else ''}"
DEPENDS += " ${@bb.utils.contains('SEL2_SPMC', '1', 'hafnium', '', d)}"
EXTRA_OEMAKE += "${@bb.utils.contains('SEL2_SPMC', '1', 'CTX_INCLUDE_EL2_REGS=1 ARM_ARCH_MINOR=4 BL32=${RECIPE_SYSROOT}/firmware/hafnium.bin', '', d)}"
# Add SP layout file and spmc manifest for hafnium
EXTRA_OEMAKE += "${@bb.utils.contains('SEL2_SPMC', '1', 'SP_LAYOUT_FILE=${TFA_SP_LAYOUT_FILE}' if d.getVar('TFA_SP_LAYOUT_FILE') else '', '', d)}"
EXTRA_OEMAKE += "${@bb.utils.contains('SEL2_SPMC', '1', 'ARM_SPMC_MANIFEST_DTS=${TFA_ARM_SPMC_MANIFEST_DTS}' if d.getVar('TFA_ARM_SPMC_MANIFEST_DTS') else '', '', d)}"
# Tell the tools where the native OpenSSL is located
EXTRA_OEMAKE += "OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}"
# Use the correct native compiler
EXTRA_OEMAKE += "HOSTCC='${BUILD_CC}'"
# Runtime variables
EXTRA_OEMAKE += "RUNTIME_SYSROOT=${STAGING_DIR_HOST}"
BUILD_DIR = "${B}/${TFA_PLATFORM}"
BUILD_DIR .= "${@'/${TFA_BOARD}' if d.getVar('TFA_BOARD') else ''}"
BUILD_DIR .= "/${@'debug' if d.getVar("TFA_DEBUG") == '1' else 'release'}"
do_compile() {
# This is still needed to have the native tools executing properly by
# setting the RPATH
sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile
sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile
sed -i '/^LIB/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/cert_create/Makefile
# Currently there are races if you build all the targets at once in parallel
for T in ${TFA_BUILD_TARGET}; do
oe_runmake -C ${S} $T
done
}
do_compile[cleandirs] = "${B}"
do_install() {
install -d -m 755 ${D}/firmware
for atfbin in ${TFA_INSTALL_TARGET}; do
processed="0"
if [ "$atfbin" = "all" ]; then
# Target all is not handled by default
bberror "all as TFA_INSTALL_TARGET is not handled by do_install"
bberror "Please specify valid targets in TFA_INSTALL_TARGET or"
bberror "rewrite or turn off do_install"
exit 1
fi
if [ -f ${BUILD_DIR}/$atfbin.bin ]; then
echo "Install $atfbin.bin"
install -m 0644 ${BUILD_DIR}/$atfbin.bin \
${D}/firmware/$atfbin-${TFA_PLATFORM}.bin
ln -sf $atfbin-${TFA_PLATFORM}.bin ${D}/firmware/$atfbin.bin
processed="1"
fi
if [ -f ${BUILD_DIR}/$atfbin/$atfbin.elf ]; then
echo "Install $atfbin.elf"
install -m 0644 ${BUILD_DIR}/$atfbin/$atfbin.elf \
${D}/firmware/$atfbin-${TFA_PLATFORM}.elf
ln -sf $atfbin-${TFA_PLATFORM}.elf ${D}/firmware/$atfbin.elf
processed="1"
fi
if [ -f ${BUILD_DIR}/$atfbin ]; then
echo "Install $atfbin"
install -m 0644 ${BUILD_DIR}/$atfbin \
${D}/firmware/$atfbin-${TFA_PLATFORM}
ln -sf $atfbin-${TFA_PLATFORM} ${D}/firmware/$atfbin
processed="1"
fi
if [ -f ${BUILD_DIR}/fdts/$atfbin.dtb ]; then
echo "Install $atfbin.dtb"
install -m 0644 "${BUILD_DIR}/fdts/$atfbin.dtb" \
"${D}/firmware/$atfbin.dtb"
processed="1"
elif [ "$atfbin" = "dtbs" ]; then
echo "dtbs install, skipped: set dtbs in TFA_INSTALL_TARGET"
elif [ -f ${B}/tools/$atfbin/$atfbin ]; then
echo "Tools $atfbin install, skipped"
elif [ "$processed" = "0" ]; then
bberror "Unsupported TFA_INSTALL_TARGET target $atfbin"
exit 1
fi
done
}
FILES:${PN} = "/firmware"
SYSROOT_DIRS += "/firmware"
FILES:${PN}-dbg = "/firmware/*.elf"
# Skip QA check for relocations in .text of elf binaries
INSANE_SKIP:${PN}-dbg = "textrel"
do_deploy() {
cp -rf ${D}/firmware/* ${DEPLOYDIR}/
}
addtask deploy after do_install
CVE_PRODUCT = "arm:arm-trusted-firmware \
arm:trusted_firmware-a \
arm:arm_trusted_firmware \
arm_trusted_firmware_project:arm_trusted_firmware"

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layers/meta-belden-marvell-bsp/COPYING.MIT Normal file
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@ -0,0 +1,17 @@
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

41
layers/meta-belden-marvell-bsp/README Normal file
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@ -0,0 +1,41 @@
This README file contains information on the contents of the meta-belden-marvell-bsp layer.
Please see the corresponding sections below for details.
Dependencies
============
URI: <first dependency>
branch: <branch name>
URI: <second dependency>
branch: <branch name>
.
.
.
Patches
=======
Please submit any patches against the meta-belden-marvell-bsp layer to the xxxx mailing list (xxxx@zzzz.org)
and cc: the maintainer:
Maintainer: XXX YYYYYY <xxx.yyyyyy@zzzzz.com>
Table of Contents
=================
I. Adding the meta-belden-marvell-bsp layer to your build
II. Misc
I. Adding the meta-belden-marvell-bsp layer to your build
=================================================
Run 'bitbake-layers add-layer meta-belden-marvell-bsp'
II. Misc
========
--- replace with specific information about the meta-belden-marvell-bsp layer ---

13
layers/meta-belden-marvell-bsp/conf/layer.conf Normal file
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@ -0,0 +1,13 @@
# We have a conf and classes directory, add to BBPATH
BBPATH .= ":${LAYERDIR}"
# We have recipes-* directories, add to BBFILES
BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
${LAYERDIR}/recipes-*/*/*.bbappend"
BBFILE_COLLECTIONS += "meta-belden-marvell-bsp"
BBFILE_PATTERN_meta-belden-marvell-bsp = "^${LAYERDIR}/"
BBFILE_PRIORITY_meta-belden-marvell-bsp = "6"
LAYERDEPENDS_meta-belden-marvell-bsp = "core meta-belden-coreos"
LAYERSERIES_COMPAT_meta-belden-marvell-bsp = "kirkstone"

8
layers/meta-belden-marvell-bsp/conf/machine/cn9130-cex7.conf Normal file
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@ -0,0 +1,8 @@
#@TYPE: Machine
#@NAME: cn9130
#@DESCRIPTION: Machine support for Marvell Opteon TX2 CN9130.
#
require conf/machine/include/cn913x.inc
UBOOT_BUILDENV_DEVICE_TREE ?= "cn9130-cex7-A"

6
layers/meta-belden-marvell-bsp/conf/machine/cn9130-cf-pro.conf Normal file
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@ -0,0 +1,6 @@
#@TYPE: Machine
#@NAME: cn9130-cf-pro
#@DESCRIPTION: Machine support for Solidrun ClearFog CN9130 Pro
#
require conf/machine/include/cn913x.inc

6
layers/meta-belden-marvell-bsp/conf/machine/cn9131-bldn-mbv.conf Normal file
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@ -0,0 +1,6 @@
#@TYPE: Machine
#@NAME: cn9131-bldn-mbv
#@DESCRIPTION: CN9131 SOM based on Bldn MBV-A/B
#
require conf/machine/include/cn913x.inc

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layers/meta-belden-marvell-bsp/conf/machine/include/cn913x.inc Normal file
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@ -0,0 +1,60 @@
# cn913x is from Marvell octeon tx2 family, but it's based on a cortex-A72
# so we can't use the armv8-2a/tune-octeontx2.inc (armv8a vs arm8-2a)
# instead we can use the older octeontx family previously known as thunderx
require conf/machine/include/arm/armv8a/tune-thunderx.inc
# SOC_FAMILY is added to MACHINE_OVERRIDES in the soc-family.inc file
SOC_FAMILY = "cn913x"
require conf/machine/include/soc-family.inc
# Bootloader configuration
# *****************************************************************************
PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
PREFERRED_VERSION_u-boot ?= "2019.10-solidrun"
# All cn913x use the same defconfig for u-boot, but another devicetree by
# settings UBOOT_BUILDENV_DEVICE_TREE in the machine configuration file
UBOOT_MACHINE = "sr_cn913x_cex7_defconfig"
UBOOT_BUILDENV_DEVICE_TREE ??= "${MACHINE}"
UBOOT_ENTRYPOINT = "0x7000000"
UBOOT_LOADADDRESS = "0x7000000"
# Kernel configuration
# ******************************************************************************
PREFERRED_PROVIDER_virtual/kernel ?= "linux-netmodule"
PREFERRED_VERSION_linux-netmodule ?= "git-5.15-solidrun"
PREFERRED_VERSION_trusted_firmware_a ?= "2.3-solidrun"
KERNEL_IMAGETYPE = "Image"
KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}"
KERNEL_DEFCONFIG ?= "cn9130-netmodule_defconfig"
# By default we compile all supported cn913x devicetree. The devicetree to use
# is then set for each machine with the KERNEL_DEVICETREE_TO_USE variable
KERNEL_DEVICETREE ?= "\
marvell/cn9131-bldn-mbv.dtb \
marvell/cn9130-cex7.dtb \
"
# getty configuration
# ******************************************************************************
SERIAL_CONSOLES = "115200;ttyS0 115200;ttyAMA0"
SERIAL_CONSOLES_CHECK ?= "${SERIAL_CONSOLES}"
# Image generation
# ******************************************************************************
# Ensure that both flash-image.bin and boot.scr are generated as they are needed
# for a wic image
EXTRA_IMAGEDEPENDS += "trusted-firmware-a"
IMAGE_BOOT_FILES += "boot.scr"
WKS_FILE = "cn913x-sdcard.wks"
IMAGE_FSTYPES += "wic.xz wic.bmap"
MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS:append = " kernel-modules kernel-devicetree"
MACHINE_EXTRA_RRECOMMENDS = "kernel-modules kernel-devicetree"

23
layers/meta-belden-marvell-bsp/recipes-bsp/mv-ddr-marvell/mv-ddr-marvell/0001-COMPILE-fix-stack-overflow-warning.patch Normal file
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@ -0,0 +1,23 @@
From 85df3fa1ce20e577b2a1c83af01a88b7abc373ac Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Wed, 24 Mar 2021 15:47:08 +0200
Subject: [PATCH] COMPILE: fix stack overflow warning
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
---
drivers/snps/snps_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/snps/snps_fw.c b/drivers/snps/snps_fw.c
index e2bbe57..811d70c 100644
--- a/drivers/snps/snps_fw.c
+++ b/drivers/snps/snps_fw.c
@@ -451,7 +451,7 @@ static void snps_mail_box_print_stream_msg(int msg_id, int msg_log_index)
/* 1D and 2D have different mail box dictionary database */
mb_stream_database = (snps_get_state() == TRAINING_2D ? two_d_messages : one_d_messages);
- stream_msg_count = sizeof(mb_stream_database) / sizeof(mb_stream_database[0]);
+ stream_msg_count = sizeof(mb_stream_database) / sizeof(struct mail_box_stream_message);
/* Most of the dictionary msg_id's are continuous, so first check database if
* msg_id cell holds this msg_id */

62
layers/meta-belden-marvell-bsp/recipes-bsp/mv-ddr-marvell/mv-ddr-marvell/0001-fix-compilation-errors-popped-up-by-GCC-10.patch Normal file
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@ -0,0 +1,62 @@
From 18c20824d9cb05c461c30f86484c0f2b0132bb85 Mon Sep 17 00:00:00 2001
From: Konstantin Porotchkin <kostap@marvell.com>
Date: Tue, 19 Jan 2021 14:06:36 +0200
Subject: [PATCH] fix compilation errors popped up by GCC-10
1. Multiple structure definitions due to define usage
in a header file.
2. Computing static array size from a derived pointer
Change-Id: Ic016813c3f06e2ec8ff9b7ad33c182c85faaa7d5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/mv_ddr/+/43918
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
---
drivers/snps/snps.h | 2 +-
drivers/snps/snps_fw.c | 11 +++++++++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/snps/snps.h b/drivers/snps/snps.h
index 2ed1fec..6964c1c 100644
--- a/drivers/snps/snps.h
+++ b/drivers/snps/snps.h
@@ -322,7 +322,7 @@ struct snps_global_data {
int current_run_num;
};
-struct snps_global_data gd;
+extern struct snps_global_data gd;
extern int static_section_completed;
diff --git a/drivers/snps/snps_fw.c b/drivers/snps/snps_fw.c
index 811d70c..7417e06 100644
--- a/drivers/snps/snps_fw.c
+++ b/drivers/snps/snps_fw.c
@@ -101,6 +101,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "ddr_topology_def.h"
#include "ddr3_training_ip_db.h"
+struct snps_global_data gd;
+
struct mail_box_major_message mb_major_messages[] = {
/* ID, Message string */
{MB_MAJOR_ID_END_INIT, "End of initialization"},
@@ -450,8 +452,13 @@ static void snps_mail_box_print_stream_msg(int msg_id, int msg_log_index)
debug_enter();
/* 1D and 2D have different mail box dictionary database */
- mb_stream_database = (snps_get_state() == TRAINING_2D ? two_d_messages : one_d_messages);
- stream_msg_count = sizeof(mb_stream_database) / sizeof(struct mail_box_stream_message);
+ if (snps_get_state() == TRAINING_2D) {
+ mb_stream_database = two_d_messages;
+ stream_msg_count = ARRAY_SIZE(two_d_messages);
+ } else {
+ mb_stream_database = one_d_messages;
+ stream_msg_count = ARRAY_SIZE(one_d_messages);
+ }
/* Most of the dictionary msg_id's are continuous, so first check database if
* msg_id cell holds this msg_id */

41
layers/meta-belden-marvell-bsp/recipes-bsp/mv-ddr-marvell/mv-ddr-marvell_git.bb Normal file
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@ -0,0 +1,41 @@
# Recipe created by recipetool
# This is the basis of a recipe and may need further editing in order to be fully functional.
# (Feel free to remove these comments when editing.)
# WARNING: the following LICENSE and LIC_FILES_CHKSUM values are best guesses - it is
# your responsibility to verify that the values are complete and correct.
#
# The following license files were not able to be identified and are
# represented as "Unknown" below, you will need to check them yourself:
# drivers/snps/fw/snps_license.txt
LICENSE = "Unknown"
LIC_FILES_CHKSUM = "file://drivers/snps/fw/snps_license.txt;md5=eec6820d302b600f6c1dc29d86f75ccb"
SRC_URI = "git://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git;branch=mv-ddr-devel;protocol=https \
file://0001-COMPILE-fix-stack-overflow-warning.patch \
file://0001-fix-compilation-errors-popped-up-by-GCC-10.patch \
"
# Modify these as desired
PV = "1.0+git${SRCPV}"
SRCREV = "305d923e6bc4236cd3b902f6679b0aef9e5fa52d"
S = "${WORKDIR}/git"
do_configure () {
:
}
do_compile () {
:
}
do_install () {
# The sources are needed by arm-trusted-firmware
install -d "${D}/usr/src/${PN}"
cp -r "${S}/." "${D}/usr/src/${PN}/"
}
FILES:${PN}-dev = "/usr/src/${PN}"
INSANE_SKIP:${PN}-dev += "file-rdeps"
SYSROOT_DIRS += " /usr/src/${PN} "

28
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/README.md Normal file
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# trusted-firmware-a
trusted-firmware-a recipes was copied from:
meta-arm/meta-arm/recipes-bsp/trusted-firmware-a
Repo: git://git.yoctoproject.org/meta-arm
Branch: kirkstone
Git SHA: 78fce73c3803aba82149a3a03fde1b708f5424fa
Theses files were copied:
- trusted-firmware-a.inc
- files/ssl.patch
Theses files were created, by doing the same as done in meta-arm/meta-arm-bsp
but using the same revision and make flags as in https://github.com/SolidRun/cn913x_yocto_meta.git
- trusted-firmware-a_2.3.bb
Theses files were copied from https://github.com/SolidRun/cn913x_yocto_meta.git
- files/mrvl_scp_bl2.img
- files/000*.patch
More info about how to use trusted-firmware-a for Marvell can be found at
https://trustedfirmware-a.readthedocs.io/en/latest/plat/marvell/armada/build.html

41
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/files/0001-Fix-fiptool-native-compilation.patch Normal file
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@ -0,0 +1,41 @@
From daccaca55e040873d003d6398f1a519cd85ce7fa Mon Sep 17 00:00:00 2001
From: Xabier Marquiegui <xmarquiegui@ainguraiiot.com>
Date: Mon, 22 Feb 2021 16:45:54 +0100
Subject: [PATCH] Fix fiptool native compilation
Makefile was overriding CPPFLAGS in such a way that the system was
unable to find some include directories
---
Makefile | 2 +-
tools/fiptool/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 961423826..ab38c7a0f 100644
--- a/Makefile
+++ b/Makefile
@@ -1270,7 +1270,7 @@ ${FIPTOOL}:
@${ECHO_BLANK_LINE}
@echo "Building $@"
ifdef UNIX_MK
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
+ ${Q}${MAKE} CPPFLAGS="${BUILD_CPPFLAGS} -DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index df8ab5c7b..c56cc35e6 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -38,7 +38,7 @@ all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
@echo " HOSTLD $@"
- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}
+ ${Q}${HOSTCC} ${BUILD_LDFLAGS} ${OBJECTS} -o $@ ${LDLIBS}
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
--
2.25.1

164
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/files/0001-ddr-spd-read-failover-to-defualt-config.patch Normal file
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@ -0,0 +1,164 @@
From 5aeea052b30604b2f8640960b775cee0f5c877cb Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Mon, 22 Nov 2021 13:33:25 +0200
Subject: [PATCH 2/2] ddr spd read failover to defualt config
---
.../octeontx/otx2/t91/t9130/board/dram_port.c | 100 ++++++++++++++++--
1 file changed, 93 insertions(+), 7 deletions(-)
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
index 0befadfc6..5de71f095 100644
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
@@ -33,7 +33,7 @@ struct mv_ddr_iface dram_iface_ap0 = {
.id = 0,
.iface_base_addr = 0,
.tm = {
- DEBUG_LEVEL_ERROR,
+ DEBUG_LEVEL_INFO,
0x1, /* active interfaces */
/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
{ { { {0x1, 0x0, 0, 0},
@@ -45,8 +45,8 @@ struct mv_ddr_iface dram_iface_ap0 = {
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0},
{0x1, 0x0, 0, 0} },
- SPEED_BIN_DDR_2400T, /* speed_bin */
- MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
+ SPEED_BIN_DDR_2400R, /* speed_bin */
+ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
MV_DDR_DIE_CAP_8GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
@@ -54,7 +54,8 @@ struct mv_ddr_iface dram_iface_ap0 = {
#if DDR32
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
#else
- MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
+/* MV_DDR_64BIT_ECC_PUP8_BUS_MASK, *//* subphys mask */
+ MV_DDR_64BIT_BUS_MASK,
#endif
MV_DDR_CFG_SPD, /* ddr configuration data src */
NOT_COMBINED, /* ddr twin-die combined*/
@@ -98,6 +99,87 @@ struct mv_ddr_iface dram_iface_ap0 = {
},
};
+u8 is_spd_empty_sr(u8 *spd_buffer){
+/* checks the first 196 bytes to check if SPD is has any DDR */
+ u32 i=0;
+ u32 size=MV_DDR_SPD_DATA_BLOCK0_SIZE+MV_DDR_SPD_DATA_BLOCK1M_SIZE;
+ for (i=0; i<size; i++){
+ if (spd_buffer[i] != 0xff) {
+ return 0;
+ }
+ }
+ return 1;
+}
+
+void define_gpio_input_sr (u32 mux_address, u32 direction_address, u8 bit_start_mux, u8 bit_dir_address)
+{
+ u32 mask=0;
+ u32 val;
+
+ /* define as gpio */
+ val = mmio_read_32 (mux_address);
+ mask |= (0xf << bit_start_mux);
+ mask = ~mask;
+ val &= mask;
+ mmio_write_32(mux_address, val);
+ /*define as input */
+
+ val = mmio_read_32(direction_address);
+ val |= (1 << bit_dir_address);
+ mmio_write_32(direction_address, val);
+
+ /*all is standard polarity by defualt */
+}
+
+u8 read_gpio_strap_sr (u32 addr, u8 bit_loc)
+{
+ u32 val;
+
+ val=mmio_read_32 (addr);
+ val &= (0x1<<bit_loc);
+ printf("\nDDR Strap %d, value is %d\n", bit_loc, val != 0);
+
+ if (!val)
+ return (u8) 0;
+
+ return (u8) 1;
+
+}
+
+void set_param_based_on_som_strap (){
+ /* sample GPIOs 10, 11
+ * MPP10: 1-ECC /0-noECC
+ * MPP11: 1-4Gb /0-8Gb per component
+ */
+
+ /*defining MPP[11:10] as gpio inputs*/
+ define_gpio_input_sr (0xf2440004, 0xf2440100, 8, 10);
+ define_gpio_input_sr (0xf2440004, 0xf2440100, 12,11);
+
+ /*after SPD read failed, defining as DEFAULT configuration*/
+ dram_iface_ap0.tm.cfg_src = MV_DDR_CFG_DEFAULT;
+
+ /* read gpio value to check if ECC exist or not */
+ if (read_gpio_strap_sr ((u32) 0xf2440110, (u8) 10)){
+ printf("ecc strap value=1\n\n");
+ dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_ECC_PUP8_BUS_MASK;
+ }
+ else {
+ dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_BUS_MASK;
+ printf("ecc strap value=0\n\n");
+ }
+ /* read gpio value to check 4GB or 8GB configuration */
+ if (!read_gpio_strap_sr ((u32) 0xf2440110, (u8) 11)){
+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_8GBIT;
+ printf("die capacity strap value=1\n\n");
+ }
+ else{
+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_4GBIT;
+ printf("die capacity strap value=1\n\n");
+ }
+}
+
+
/* Pointer to the first DRAM interface in the system */
struct mv_ddr_iface *ptr_iface = &dram_iface_ap0;
@@ -109,7 +191,7 @@ struct mv_ddr_iface *mv_ddr_iface_get(void)
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
- /* Return the board topology as defined in the board code */
+/* Return the board topology as defined in the board code */
return &ptr_iface->tm;
}
@@ -135,6 +217,8 @@ static void mpp_config(void)
* based on information received from SPD or bootloader
* configuration located on non volatile storage
*/
+
+
void plat_marvell_dram_update_topology(void)
{
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@@ -152,7 +236,9 @@ void plat_marvell_dram_update_topology(void)
i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
/* read data from spd */
- i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
- sizeof(tm->spd_data.all_bytes));
+ i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,sizeof(tm->spd_data.all_bytes));
+ /* if SPD is empty, then copy default configuration as SPD */
+ if (is_spd_empty_sr(tm->spd_data.all_bytes))
+ set_param_based_on_som_strap();
}
}
--
2.25.1

127
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/files/0002-som-sdp-failover-using-crc-verification.patch Normal file
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@ -0,0 +1,127 @@
From da25bbba607de35267f4dbe74cd772588260de57 Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Mon, 6 Dec 2021 18:34:37 +0200
Subject: [PATCH] som sdp failover using crc verification
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
---
.../octeontx/otx2/t91/t9130/board/dram_port.c | 63 ++++++++++++-------
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
index 5de71f095..d59b8100d 100644
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
@@ -50,7 +50,7 @@ struct mv_ddr_iface dram_iface_ap0 = {
MV_DDR_DIE_CAP_8GBIT, /* die capacity */
MV_DDR_FREQ_SAR, /* frequency */
0, 0, /* cas_l, cas_wl */
- MV_DDR_TEMP_LOW} }, /* temperature */
+ MV_DDR_TEMP_HIGH} }, /* temperature */
#if DDR32
MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
#else
@@ -99,16 +99,33 @@ struct mv_ddr_iface dram_iface_ap0 = {
},
};
-u8 is_spd_empty_sr(u8 *spd_buffer){
-/* checks the first 196 bytes to check if SPD is has any DDR */
- u32 i=0;
- u32 size=MV_DDR_SPD_DATA_BLOCK0_SIZE+MV_DDR_SPD_DATA_BLOCK1M_SIZE;
- for (i=0; i<size; i++){
- if (spd_buffer[i] != 0xff) {
- return 0;
- }
+int spd_crc16_sr (u8 *ptr, int count){
+ /*crc16 calculation*/
+ int crc, i;
+ crc = 0;
+ while (--count >= 0) {
+ crc = crc ^ (int)*ptr++ << 8;
+ for (i = 0; i < 8; ++i)
+ if (crc & 0x8000)
+ crc = crc << 1 ^ 0x1021;
+ else
+ crc = crc << 1;
}
- return 1;
+ return (crc & 0xFFFF);
+}
+
+
+u8 spd_verify_correction_sr(u8 *spd_buffer){
+/* this function verifies that the the first 196 bytes to check if SPD has any DDR configuration */
+ int data16;
+ data16= spd_crc16_sr(spd_buffer, 126);
+ if ((spd_buffer[126] !=(u8)(data16&0xff)) || (spd_buffer[127]!=(u8)(data16>>8))){
+ /* if bits 126 and 127 in the spd matches the crc calculation and the data is valid*/
+ return 1;
+ }
+
+ return 0;
+
}
void define_gpio_input_sr (u32 mux_address, u32 direction_address, u8 bit_start_mux, u8 bit_dir_address)
@@ -137,7 +154,6 @@ u8 read_gpio_strap_sr (u32 addr, u8 bit_loc)
val=mmio_read_32 (addr);
val &= (0x1<<bit_loc);
- printf("\nDDR Strap %d, value is %d\n", bit_loc, val != 0);
if (!val)
return (u8) 0;
@@ -156,26 +172,26 @@ void set_param_based_on_som_strap (){
define_gpio_input_sr (0xf2440004, 0xf2440100, 8, 10);
define_gpio_input_sr (0xf2440004, 0xf2440100, 12,11);
- /*after SPD read failed, defining as DEFAULT configuration*/
+ /*after SPD crc failed, defining as DEFAULT configuration*/
dram_iface_ap0.tm.cfg_src = MV_DDR_CFG_DEFAULT;
/* read gpio value to check if ECC exist or not */
if (read_gpio_strap_sr ((u32) 0xf2440110, (u8) 10)){
- printf("ecc strap value=1\n\n");
- dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_ECC_PUP8_BUS_MASK;
+ printf("w/ ecc; strap value=1\n");
+ dram_iface_ap0.tm.bus_act_mask = MV_DDR_64BIT_ECC_PUP8_BUS_MASK;
}
else {
- dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_BUS_MASK;
- printf("ecc strap value=0\n\n");
+ dram_iface_ap0.tm.bus_act_mask =MV_DDR_64BIT_BUS_MASK;
+ printf("w/o ecc; strap value=0\n");
}
/* read gpio value to check 4GB or 8GB configuration */
- if (!read_gpio_strap_sr ((u32) 0xf2440110, (u8) 11)){
- dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_8GBIT;
- printf("die capacity strap value=1\n\n");
+ if (read_gpio_strap_sr ((u32) 0xf2440110, (u8) 11)){
+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_16GBIT;
+ printf("8GB capacity; strap value=1\n");
}
else{
- dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_4GBIT;
- printf("die capacity strap value=1\n\n");
+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_8GBIT;
+ printf("4GB capacity; strap value=0\n");
}
}
@@ -237,8 +253,11 @@ void plat_marvell_dram_update_topology(void)
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,sizeof(tm->spd_data.all_bytes));
+
/* if SPD is empty, then copy default configuration as SPD */
- if (is_spd_empty_sr(tm->spd_data.all_bytes))
+ if (spd_verify_correction_sr(tm->spd_data.all_bytes)) {
set_param_based_on_som_strap();
+ }
+
}
}
--
2.25.1

BIN
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/files/mrvl_scp_bl2.img Normal file
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52
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/files/ssl.patch Normal file
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@ -0,0 +1,52 @@
fiptool: respect OPENSSL_DIR
fiptool links to libcrypto, so as with the other tools it should respect
OPENSSL_DIR for include/library paths.
Upstream-Status: Submitted
Signed-off-by: Ross Burton <ross.burton@arm.com>
diff --git a/Makefile b/Makefile
index ec6f88585..2d3b9fc26 100644
--- a/Makefile
+++ b/Makefile
@@ -1388,7 +1388,7 @@ fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
${FIPTOOL}: FORCE
ifdef UNIX_MK
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
+ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} --no-print-directory -C ${FIPTOOLPATH}
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index 11d2e7b0b..7c2a08379 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -12,6 +12,8 @@ FIPTOOL ?= fiptool${BIN_EXT}
PROJECT := $(notdir ${FIPTOOL})
OBJECTS := fiptool.o tbbr_config.o
V ?= 0
+OPENSSL_DIR := /usr
+
override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99
@@ -20,7 +22,7 @@ ifeq (${DEBUG},1)
else
HOSTCCFLAGS += -O2
endif
-LDLIBS := -lcrypto
+LDLIBS := -L${OPENSSL_DIR}/lib -lcrypto
ifeq (${V},0)
Q := @
@@ -28,7 +30,7 @@ else
Q :=
endif
-INCLUDE_PATHS := -I../../include/tools_share
+INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include
HOSTCC ?= gcc

30
layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.3-solidrun.bb Normal file
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@ -0,0 +1,30 @@
require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc
PV = "2.3+git${SRCPV}"
SRCREV_tfa = "00ad74c7afe67b2ffaf08300710f18d3dafebb45"
LIC_FILES_CHKSUM += "file://docs/license.rst;md5=189505435dbcdcc8caa63c46fe93fa89"
SRC_URI += " \
file://0001-ddr-spd-read-failover-to-defualt-config.patch \
file://0002-som-sdp-failover-using-crc-verification.patch \
file://mrvl_scp_bl2.img \
"
COMPATIBLE_MACHINE = "cn913x"
DEPENDS += "mv-ddr-marvell coreutils-native"
CP_NUM:cn9132 = "3"
CP_NUM:cn9130 = "1"
TFA_PLATFORM = "t9130"
TFA_BUILD_TARGET = "all mrvl_flash"
TFA_INSTALL_TARGET = "flash-image"
TFA_DEBUG = "1"
TFA_MBEDTLS = "0"
TFA_UBOOT = "1"
TFA_UEFI = "0"
EXTRA_OEMAKE += "MV_DDR_PATH=${PKG_CONFIG_SYSROOT_DIR}/usr/src/mv-ddr-marvell CP_NUM=${CP_NUM} SCP_BL2=${WORKDIR}/mrvl_scp_bl2.img"

24
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch Normal file
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@ -0,0 +1,24 @@
From 0e0801291261a2c1267a42905d647cc0d1140791 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Thu, 30 Jan 2020 09:37:15 +0000
Subject: [PATCH] Remove redundant YYLOC global declaration
Same as the upstream fix for building dtc with gcc 10.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
---
scripts/dtc/dtc-lexer.l | 1 -
1 file changed, 1 deletion(-)
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
index fd825ebba6..24af549977 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n
#include "srcpos.h"
#include "dtc-parser.tab.h"
-YYLTYPE yylloc;
extern bool treesource_error;
/* CAUTION: this will stop working if we ever use yyless() or yyunput() */

18
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-sr_cn913x_cex7-enable-VERSION_VARIABLE.patch Normal file
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@ -0,0 +1,18 @@
From 8b62e225c541fdfcc764582ee80bf0d8a0b6bc65 Mon Sep 17 00:00:00 2001
From: Samuel Dolt <samuel.dolt@netmodule.com>
Date: Mon, 25 Jul 2022 15:02:00 +0200
Subject: [PATCH] sr_cn913x_cex7: enable VERSION_VARIABLE
---
configs/sr_cn913x_cex7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index 3e01b31371..a7c6c9f93e 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -115,3 +115,4 @@ CONFIG_ZSTD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_LIBFDT=y
+CONFIG_VERSION_VARIABLE=y

27
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-sr_cn913x_cex7-enable-more-image-formats.patch Normal file
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@ -0,0 +1,27 @@
From ca34fc483e68e332c5aa6c3cc98e04604216d846 Mon Sep 17 00:00:00 2001
From: Samuel Dolt <samuel.dolt@netmodule.com>
Date: Fri, 15 Jul 2022 15:36:12 +0200
Subject: [PATCH] sr_cn913x_cex7: enable more image formats
---
configs/sr_cn913x_cex7_defconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index d7445e9476..3e01b31371 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -105,3 +105,13 @@ CONFIG_I2C_EEPROM=y
CONFIG_CMD_TLV_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_NET_RANDOM_ETHADDR=y
+# Custom
+CONFIG_BZIP2=y
+CONFIG_GZIP=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_LIBFDT=y

22
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0021-octeontx2_cn913x-increase-CONFIG_SYS_BOOTM_LEN-to-32.patch Normal file
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@ -0,0 +1,22 @@
From 7e4c3c48c4ed9dcecf5228c6b4480a7c01fc6dca Mon Sep 17 00:00:00 2001
From: Samuel Dolt <samuel.dolt@netmodule.com>
Date: Tue, 19 Jul 2022 11:21:37 +0200
Subject: [PATCH] octeontx2_cn913x: increase CONFIG_SYS_BOOTM_LEN to 32MB
---
include/configs/octeontx2_cn913x.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
index d01644fcb5..9edf57c6c2 100644
--- a/include/configs/octeontx2_cn913x.h
+++ b/include/configs/octeontx2_cn913x.h
@@ -22,6 +22,8 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_BOOTM_LEN 0x3200000 /* 32MB */
+
#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
#define BOOT_TARGET_DEVICES(func) \

30
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/boot.cmd Normal file
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@ -0,0 +1,30 @@
# This script allow to boot an ostree or a non-ostree based image
# This require an image built with the same partition layout as found in
# wic/cn913x-sdcard.wks and wic/cn913x-sdcard-sota.wks:
# - partition 1 contains the first copy of the bootloader
# - partition 2 contains the second copy of the bootloader
# - partition 3 contains this script
# - partition 4 contains the rootfs
# This scripts should work both on any media type supported by u-boot with
# partition support, as we use $devtype and $devnum to refer to the current
# boot device
load_addr=0C000000
root_part=4
if test -e ${devtype} ${devnum}:${root_part} /boot/Image; then
echo "found a Image"
echo "Loading kernel /boot/Image"
load ${devtype} ${devnum}:${root_part} $kernel_addr_r /boot/Image
echo "Loading device tree /boot/${fdtfile}"
load ${devtype} ${devnum}:${root_part} ${fdt_addr_r} /boot/${fdtfile}
booti ${kernel_addr_r} - ${fdt_addr_r}
echo "Booting the kernel failed: continuing..."
fi
echo "No supported rootf found: continuing..."

1
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/cn913x.cfg Normal file
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@ -0,0 +1 @@
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y

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File diff suppressed because it is too large Load Diff

27
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@ -0,0 +1,27 @@
From 0dce367ced42c77d4de5c17b52605c6c003a4b20 Mon Sep 17 00:00:00 2001
From: Sven Auhagen <Sven.Auhagen@voleatech.de>
Date: Sun, 12 Sep 2021 09:25:44 +0200
Subject: [PATCH] cmd: tlv_eeprom
The function show_eeprom is missing int i if debug is enabled.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
---
cmd/tlv_eeprom.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 211ab2680f..96d40f4f4d 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -166,6 +166,9 @@ static void show_eeprom(u8 *eeprom)
{
int tlv_end;
int curr_tlv;
+#ifdef DEBUG
+ int i;
+#endif
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_tlv;

227
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@ -0,0 +1,227 @@
From 3a807537ace144e802e3421b29f3eea0e48d2f1f Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 17 Mar 2022 11:52:34 +0200
Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable current_dev
Make tlv_eeprom command device selection an explicit parameter of all
function calls.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
cmd/tlv_eeprom.c | 50 ++++++++++++++++++++++----------------------
include/tlv_eeprom.h | 3 ++-
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 96d40f4f4d..05d28c26c8 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -26,18 +26,18 @@ DECLARE_GLOBAL_DATA_PTR;
/* File scope function prototypes */
static bool is_checksum_valid(u8 *eeprom);
-static int read_eeprom(u8 *eeprom);
-static void show_eeprom(u8 *eeprom);
+static int read_eeprom(int devnum, u8 *eeprom);
+static void show_eeprom(int devnum, u8 *eeprom);
static void decode_tlv(struct tlvinfo_tlv *tlv);
static void update_crc(u8 *eeprom);
-static int prog_eeprom(u8 *eeprom);
+static int prog_eeprom(int devnum, u8 *eeprom);
static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
static int set_mac(char *buf, const char *string);
static int set_date(char *buf, const char *string);
static int set_bytes(char *buf, const char *string, int *converted_accum);
-static void show_tlv_devices(void);
+static void show_tlv_devices(int current_dev);
/* Set to 1 if we've read EEPROM into memory */
static int has_been_read;
@@ -45,7 +45,6 @@ static int has_been_read;
static u8 eeprom[TLV_INFO_MAX_LEN];
static struct udevice *tlv_devices[MAX_TLV_DEVICES];
-static unsigned int current_dev;
#define to_header(p) ((struct tlvinfo_header *)p)
#define to_entry(p) ((struct tlvinfo_tlv *)p)
@@ -122,7 +121,7 @@ static bool is_checksum_valid(u8 *eeprom)
*
* Read the EEPROM into memory, if it hasn't already been read.
*/
-static int read_eeprom(u8 *eeprom)
+static int read_eeprom(int devnum, u8 *eeprom)
{
int ret;
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
@@ -132,12 +131,11 @@ static int read_eeprom(u8 *eeprom)
return 0;
/* Read the header */
- ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, current_dev);
+ ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
/* If the header was successfully read, read the TLVs */
if (ret == 0 && is_valid_tlvinfo_header(eeprom_hdr))
ret = read_tlv_eeprom((void *)eeprom_tlv, HDR_SIZE,
- be16_to_cpu(eeprom_hdr->totallen),
- current_dev);
+ be16_to_cpu(eeprom_hdr->totallen), devnum);
// If the contents are invalid, start over with default contents
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
@@ -162,7 +160,7 @@ static int read_eeprom(u8 *eeprom)
*
* Display the contents of the EEPROM
*/
-static void show_eeprom(u8 *eeprom)
+static void show_eeprom(int devnum, u8 *eeprom)
{
int tlv_end;
int curr_tlv;
@@ -177,7 +175,7 @@ static void show_eeprom(u8 *eeprom)
return;
}
- printf("TLV: %u\n", current_dev);
+ printf("TLV: %u\n", devnum);
printf("TlvInfo Header:\n");
printf(" Id String: %s\n", eeprom_hdr->signature);
printf(" Version: %d\n", eeprom_hdr->version);
@@ -386,7 +384,7 @@ static void update_crc(u8 *eeprom)
*
* Write the EEPROM data from CPU memory to the hardware.
*/
-static int prog_eeprom(u8 *eeprom)
+static int prog_eeprom(int devnum, u8 *eeprom)
{
int ret = 0;
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
@@ -395,7 +393,7 @@ static int prog_eeprom(u8 *eeprom)
update_crc(eeprom);
eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
- ret = write_tlv_eeprom(eeprom, eeprom_len);
+ ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
if (ret) {
printf("Programming failed.\n");
return -1;
@@ -430,11 +428,12 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
char cmd;
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ static unsigned int current_dev = 0;
// If no arguments, read the EERPOM and display its contents
if (argc == 1) {
- read_eeprom(eeprom);
- show_eeprom(eeprom);
+ read_eeprom(current_dev, eeprom);
+ show_eeprom(current_dev, eeprom);
return 0;
}
@@ -445,7 +444,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
// Read the EEPROM contents
if (cmd == 'r') {
has_been_read = 0;
- if (!read_eeprom(eeprom))
+ if (!read_eeprom(current_dev, eeprom))
printf("EEPROM data loaded from device to memory.\n");
return 0;
}
@@ -460,7 +459,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
if (argc == 2) {
switch (cmd) {
case 'w': /* write */
- prog_eeprom(eeprom);
+ prog_eeprom(current_dev, eeprom);
break;
case 'e': /* erase */
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
@@ -473,7 +472,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
show_tlv_code_list();
break;
case 'd': /* dev */
- show_tlv_devices();
+ show_tlv_devices(current_dev);
break;
default:
cmd_usage(cmdtp);
@@ -883,7 +882,7 @@ static int set_bytes(char *buf, const char *string, int *converted_accum)
return 0;
}
-static void show_tlv_devices(void)
+static void show_tlv_devices(int current_dev)
{
unsigned int dev;
@@ -953,14 +952,14 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev_num)
/**
* write_tlv_eeprom - write the hwinfo to i2c EEPROM
*/
-int write_tlv_eeprom(void *eeprom, int len)
+int write_tlv_eeprom(void *eeprom, int len, int dev)
{
if (!(gd->flags & GD_FLG_RELOC))
return -ENODEV;
- if (!tlv_devices[current_dev])
+ if (!tlv_devices[dev])
return -ENODEV;
- return i2c_eeprom_write(tlv_devices[current_dev], 0, eeprom, len);
+ return i2c_eeprom_write(tlv_devices[dev], 0, eeprom, len);
}
int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
@@ -1015,10 +1014,11 @@ int mac_read_from_eeprom(void)
int maccount;
u8 macbase[6];
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ int devnum = 0; // TODO: support multiple EEPROMs
puts("EEPROM: ");
- if (read_eeprom(eeprom)) {
+ if (read_eeprom(devnum, eeprom)) {
printf("Read failed.\n");
return -1;
}
@@ -1083,7 +1083,7 @@ int mac_read_from_eeprom(void)
*
* This function must be called after relocation.
*/
-int populate_serial_number(void)
+int populate_serial_number(int devnum)
{
char serialstr[257];
int eeprom_index;
@@ -1092,7 +1092,7 @@ int populate_serial_number(void)
if (env_get("serial#"))
return 0;
- if (read_eeprom(eeprom)) {
+ if (read_eeprom(devnum, eeprom)) {
printf("Read failed.\n");
return -1;
}
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
index 1de2fe2337..aa96c9e8d4 100644
--- a/include/tlv_eeprom.h
+++ b/include/tlv_eeprom.h
@@ -84,11 +84,12 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev);
* write_tlv_eeprom - Write the entire EEPROM binary data to the hardware
* @eeprom: Pointer to buffer to hold the binary data
* @len : Maximum size of buffer
+ * @dev : EEPROM device to write
*
* Note: this routine does not validate the EEPROM data.
*
*/
-int write_tlv_eeprom(void *eeprom, int len);
+int write_tlv_eeprom(void *eeprom, int len, int dev);
/**
* read_tlvinfo_tlv_eeprom - Read the TLV from EEPROM, and validate

94
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@ -0,0 +1,94 @@
From 28da9685c7e65f70065319921ccaf2d2aea7b185 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 17 Mar 2022 12:49:46 +0200
Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable has_been_read
has_been_read is only used as an optimization for do_tlv_eeprom.
Explicitly use and set inside this function, thus making read_eeprom
stateless.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
cmd/tlv_eeprom.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 05d28c26c8..70c1a2e7df 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -39,8 +39,6 @@ static int set_date(char *buf, const char *string);
static int set_bytes(char *buf, const char *string, int *converted_accum);
static void show_tlv_devices(int current_dev);
-/* Set to 1 if we've read EEPROM into memory */
-static int has_been_read;
/* The EERPOM contents after being read into memory */
static u8 eeprom[TLV_INFO_MAX_LEN];
@@ -127,9 +125,6 @@ static int read_eeprom(int devnum, u8 *eeprom)
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_tlv = to_entry(&eeprom[HDR_SIZE]);
- if (has_been_read)
- return 0;
-
/* Read the header */
ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
/* If the header was successfully read, read the TLVs */
@@ -146,10 +141,8 @@ static int read_eeprom(int devnum, u8 *eeprom)
update_crc(eeprom);
}
- has_been_read = 1;
-
#ifdef DEBUG
- show_eeprom(eeprom);
+ show_eeprom(devnum, eeprom);
#endif
return ret;
@@ -429,10 +422,15 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
char cmd;
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
static unsigned int current_dev = 0;
+ /* Set to devnum if we've read EEPROM into memory */
+ static int has_been_read = -1;
// If no arguments, read the EERPOM and display its contents
if (argc == 1) {
- read_eeprom(current_dev, eeprom);
+ if(has_been_read != current_dev) {
+ read_eeprom(current_dev, eeprom);
+ has_been_read = current_dev;
+ }
show_eeprom(current_dev, eeprom);
return 0;
}
@@ -443,14 +441,16 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
// Read the EEPROM contents
if (cmd == 'r') {
- has_been_read = 0;
- if (!read_eeprom(current_dev, eeprom))
+ has_been_read = -1;
+ if (!read_eeprom(current_dev, eeprom)) {
printf("EEPROM data loaded from device to memory.\n");
+ has_been_read = current_dev;
+ }
return 0;
}
// Subsequent commands require that the EEPROM has already been read.
- if (!has_been_read) {
+ if (has_been_read != current_dev) {
printf("Please read the EEPROM data first, using the 'tlv_eeprom read' command.\n");
return 0;
}
@@ -506,7 +506,6 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
return 0;
}
current_dev = devnum;
- has_been_read = 0;
} else {
cmd_usage(cmdtp);
}

37
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0005-cmd-tlv_eeprom-do_tlv_eeprom-stop-using-non-api-read.patch Normal file
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@ -0,0 +1,37 @@
From 6578def0ace0d030a02b8c45031d41c5d2ef517e Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 17 Mar 2022 14:23:22 +0200
Subject: [PATCH] cmd: tlv_eeprom: do_tlv_eeprom: stop using non-api
read_eeprom function
IN the scope of do_tlv_eeprom, the error-checking provided by the
read_eeprom function is not required.
Instead use the API function read_tlv_eeprom.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
cmd/tlv_eeprom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 70c1a2e7df..8a926ba224 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -428,7 +428,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
// If no arguments, read the EERPOM and display its contents
if (argc == 1) {
if(has_been_read != current_dev) {
- read_eeprom(current_dev, eeprom);
+ read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev);
has_been_read = current_dev;
}
show_eeprom(current_dev, eeprom);
@@ -442,7 +442,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
// Read the EEPROM contents
if (cmd == 'r') {
has_been_read = -1;
- if (!read_eeprom(current_dev, eeprom)) {
+ if (read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev) == 0) {
printf("EEPROM data loaded from device to memory.\n");
has_been_read = current_dev;
}

278
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@ -0,0 +1,278 @@
From 62114ab82feaf919138d2d4377344072c95571de Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Thu, 17 Mar 2022 16:09:02 +0200
Subject: [PATCH] cmd: tlv_eeprom: convert functions used by command to api
functions
- prog_eeprom: write_tlvinfo_tlv_eeprom
- update_crc: tlvinfo_update_crc
- is_valid_tlv: is_valid_tlvinfo_entry
- is_checksum_valid: tlvinfo_check_crc
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
cmd/tlv_eeprom.c | 56 +++++++++++++++----------------------------
include/tlv_eeprom.h | 57 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+), 37 deletions(-)
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
index 8a926ba224..271fefc0c6 100644
--- a/cmd/tlv_eeprom.c
+++ b/cmd/tlv_eeprom.c
@@ -25,13 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_TLV_DEVICES 2
/* File scope function prototypes */
-static bool is_checksum_valid(u8 *eeprom);
static int read_eeprom(int devnum, u8 *eeprom);
static void show_eeprom(int devnum, u8 *eeprom);
static void decode_tlv(struct tlvinfo_tlv *tlv);
-static void update_crc(u8 *eeprom);
-static int prog_eeprom(int devnum, u8 *eeprom);
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
static int set_mac(char *buf, const char *string);
@@ -55,18 +51,6 @@ static inline bool is_digit(char c)
return (c >= '0' && c <= '9');
}
-/**
- * is_valid_tlv
- *
- * Perform basic sanity checks on a TLV field. The TLV is pointed to
- * by the parameter provided.
- * 1. The type code is not reserved (0x00 or 0xFF)
- */
-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
-{
- return((tlv->type != 0x00) && (tlv->type != 0xFF));
-}
-
/**
* is_hex
*
@@ -80,14 +64,12 @@ static inline u8 is_hex(char p)
}
/**
- * is_checksum_valid
- *
* Validate the checksum in the provided TlvInfo EEPROM data. First,
* verify that the TlvInfo header is valid, then make sure the last
* TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
* and compare it to the value stored in the EEPROM CRC-32 TLV.
*/
-static bool is_checksum_valid(u8 *eeprom)
+bool tlvinfo_check_crc(u8 *eeprom)
{
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_crc;
@@ -134,11 +116,11 @@ static int read_eeprom(int devnum, u8 *eeprom)
// If the contents are invalid, start over with default contents
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
- !is_checksum_valid(eeprom)) {
+ !tlvinfo_check_crc(eeprom)) {
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
eeprom_hdr->version = TLV_INFO_VERSION;
eeprom_hdr->totallen = cpu_to_be16(0);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
}
#ifdef DEBUG
@@ -180,7 +162,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
tlv_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
while (curr_tlv < tlv_end) {
eeprom_tlv = to_entry(&eeprom[curr_tlv]);
- if (!is_valid_tlv(eeprom_tlv)) {
+ if (!is_valid_tlvinfo_entry(eeprom_tlv)) {
printf("Invalid TLV field starting at EEPROM offset %d\n",
curr_tlv);
return;
@@ -190,7 +172,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
}
printf("Checksum is %s.\n",
- is_checksum_valid(eeprom) ? "valid" : "invalid");
+ tlvinfo_check_crc(eeprom) ? "valid" : "invalid");
#ifdef DEBUG
printf("EEPROM dump: (0x%x bytes)", TLV_INFO_MAX_LEN);
@@ -337,13 +319,13 @@ static void decode_tlv(struct tlvinfo_tlv *tlv)
}
/**
- * update_crc
+ * tlvinfo_update_crc
*
* This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
* one is added. This function should be called after each update to the
* EEPROM structure, to make sure the CRC is always correct.
*/
-static void update_crc(u8 *eeprom)
+void tlvinfo_update_crc(u8 *eeprom)
{
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_crc;
@@ -373,20 +355,20 @@ static void update_crc(u8 *eeprom)
}
/**
- * prog_eeprom
+ * write_tlvinfo_tlv_eeprom
*
- * Write the EEPROM data from CPU memory to the hardware.
+ * Write the TLV data from CPU memory to the hardware.
*/
-static int prog_eeprom(int devnum, u8 *eeprom)
+int write_tlvinfo_tlv_eeprom(void *eeprom, int dev)
{
int ret = 0;
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
int eeprom_len;
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
- ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
+ ret = write_tlv_eeprom(eeprom, eeprom_len, dev);
if (ret) {
printf("Programming failed.\n");
return -1;
@@ -459,13 +441,13 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
if (argc == 2) {
switch (cmd) {
case 'w': /* write */
- prog_eeprom(current_dev, eeprom);
+ write_tlvinfo_tlv_eeprom(eeprom, current_dev);
break;
case 'e': /* erase */
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
eeprom_hdr->version = TLV_INFO_VERSION;
eeprom_hdr->totallen = cpu_to_be16(0);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
printf("EEPROM data in memory reset.\n");
break;
case 'l': /* list */
@@ -546,7 +528,7 @@ U_BOOT_CMD(tlv_eeprom, 4, 1, do_tlv_eeprom,
* An offset from the beginning of the EEPROM is returned in the
* eeprom_index parameter if the TLV is found.
*/
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
+bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
{
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
struct tlvinfo_tlv *eeprom_tlv;
@@ -558,7 +540,7 @@ static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
eeprom_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
while (*eeprom_index < eeprom_end) {
eeprom_tlv = to_entry(&eeprom[*eeprom_index]);
- if (!is_valid_tlv(eeprom_tlv))
+ if (!is_valid_tlvinfo_entry(eeprom_tlv))
return false;
if (eeprom_tlv->type == tcode)
return true;
@@ -591,7 +573,7 @@ static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code)
eeprom_hdr->totallen =
cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) -
tlength);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
return true;
}
return false;
@@ -692,7 +674,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval)
// Update the total length and calculate (add) a new CRC-32 TLV
eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) +
ENT_SIZE + new_tlv_len);
- update_crc(eeprom);
+ tlvinfo_update_crc(eeprom);
return true;
}
@@ -983,7 +965,7 @@ int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
be16_to_cpu(tlv_hdr->totallen), dev_num);
if (ret < 0)
return ret;
- if (!is_checksum_valid(eeprom))
+ if (!tlvinfo_check_crc(eeprom))
return -EINVAL;
*hdr = tlv_hdr;
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
index aa96c9e8d4..eeb8af57f1 100644
--- a/include/tlv_eeprom.h
+++ b/include/tlv_eeprom.h
@@ -111,6 +111,51 @@ int write_tlv_eeprom(void *eeprom, int len, int dev);
int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
struct tlvinfo_tlv **first_entry, int dev);
+/**
+ * Write TLV data to the EEPROM.
+ *
+ * - Only writes length of actual tlv data
+ * - updates checksum
+ *
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
+ * of size at least TLV_INFO_MAX_LEN.
+ * @dev : EEPROM device to write
+ *
+ */
+int write_tlvinfo_tlv_eeprom(void *eeprom, int dev);
+
+/**
+ * tlvinfo_find_tlv
+ *
+ * This function finds the TLV with the supplied code in the EERPOM.
+ * An offset from the beginning of the EEPROM is returned in the
+ * eeprom_index parameter if the TLV is found.
+ */
+bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
+
+/**
+ * tlvinfo_update_crc
+ *
+ * This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
+ * one is added. This function should be called after each update to the
+ * EEPROM structure, to make sure the CRC is always correct.
+ *
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
+ * of size at least TLV_INFO_MAX_LEN.
+ */
+void tlvinfo_update_crc(u8 *eeprom);
+
+/**
+ * Validate the checksum in the provided TlvInfo EEPROM data. First,
+ * verify that the TlvInfo header is valid, then make sure the last
+ * TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
+ * and compare it to the value stored in the EEPROM CRC-32 TLV.
+ *
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
+ * of size at least TLV_INFO_MAX_LEN.
+ */
+bool tlvinfo_check_crc(u8 *eeprom);
+
#else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
@@ -150,4 +195,16 @@ static inline bool is_valid_tlvinfo_header(struct tlvinfo_header *hdr)
(be16_to_cpu(hdr->totallen) <= TLV_TOTAL_LEN_MAX));
}
+/**
+ * is_valid_tlv
+ *
+ * Perform basic sanity checks on a TLV field. The TLV is pointed to
+ * by the parameter provided.
+ * 1. The type code is not reserved (0x00 or 0xFF)
+ */
+static inline bool is_valid_tlvinfo_entry(struct tlvinfo_tlv *tlv)
+{
+ return((tlv->type != 0x00) && (tlv->type != 0xFF));
+}
+
#endif /* __TLV_EEPROM_H_ */

56
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@ -0,0 +1,56 @@
From 04ce313a110bae4262684666c245443182d6f0bc Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Mar 2022 11:11:25 +0200
Subject: [PATCH] cmd: tlv_eeprom: remove empty function implementations from
header
tlv_eeprom exposed functions are independent from platforms, hence no
stubs are required.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
include/tlv_eeprom.h | 24 ++----------------------
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
index eeb8af57f1..201a2b44af 100644
--- a/include/tlv_eeprom.h
+++ b/include/tlv_eeprom.h
@@ -65,7 +65,8 @@ struct __attribute__ ((__packed__)) tlvinfo_tlv {
#define TLV_CODE_VENDOR_EXT 0xFD
#define TLV_CODE_CRC_32 0xFE
-#if CONFIG_IS_ENABLED(CMD_TLV_EEPROM)
+/* how many EEPROMs can be used */
+#define TLV_MAX_DEVICES 2
/**
* read_tlv_eeprom - Read the EEPROM binary data from the hardware
@@ -156,27 +157,6 @@ void tlvinfo_update_crc(u8 *eeprom);
*/
bool tlvinfo_check_crc(u8 *eeprom);
-#else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
-
-static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
-{
- return -ENOTSUPP;
-}
-
-static inline int write_tlv_eeprom(void *eeprom, int len)
-{
- return -ENOTSUPP;
-}
-
-static inline int
-read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
- struct tlvinfo_tlv **first_entry, int dev)
-{
- return -ENOTSUPP;
-}
-
-#endif /* CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
-
/**
* is_valid_tlvinfo_header
*

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From 40355952340169930bfbd03a6ea4de3041c39754 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Mar 2022 12:07:38 +0200
Subject: [PATCH] lib: tlv_eeprom: add function for reading one entry into a C
string
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
include/tlv_eeprom.h | 12 ++++++++++++
lib/tlv/tlv_eeprom.c | 23 +++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
index ee9f035c8c..c91618e480 100644
--- a/include/tlv_eeprom.h
+++ b/include/tlv_eeprom.h
@@ -167,6 +167,18 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval);
*/
bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
+/**
+ * Read the TLV entry with specified code to a buffer as terminated C string.
+ * @eeprom: Pointer to buffer holding the TLV EEPROM binary data.
+ * @code: The TLV Code of the entry to read.
+ * @buffer: Pointer to buffer where the value will be stored. Must have capacity
+ * for the string representation of the data including null terminator.
+ * @length: size of the buffer where the value will be stored.
+ *
+ * Return length of string on success, -1 on error.
+ */
+ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length);
+
/**
* tlvinfo_update_crc
*
diff --git a/lib/tlv/tlv_eeprom.c b/lib/tlv/tlv_eeprom.c
index fe164cabe6..e2c7a0d664 100644
--- a/lib/tlv/tlv_eeprom.c
+++ b/lib/tlv/tlv_eeprom.c
@@ -349,6 +349,29 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval)
return true;
}
+/**
+ * Read the TLV entry with specified code to a buffer as terminated C string.
+ */
+ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length) {
+ int index;
+ struct tlvinfo_tlv *tlv;
+
+ // read sku from part-number field
+ if(tlvinfo_find_tlv(eeprom, code, &index)) {
+ tlv = (struct tlvinfo_tlv *) &eeprom[index];
+ if(tlv->length > length) {
+ pr_err("%s: tlv value (%d) larger than buffer (%zu)!\n", __func__, tlv->length+1, length);
+ return -1;
+ }
+ memcpy(buffer, tlv->value, tlv->length);
+ buffer[tlv->length] = 0;
+
+ return tlv->length;
+ }
+
+ return -1;
+}
+
/**
* set_mac
*

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@ -0,0 +1,111 @@
From 79df8e99fb5cc4c0e2716b1051302f72df28ee04 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 13 Mar 2022 10:54:15 +0200
Subject: [PATCH] add SoM and Carrier eeproms
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm/dts/cn9130-cex7-A.dts | 11 ++++++-----
arch/arm/dts/cn9130-cf-base.dts | 20 +++++++++++++++-----
arch/arm/dts/cn9130-cf-pro.dts | 20 +++++++++++++++-----
3 files changed, 36 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/cn9130-cex7-A.dts b/arch/arm/dts/cn9130-cex7-A.dts
index 2db0fc802e..209e485822 100644
--- a/arch/arm/dts/cn9130-cex7-A.dts
+++ b/arch/arm/dts/cn9130-cex7-A.dts
@@ -147,12 +147,13 @@
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
- eeprom0: eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- pagesize = <0x20>;
- };
+ /* M24C0x-MWN */
+ com_eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <0x10>;
+ };
};
&cp0_i2c1 {
diff --git a/arch/arm/dts/cn9130-cf-base.dts b/arch/arm/dts/cn9130-cf-base.dts
index a9d4a4491f..355c9d8ed0 100644
--- a/arch/arm/dts/cn9130-cf-base.dts
+++ b/arch/arm/dts/cn9130-cf-base.dts
@@ -145,11 +145,7 @@
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
- eeprom0: eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x53>;
- pagesize = <0x20>;
- };
+
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@@ -225,6 +221,20 @@
line-name = "m.2 devslp";
};
};
+
+ /* 24AA025UID */
+ carrier_eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <8>;
+ };
+
+ /* M24C02-WMN6TP */
+ som_eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
};
&cp0_i2c1 {
diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
index fb37dd833d..6931818cf6 100644
--- a/arch/arm/dts/cn9130-cf-pro.dts
+++ b/arch/arm/dts/cn9130-cf-pro.dts
@@ -145,11 +145,7 @@
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
- eeprom0: eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x53>;
- pagesize = <0x20>;
- };
+
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@@ -231,6 +227,20 @@
line-name = "m.2 devslp";
};
};
+
+ /* 24AA025UID */
+ carrier_eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <8>;
+ };
+
+ /* M24C02-WMN6TP */
+ som_eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
};
&cp0_i2c1 {

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@ -0,0 +1,143 @@
From a4fce9816a992f26044cef488b2617d7006535c2 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 13 Mar 2022 12:42:28 +0200
Subject: [PATCH] find fdtfile from tlv eeprom
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
board/Marvell/octeontx2_cn913x/board.c | 97 ++++++++++++++++++++++++++
configs/sr_cn913x_cex7_defconfig | 2 +
2 files changed, 99 insertions(+)
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
index 27db37e86e..1e900d2aab 100644
--- a/board/Marvell/octeontx2_cn913x/board.c
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -8,11 +8,13 @@
#include <common.h>
#include <console.h>
#include <dm.h>
+#include <env.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <power/regulator.h>
+#include <tlv_eeprom.h>
#ifdef CONFIG_BOARD_CONFIG_EEPROM
#include <mvebu/cfg_eeprom.h>
#endif
@@ -121,8 +123,103 @@ static int init_bootcmd_console(void)
}
#endif
+/*
+ * Read TLV formatted data from eeprom.
+ * Only read as much data as indicated by the TLV header.
+ */
+// TODO: this should be a library function?!
+static bool get_tlvinfo_from_eeprom(int index, u8 *buffer, size_t length) {
+ struct tlvinfo_header *eeprom_hdr = (struct tlvinfo_header *) buffer;
+ struct tlvinfo_tlv *eeprom_tlv = (struct tlvinfo_tlv *) &buffer[sizeof(struct tlvinfo_header)];
+
+ if(length < TLV_INFO_HEADER_SIZE) {
+ pr_err("%s: buffer too small for tlv header!\n", __func__);
+ return false;
+ }
+ if(read_tlv_eeprom((void *)eeprom_hdr, 0, TLV_INFO_HEADER_SIZE, index) != 0) {
+ pr_err("%s: failed to read from eeprom!\n", __func__);
+ return false;
+ }
+ if(!is_valid_tlvinfo_header(eeprom_hdr)) {
+ pr_warn("%s: invalid tlv header!\n", __func__);
+ return false;
+ }
+ if(length - TLV_INFO_HEADER_SIZE < be16_to_cpu(eeprom_hdr->totallen)) {
+ pr_err("%s: buffer too small for tlv data!\n", __func__);
+ return false;
+ }
+ if(read_tlv_eeprom((void *)eeprom_tlv, sizeof(struct tlvinfo_header), be16_to_cpu(eeprom_hdr->totallen), index) != 0) {
+ pr_err("%s: failed to read from eeprom!\n", __func__);
+ return false;
+ }
+
+ return true;
+}
+
+static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
+ char cpu[5] = {0};
+ char carrier[8] = {0};
+ static u8 eeprom[TLV_INFO_MAX_LEN];
+ char sku[257];
+
+ for(int i = 0; i < 2;i++) {
+ // read eeprom
+ if(!get_tlvinfo_from_eeprom(i, eeprom, sizeof(eeprom))) {
+ pr_info("%s: failed to read eeprom %d\n", __func__, i);
+ continue;
+ }
+
+ // read sku
+ if(!tlvinfo_read_tlv(eeprom, TLV_CODE_PART_NUMBER, sku, sizeof(sku))) {
+ pr_warn("%s: could not find sku in eeprom\n", __func__);
+ continue;
+ }
+ pr_debug("%s: read sku %s\n", __func__, sku);
+
+ // parse sku - processor or carrier indicated at index 2-6
+ if(memcmp(&sku[2], "CFCB", 4) == 0) {
+ // Clearfog Base
+ strcpy(carrier, "cf-base");
+ } else if(memcmp(&sku[2], "CFCP", 4) == 0) {
+ // Clearfog Pro
+ strcpy(carrier, "cf-pro");
+ } else if(memcmp(&sku[2], "C", 1) == 0) {
+ // COM-Express 7 - C9130 / C9131 / C9132 ...
+ memcpy(cpu, &sku[3], 4);
+ strcpy(carrier, "cex7");
+ } else if(memcmp(&sku[2], "S9130", 4) == 0) {
+ // SoM - S9130 / S9131 / S9132 ...
+ memcpy(cpu, &sku[3], 4);
+ } else {
+ pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
+ }
+ }
+
+ if(!cpu[0]) {
+ pr_err("%s: could not identify SoC, defaulting to %s!\n", __func__, "CN9130");
+ strcpy(cpu, "9130");
+ }
+
+ if(!carrier[0]) {
+ pr_err("%s: could not identify carrier, defaulting to %s!\n", __func__, "Clearfog Pro");
+ strcpy(carrier, "cf-pro");
+ }
+
+ // assemble fdtfile
+ if(snprintf(buffer, length, "marvell/cn%s-%s.dtb", cpu, carrier) >= length) {
+ pr_err("%s: fdtfile buffer too small, result truncated!\n", __func__);
+ }
+}
+
int board_late_init(void)
{
+ char fdtfile[32] = {0};
+
+ // identify device
+ get_fdtfile_from_tlv_eeprom(fdtfile, sizeof(fdtfile));
+ if (!env_get("fdtfile"))
+ env_set("fdtfile", fdtfile);
+
#if CONFIG_IS_ENABLED(OCTEONTX_SERIAL_BOOTCMD)
if (init_bootcmd_console())
printf("Failed to init bootcmd input\n");
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index 307cefef65..f971d9d4d0 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -102,3 +102,5 @@ CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SMBIOS_MANUFACTURER=""
CONFIG_OF_BOARD_FIXUP=y
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
+CONFIG_I2C_EEPROM=y
+CONFIG_CMD_TLV_EEPROM=y

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From 6516e51970deea70b79ebff44ad704b2be08e3fb Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Sun, 20 Mar 2022 15:02:03 +0200
Subject: [PATCH] octeontx2_cn913x: support distro-boot
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
configs/sr_cn913x_cex7_defconfig | 1 -
include/configs/octeontx2_cn913x.h | 12 ++++++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index f971d9d4d0..30e51c0026 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -11,7 +11,6 @@ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_BOOTCOMMAND="run get_images; run set_bootargs; booti $kernel_addr $ramfs_addr $fdt_addr"
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
index 2ae70e5efe..aa966bd292 100644
--- a/include/configs/octeontx2_cn913x.h
+++ b/include/configs/octeontx2_cn913x.h
@@ -35,6 +35,18 @@
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=" CONFIG_DEFAULT_CONSOLE "\0"\
+ "kernel_addr_r=0x7000000\0" \
+ "fdt_addr_r=0x6f00000\0" \
+ "ramdisk_addr_r=0x9000000\0" \
+ "scriptaddr=0x6e00000\0" \
+ "pxefile_addr_r=0x6000000\0" \
+ BOOTENV
+
/* RTC configuration */
#ifdef CONFIG_MARVELL_RTC
#define ERRATA_FE_3124064

35
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0015-octeontx2_cn913x-remove-console-variable.patch Normal file
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@ -0,0 +1,35 @@
From 03297ee2679e39da71dd39fb3076b305621c45d5 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Tue, 22 Mar 2022 11:09:06 +0200
Subject: [PATCH] octeontx2_cn913x: remove console variable
console is now properly selected by chosen nodei n device-tree rather
than through bootargs.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
include/configs/octeontx2_cn913x.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
index aa966bd292..d01644fcb5 100644
--- a/include/configs/octeontx2_cn913x.h
+++ b/include/configs/octeontx2_cn913x.h
@@ -8,9 +8,6 @@
#ifndef _CONFIG_OCTEONTX2_CN913X_H
#define _CONFIG_OCTEONTX2_CN913X_H
-#define CONFIG_DEFAULT_CONSOLE "console=ttyS0,115200 "\
- "earlycon=uart8250,mmio32,0xf0512000"
-
#include <configs/mvebu_armada-common.h>
/*
@@ -39,7 +36,6 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" CONFIG_DEFAULT_CONSOLE "\0"\
"kernel_addr_r=0x7000000\0" \
"fdt_addr_r=0x6f00000\0" \
"ramdisk_addr_r=0x9000000\0" \

19
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0016-octeontx2_cn913x-enable-mmc-partconf-command.patch Normal file
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@ -0,0 +1,19 @@
From 11a0fbc3e0ab35fbb5620e59fa65b201df26eabd Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Tue, 22 Mar 2022 11:12:12 +0200
Subject: [PATCH] octeontx2_cn913x: enable mmc partconf command
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
configs/sr_cn913x_cex7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index 30e51c0026..24219ef45d 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -103,3 +103,4 @@ CONFIG_OF_BOARD_FIXUP=y
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
CONFIG_I2C_EEPROM=y
CONFIG_CMD_TLV_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y

783
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0017-uboot-add-support-cn9131-cf-solidwan.patch Normal file
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@ -0,0 +1,783 @@
From c6279eb32f1d4f295c8f0335f4586ff92d3e4439 Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Thu, 7 Jul 2022 21:58:29 +0300
Subject: [PATCH] uboot: add support cn9131-cf-solidwan
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
---
arch/arm/dts/Makefile | 7 +-
arch/arm/dts/armada-cp110.dtsi | 14 +
arch/arm/dts/cn9130-cf-solidwan.dts | 382 +++++++++++++++++++++++++
arch/arm/dts/cn9130-som.dtsi | 9 +
arch/arm/dts/cn9131-cf-solidwan.dts | 50 ++++
arch/arm/dts/cn9131-cf-solidwan.dtsi | 214 ++++++++++++++
board/Marvell/octeontx2_cn913x/board.c | 8 +-
configs/sr_cn913x_cex7_defconfig | 1 +
8 files changed, 683 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/cn9130-cf-solidwan.dts
create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dts
create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 246bd4665e..db8f42d94d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -242,7 +242,12 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9132-db-C.dtb \
cn9132-cex7-A.dtb \
cn9130-cf-pro.dtb \
- cn9130-cf-base.dtb
+ cn9130-cf-base.dtb \
+ cn9130-bldn-mbv.dtb \
+ cn9131-bldn-mbv.dtb \
+ cn9130-cf-solidwan.dtb \
+ cn9131-cf-solidwan.dtb
+
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
index af55c5573d..6abe8f0bea 100644
--- a/arch/arm/dts/armada-cp110.dtsi
+++ b/arch/arm/dts/armada-cp110.dtsi
@@ -31,6 +31,11 @@
compatible = "simple-bus";
ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
+
+/* CP110_LABEL(ser1): ser@15
+
+*/
+
CP110_LABEL(mdio): mdio@12a200 {
#address-cells = <1>;
#size-cells = <0>;
@@ -39,6 +44,15 @@
mdio-name = CP110_STRING_LABEL(mdio);
status = "disabled";
};
+ CP110_LABEL(mdio2): mdio@12a400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ mdio-name = CP110_STRING_LABEL(mdio);
+ status = "disabled";
+ };
+
CP110_LABEL(xmdio): mdio@12a600 {
#address-cells = <1>;
diff --git a/arch/arm/dts/cn9130-cf-solidwan.dts b/arch/arm/dts/cn9130-cf-solidwan.dts
new file mode 100644
index 0000000000..c26bb15af9
--- /dev/null
+++ b/arch/arm/dts/cn9130-cf-solidwan.dts
@@ -0,0 +1,382 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-cex7-A.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+ model = "SolidRun CN9130 based SOM ClearFog SolidWAN ";
+ compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+ "marvell,cn9030", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806", "marvell,armada70x0";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp0_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ sdhci@780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+ ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap_mmc_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+ gpio@440100 {
+ p24 {
+ gpio-hog;
+ gpios = <24 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "switch_reset";
+ };
+ };
+ };
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+ vqmmc-supply = <&ap_reg_mmc_vccq>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+/*
+&cp0_uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart1_pins>;
+ u-boot,dm-pre-reloc;
+};
+*/
+
+/****** CP related configuration ******/
+
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-1] SMI MDC/MDIO
+ * [2-3] UART1 TX/RX
+ * [4-5] UART1 RTS/CTS
+ * [6-8] PTP
+ * [10-11] GPIO - SPD Strap
+ * [12-16] SPI1
+ * [17-26] GPIO - Boot straps
+ * [27-34] GPIO
+ * [35-36] I2C1
+ * [37-38] I2C1
+ * [39] GPIO
+ * [40] RCVR CLK
+ * [41] GPIO VHV_EN
+ * [43] SD CARD DT
+ * [44-55] RGMII --> GPIOs
+ * [56-61] SDIO
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 10 10 8 8 6 6 0 0 0 0
+ 0 0 3 3 3 3 3 0 0 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 2 2 2 2 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0xe 0xe 0xe 0xe
+ 0xe 0xe 0 >;
+};
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ eeprom0: eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ /* connected to SFP0*/
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ status = "okay";
+ no-1-8-v;
+};
+
+/* SPI NOR */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins
+ &cp0_spi1_cs1_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0x2000000 0x1000004>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <20000000>;
+ };
+ spi-flash@1 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x1>;
+ /* On carrier MUX does not allow higher frequencies */
+ spi-max-frequency = <20000000>;
+ };
+
+
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_PEX2>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SRDS #0 - PCIe X1 Gen3 M.2 Slot */
+&cp0_pcie0 {
+ num-lanes = <1>;
+ status = "okay";
+// pinctrl-0 = <&cp0_pci0_reset_pins>;
+// marvell,reset-gpio = <&cp0_gpio0 6 GPIO_ACTIVE_LOW>; //MPP6
+};
+
+/* SRDS #1 - 1GbE SGMII */
+&cp0_eth2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&cp0_phy1>;
+ // phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
+};
+
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_i2c1>;
+ los-gpio = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
+ mod-def0-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; //MPP32
+ tx-disable-gpio = <&cp0_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
+ tx-fault-gpio = <&cp0_gpio0 31 GPIO_ACTIVE_HIGH>; //MPP31
+ maximum-power-milliwatt = <2000>;
+};
+
+/* SRDS #3 - 1GE PHY over SGMII */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&cp0_phy0>;
+ phy-mode = "sgmii";
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
+};
+
+/* SRDS #4 - USB 3.0 host on M.2 connector */
+&cp0_usb3_1 {
+ status = "okay";
+ vbus-supply = <&cp0_reg_usb3_vbus1>;
+};
+&cp0_utmi0 {
+ status = "okay";
+};
+&cp0_utmi1 {
+ status = "okay";
+};
+/*
+&cp0_usb3_0 {
+ status = "okay";
+ vbus-supply = <&cp0_reg_usb3_vbus0>;
+};
+*/
+
+/* SRDS #5 - mini PCIE slot */
+&cp0_pcie2 {
+ num-lanes = <1>;
+ status = "okay";
+// pinctrl-0 = <&cp0_pci2_reset_pins>;
+// marvell,reset-gpio = <&cp0_gpio0 8 GPIO_ACTIVE_LOW>; //MPP6
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_mdio_pins>;
+ cp0_phy0: ethernet-phy@0 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+ cp0_phy1: ethernet-phy@1 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <1>;
+ };
+};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = < 43 >;
+ marvell,function = <1>;
+ };
+ cp0_spi1_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+ cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+ marvell,pins = < 12 >;
+ marvell,function = <3>;
+ };
+ cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = < 0 1 >;
+ marvell,function = <10>;
+ };
+ cp0_pci0_reset_pins: pci0-reset-pins {
+ marvell,pins = < 6 >;
+ marvell,function = <0>;
+ };
+ cp0_pci2_reset_pins: pci2-reset-pins {
+ marvell,pins = < 8 >;
+ marvell,function = <0>;
+ };
+ cp0_uart1_pins: cp0-uart1-pins {
+ marvell,pins = < 2 3 >;
+ marvell,function = <8>;
+ };
+};
diff --git a/arch/arm/dts/cn9130-som.dtsi b/arch/arm/dts/cn9130-som.dtsi
index 683821e0ea..ca69cd3ba0 100644
--- a/arch/arm/dts/cn9130-som.dtsi
+++ b/arch/arm/dts/cn9130-som.dtsi
@@ -12,6 +12,15 @@
#include "armada-ap807.dtsi"
#include "armada-ap80x-quad.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+
+
/* This defines used to calculate the base address of each CP */
#define CP110_BASE_OFFSET (0xf2000000)
#define CP110_SPACE_SIZE (0x02000000)
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dts b/arch/arm/dts/cn9131-cf-solidwan.dts
new file mode 100644
index 0000000000..95c3aec3c5
--- /dev/null
+++ b/arch/arm/dts/cn9131-cf-solidwan.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9131-cex7-A */
+
+#include "cn9130-cf-solidwan.dts"
+#include "cn9131-cf-solidwan.dtsi"
+
+/ {
+ model = "Belden CN9131 based Platform";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp1_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe
+ * Lane 1: SATA
+ * Lane 2: USB3
+ * Lane 3: SGMII
+ * Lane 4: XFI
+ * Lane 5: SGMII
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+
+ };
+};
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dtsi b/arch/arm/dts/cn9131-cf-solidwan.dtsi
new file mode 100644
index 0000000000..5f2ee49850
--- /dev/null
+++ b/arch/arm/dts/cn9131-cf-solidwan.dtsi
@@ -0,0 +1,214 @@
+/*
+* Copyright (C) 2020 SolidRun ltd.
+*
+* SPDX-License-Identifier: GPL-2.0
+* https://spdx.org/licenses
+*/
+
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1 */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME cp1
+#define CP110_NUM 1
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "SolidRun CN9131 based SolidWan";
+ compatible = "marvell,cn9131-db";
+
+ aliases {
+ gpio3 = &cp1_gpio0;
+ gpio4 = &cp1_gpio1;
+ fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
+ fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
+ };
+
+ cp1 {
+ config-space {
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+// pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+ };
+ cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+// pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+// gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+&cp1_ld_efuse0 {
+ status = "disabled";
+};
+
+&cp1_ld_efuse1 {
+ status = "disabled";
+};
+
+&cp1_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c1_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+
+&cp1_utmi0 {
+ status = "okay";
+};
+&cp1_utmi1 {
+ status = "okay";
+};
+/*
+&cp1_usb3_1 {
+ status = "okay";
+ vbus-supply = <&cp1_reg_usb3_vbus1>;
+};
+*/
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ status = "okay";
+ num-lanes = <1>;
+ /* non-prefetchable memory */
+ ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+// pinctrl-names = "default";
+// marvell,reset-gpio = <&cp1_gpio0 29 GPIO_ACTIVE_LOW>;
+};
+
+&cp1_pinctl {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,cp115-standalone-pinctrl";
+ bank-name ="cp1-110";
+
+ /* MPP Bus:
+ * [1:0] UART0
+ * [29:2] NC
+ * [30:29] GPIO - M.2 Power off
+ * [32:31] NC
+ * [34:33] SFP GPIOs
+ * [36:35] I2C
+ * [38:37] SMI
+ * [41:40] UART1
+ * [48:42] NC
+ * [50:49] SFP GPIOs
+ * [62:51] NC
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x2 0x2 0x7 0x7 0x0
+ 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 >;
+
+ cp1_uart0_pins: cp1-uart0-pins-1 {
+ marvell,pins = < 0 1 >;
+ marvell,function = <8>;
+ };
+ cp1_uart1_pins: cp1-uart1-pins-1 {
+ marvell,pins = < 40 41 >;
+ marvell,function = <7>;
+ };
+
+ cp1_i2c1_pins: cp1-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+
+ cp1_mdio_pins: cp1-mdio-pins {
+ marvell,pins = < 37 38 >;
+ marvell,function = <7>;
+ };
+
+
+};
+
+&cp1_mdio2 {
+ status = "okay";
+ pinctrl-0 = <&cp1_mdio_pins>;
+ cp1_phy0: ethernet-phy@0 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+ cp1_phy1: ethernet-phy@1 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <1>;
+ };
+};
+
+/* SATA0 */
+&cp1_sata0 {
+ status = "okay";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c1>;
+ los-gpio = <&cp1_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
+ mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
+ tx-disable-gpio = <&cp1_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
+ tx-fault-gpio = <&cp1_gpio1 17 GPIO_ACTIVE_HIGH>; //MPP49
+ maximum-power-milliwatt = <2000>;
+};
+
+/* SERDES 3 SGMII */
+&cp1_eth1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&cp1_phy0>;
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
+};
+
+/* SERDES 5 SGMII */
+&cp1_eth2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy = <&cp1_phy1>;
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
+};
+
+/* M.2 LTE USB */
+&cp1_usb3_0 {
+ status = "okay";
+ vbus-supply = <&cp1_reg_usb3_vbus0>;
+};
+
+
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
index 1e900d2aab..cfd8d5f5fd 100644
--- a/board/Marvell/octeontx2_cn913x/board.c
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -188,8 +188,14 @@ static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
memcpy(cpu, &sku[3], 4);
strcpy(carrier, "cex7");
} else if(memcmp(&sku[2], "S9130", 4) == 0) {
- // SoM - S9130 / S9131 / S9132 ...
+ // SoM - S9130
memcpy(cpu, &sku[3], 4);
+ } else if(memcmp(&sku[2], "CFSW", 4) == 0) {
+ // SolidWan SOM S9131
+ strcpy(carrier, "cf-swn");
+ } else if(memcmp(&sku[2], "MBV", 3) == 0) {
+ //BLDN MBV S9131
+ strcpy(carrier, "bldn-mbv");
} else {
pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
}
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
index 24219ef45d..d7445e9476 100644
--- a/configs/sr_cn913x_cex7_defconfig
+++ b/configs/sr_cn913x_cex7_defconfig
@@ -104,3 +104,4 @@ CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
CONFIG_I2C_EEPROM=y
CONFIG_CMD_TLV_EEPROM=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_NET_RANDOM_ETHADDR=y

779
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0018-uboot-add-support-bldn-mbv.patch Normal file
View File

@ -0,0 +1,779 @@
From 70b50e2ac9671cbda2e9efd7ebef37eec66b8332 Mon Sep 17 00:00:00 2001
From: Alon Rotman <alon.rotman@solid-run.com>
Date: Thu, 7 Jul 2022 21:59:29 +0300
Subject: [PATCH] uboot: add support bldn-mbv
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
---
arch/arm/dts/cn9130-bldn-mbv.dts | 477 ++++++++++++++++++++++++++++++
arch/arm/dts/cn9131-bldn-mbv.dts | 46 +++
arch/arm/dts/cn9131-bldn-mbv.dtsi | 223 ++++++++++++++
3 files changed, 746 insertions(+)
create mode 100644 arch/arm/dts/cn9130-bldn-mbv.dts
create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dts
create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dtsi
diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
new file mode 100644
index 0000000000..9e10eab008
--- /dev/null
+++ b/arch/arm/dts/cn9130-bldn-mbv.dts
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9130-som.dts */
+#include "cn9130-som.dtsi"
+
+/ {
+ model = "Belden CN9130 based SOM and Carrier MBV-A/B";
+ compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+ "marvell,cn9030", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806", "marvell,armada70x0";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp0_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ sdhci@780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+ ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap_mmc_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ };
+ gpio@440100 {
+ p24 {
+ gpio-hog;
+ gpios = <24 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "switch_reset";
+ };
+ };
+ };
+};
+
+
+/***** AP related configuration *****/
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+
+/* on-board eMMC */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
+ vqmmc-supply = <&ap_reg_mmc_vccq>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+/*
+&cp0_uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_uart1_pins>;
+ u-boot,dm-pre-reloc;
+};
+*/
+
+/****** CP related configuration ******/
+
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-1] SMI MDC/MDIO
+ * [2-3] UART1 TX/RX
+ * [4-5] UART1 RTS/CTS - NC on carrier board
+ * [6-8] PTP
+ * [10-11] SPD Strap - GPIO
+ * [12-16] SPI1
+ * [17-26] Boot straps - GPIO
+ * [35-36] I2C1
+ * [37-38] I2C0
+ * [40] RCVR CLK - NC
+ * [41] VHV_EN - GPIO
+ * [43] SD CARD DT
+ * [44-55] RGMII
+ * [56-61] SDIO
+
+ ***** GPIOs connected to CPLD******
+ * [28] RESET_VSC8504_PHY
+ * [31] CPLD_RESET_VSC8254_PHY
+ * [32] INT_RELEASE
+ * [33] CPLD_STATUS_INT
+ * [34] CPLD_PWR_INT
+ * [39] RESET_EMMC
+ * [42] CPLD_DONE
+ * [43] CPLD_PROG_N
+
+
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0xa 0xa 8 8 6 6 9 9 9 0
+ 0 0 3 3 3 3 3 0 0 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 2 2 2 2 0
+ 2 0 0 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0 >;
+};
+
+
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ /* on som */
+ eeprom0: eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ pagesize = <0x20>;
+ };
+ /* on carrier */
+ eeprom1: eeprom@50 {
+ compatible = "i2c-eeprom";
+ reg = <0x50>;
+ pagesize = <0x16>;
+ };
+
+};
+
+&cp0_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ clock-frequency = <100000>;
+ rtc: rtc@68 {
+ reg = <68>;
+ compatible = "dallas,ds1339";
+ /*connected to rtc DS1339U-33+*/
+ };
+ i2c-switch@e6 {
+ compatible = "nxp,pca9543";
+ reg = <0xe6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c_sfp0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*connected to sfp cp0_eth0*/
+ };
+ i2c_sfp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /*connected to sfp cp1_eth1*/
+ };
+ };
+ temp_sns:temp_sense@40 {
+ reg = <40>;
+
+ };
+};
+
+/* SD CARD */
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ status = "okay";
+ no-1-8-v;
+ max-frequency = <25000000>;
+};
+
+/* SPI NOR */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins
+ &cp0_spi1_cs1_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0x2000000 0x1000004>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_PEX1>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_PEX2>;
+ };
+};
+
+&cp0_sata0 {
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "disabled";
+};
+
+
+&cp0_utmi0 {
+ status = "okay";
+};
+&cp0_utmi1 {
+ status = "okay";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+
+/* SRDS #0 - PCIe X1 mPCIe #0 */
+&cp0_pcie0 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+/* SRDS #1 - SGMII connected to VSC8584 1GbE PHY */
+&cp0_eth2 {
+ status = "okay";
+// phy = <&cp0_vsc_phy19>; //address 0x0011001
+ phy-mode = "sgmii";
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+ compatible = "sff,sfp";
+
+ /* for SFP direct connectivity */
+// i2c-bus = <&i2c_sfp0>;
+// mod-def0-gpio = <&cp0_gpio0 27 GPIO_ACTIVE_LOW>;
+
+ /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
+// phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+/* SRDS #3 - SGMII connected to VSC8584 1GbE PHY */
+
+&cp0_eth1 {
+ status = "okay";
+// phy = <&cp0_vsc_phy18>; //address 0x0011000
+ phy-mode = "sgmii";
+// phy = <&cp0_phy0>; // only for testing on cf-solidwan - to be removed for final dtb
+};
+
+/* SRDS #4 - Extenssion conector */
+&cp0_pcie1 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+/* SRDS #5 - Extenssion connector */
+&cp0_pcie2 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
+&cp0_mdio {
+ status = "disabled";
+ pinctrl-0 = <&cp0_mdio_pins>;
+
+ /** only for testing on cf-solidwan - to be removed for final dtb */
+/* cp0_phy0: ethernet-phy@0 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+ cp0_phy1: ethernet-phy@0 {
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+*/
+
+};
+
+&cp0_gpio0{
+ phy_vsc8504_phy_reset {
+ gpio-hog;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "phy_vsc8504_phy_reset";
+ };
+ phy_vsc8254_phy_reset {
+ gpio-hog;
+ gpios = <31 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "phy_vsc8254_phy_reset";
+ };
+};
+
+&cp0_gpio1{
+ cpld_int_release {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; //MPP32
+ output-high;
+ line-name = "cpld_int_release";
+ };
+ cpld_status_int {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; //MPP33
+ output-high;
+ line-name = "cpld_status_int";
+ };
+ cpld_pwr_int {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_HIGH>; //MPP34
+ output-high;
+ line-name = "cpld_pwr_int";
+ };
+ cpld_reset_emmc{
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>; //MPP39
+ output-high;
+ line-name = "cpld_reset_emmc";
+ };
+ cpld_done {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>; //MPP42
+ input;
+ line-name = "cpld_done";
+ };
+ cpld_prog_n {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>; //MPP43
+ output-high;
+ line-name = "cpld_prog_n";
+ };
+};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = < 43 >;
+ marvell,function = <1>;
+ };
+ cp0_spi1_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+ cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
+ marvell,pins = < 12 >;
+ marvell,function = <3>;
+ };
+ cp0_mdio_pins: cp0-mdio-pins {
+ marvell,pins = < 0 1 >;
+ marvell,function = <10>;
+ };
+ cp0_ptp_pins: cp0-ptp-pins {
+ marvell,pins = < 6 7 8 >;
+ marvell,function = <9>;
+ };
+ cp0_uart1_pins: cp0-uart1-pins {
+ marvell,pins = < 2 3 >;
+ marvell,function = <8>;
+ };
+};
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
new file mode 100644
index 0000000000..d10c7f032e
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2020 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/* cn9131-bldn mbv-a/b */
+#include "cn9130-bldn-mbv.dts"
+#include "cn9131-bldn-mbv.dtsi"
+
+/ {
+ model = "Belden CN9131 based Platform";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp1_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x1)
+ * Lane 1: USB3
+ * Lane 2: ETH PORT 10GE
+ * Lane 3: NC
+ * Lane 4: PCIE1 X1
+ * Lane 5: PCIe2 X1
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_PEX1>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_PEX2>;
+ };
+};
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dtsi b/arch/arm/dts/cn9131-bldn-mbv.dtsi
new file mode 100644
index 0000000000..afd63d8ba6
--- /dev/null
+++ b/arch/arm/dts/cn9131-bldn-mbv.dtsi
@@ -0,0 +1,223 @@
+/*
+* Copyright (C) 2020 SolidRun ltd.
+*
+* SPDX-License-Identifier: GPL-2.0
+* https://spdx.org/licenses
+*/
+
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1 */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME cp1
+#define CP110_NUM 1
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+/ {
+ model = "Belden CN9131 based MBV-A/B";
+ compatible = "marvell,cn9131-db";
+
+ aliases {
+ gpio3 = &cp1_gpio0;
+ gpio4 = &cp1_gpio1;
+ fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
+ fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
+ };
+ cp1 {
+ config-space {
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ };
+ cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ };
+
+ cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ };
+ };
+ };
+};
+
+&cp1_ld_efuse0 {
+ status = "disabled";
+};
+
+&cp1_ld_efuse1 {
+ status = "disabled";
+};
+
+&cp1_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c1_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp1_utmi0 {
+ status = "okay";
+};
+&cp1_utmi1 {
+ status = "okay";
+};
+
+&cp1_usb3_0 {
+ status = "disabled";
+};
+
+&cp1_xmdio {
+ status = "okay";
+ pinctrl-0 = <&cp1_xmdio_pins>;
+ cp0_sfi_phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ cp1_sfi_phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+};
+
+&cp1_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp1_mdio_pins>;
+ cp0_vsc_phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cp0_vsc_phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+
+&cp1_pinctl {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,cp115-standalone-pinctrl";
+ bank-name ="cp1-110";
+
+ /* MPP Bus:
+ * [3:2] xmdio
+ * [5:4] mdio
+ * [36:35] i2c1
+ * [43:40] rs232
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x0 0x0 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x2 0x2 0x0 0x0 0x0
+ 0x7 0x7 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 >;
+
+ cp1_i2c1_pins: cp1-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp1_xmdio_pins: cp1-xmdio-pins-0 {
+ marvell,pins = < 2 3 >;
+ marvell,function = <10>;
+ };
+ cp1_mdio_pins: cp1-mdio-pins-0 {
+ marvell,pins = < 4 5 >;
+ marvell,function = <10>;
+ };
+ cp1_uart1_pins: cp1-uart1-pins-0 {
+ marvell,pins = < 40 41 42 43 >;
+ marvell,function = <7>;
+ };
+};
+
+/* SATA0 */
+&cp1_sata0 {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* SRDS #0 - PCIe Extenssion card */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ status = "okay";
+ ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+};
+
+/* SRDS #1 - USB Extenssion card */
+&cp1_usb3_0 {
+ status = "okay";
+ vbus-supply = <&cp1_reg_usb3_vbus0>;
+};
+
+/* SRDS #2 - 10GE SFP+ */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+ compatible = "sff,sfp";
+
+ /* for SFP direct connectivity */
+// i2c-bus = <i2c_sfp1>;
+// mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
+// compatible = "sff,sfp";
+// maximum-power-milliwatt = <2000>;
+
+ /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
+ phy = <&cp1_sfi_phy9>; //address 0x01001
+
+};
+
+/* SRDS #3 - not in use */
+
+
+/* SRDS #4 - mPCIe */
+&cp1_pcie1 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+/* SRDS #5 - mPCIe */
+&cp1_pcie2 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+/*************** definitions of addresses for cp0 eth ports ************/
+
+&cp0_eth0 {
+ status = "okay";
+ phy = <&cp0_sfi_phy8>; //address 0x01000
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&cp0_vsc_phy18>; //address 0x0011000
+};
+
+&cp0_eth2 {
+ status = "okay";
+ phy = <&cp0_vsc_phy19>; //address 0x0011001
+};
+

66
layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/u-boot_2019.10-solidrun.bb Normal file
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@ -0,0 +1,66 @@
HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome"
DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \
ARM, MIPS and several other processors, which can be installed in a boot \
ROM and used to initialize and test the hardware or to download and run \
application code."
SECTION = "bootloaders"
DEPENDS += "flex-native bison-native"
COMPATIBLE_MACHINE = "cn913x"
LICENSE = "GPLv2+"
LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e"
PE = "1"
# We use the revision in order to avoid having to fetch it from the
# repo during parse
SRCREV = "61ba1244b548463dbfb3c5285b6b22e7c772c5bd"
# Patch from https://github.com/SolidRun/cn913x_build
# Git SHA: f33e2aeb01c7ee061be7b053035ae87ce30fce4a
SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
file://solidrun/0001-cmd-add-tlv_eeprom-command.patch \
file://solidrun/0002-cmd-tlv_eeprom.patch \
file://solidrun/0003-cmd-tlv_eeprom-remove-use-of-global-variable-current.patch \
file://solidrun/0004-cmd-tlv_eeprom-remove-use-of-global-variable-has_bee.patch \
file://solidrun/0005-cmd-tlv_eeprom-do_tlv_eeprom-stop-using-non-api-read.patch \
file://solidrun/0006-cmd-tlv_eeprom-convert-functions-used-by-command-to-.patch \
file://solidrun/0007-cmd-tlv_eeprom-remove-empty-function-implementations.patch \
file://solidrun/0008-cmd-tlv_eeprom-split-off-tlv-library-from-command.patch \
file://solidrun/0009-lib-tlv_eeprom-add-function-for-reading-one-entry-in.patch \
file://solidrun/0010-uboot-marvell-patches.patch \
file://solidrun/0011-uboot-support-cn913x-solidrun-paltfroms.patch \
file://solidrun/0012-add-SoM-and-Carrier-eeproms.patch \
file://solidrun/0013-find-fdtfile-from-tlv-eeprom.patch \
file://solidrun/0014-octeontx2_cn913x-support-distro-boot.patch \
file://solidrun/0015-octeontx2_cn913x-remove-console-variable.patch \
file://solidrun/0016-octeontx2_cn913x-enable-mmc-partconf-command.patch \
file://solidrun/0017-uboot-add-support-cn9131-cf-solidwan.patch \
file://solidrun/0018-uboot-add-support-bldn-mbv.patch \
file://0001-Remove-redundant-YYLOC-global-declaration.patch \
file://0001-sr_cn913x_cex7-enable-more-image-formats.patch \
file://0021-octeontx2_cn913x-increase-CONFIG_SYS_BOOTM_LEN-to-32.patch \
file://0001-sr_cn913x_cex7-enable-VERSION_VARIABLE.patch \
file://boot.cmd \
file://cn913x.cfg \
"
#
S = "${WORKDIR}/git"
require recipes-bsp/u-boot/u-boot.inc
# Solidrun patches require to build out-of-the-tree
B = "${WORKDIR}/build"
DEPENDS += "bc-native dtc-native u-boot-mkimage-native"
do_compile:prepend() {
export DEVICE_TREE="${UBOOT_BUILDENV_DEVICE_TREE}"
}
# compile boot.cmd into boot.scr
UBOOT_ENV_SUFFIX = "scr"
UBOOT_ENV = "boot"
SYSROOT_DIRS += " /boot "

23
layers/meta-belden-marvell-bsp/recipes-kernel/linux/linux-netmodule_git-5.15-solidrun.bb Normal file
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@ -0,0 +1,23 @@
DESCRIPTION = "Linux kernel for various NetModule hardware"
COMPATIBLE_MACHINE = "cn913x"
inherit kernel
SRC_URI = "git://gitlab.com/netmodule/kernel/linux-netmodule.git;protocol=ssh;user=git;branch=5.15/solidrun/base"
SRCREV ?= "be2f2f0c96e85ecec9d807397194e46bb8bea4a5"
LICENSE = "GPLv2"
LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
S = "${WORKDIR}/git"
#If a KERNEL_DEFCONFIG is specified, the defconfig specified in SRC_URI will be overwritten!
do_configure:append(){
if [ "${KERNEL_DEFCONFIG}" != "" ]; then
oe_runmake ${KERNEL_DEFCONFIG}
fi
configs="${@" ".join(find_cfgs(d))}"
if [ ! -z "${configs}" ]; then
${S}/scripts/kconfig/merge_config.sh -m -O ${WORKDIR}/build ${WORKDIR}/build/.config ${WORKDIR}/*.cfg
fi
}

22
layers/meta-belden-marvell-bsp/wic/cn913x-sdcard.wks Normal file
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@ -0,0 +1,22 @@
# short-description: Create OTA-enabled SD card image
# long-description: Creates a partitioned SD card image with OSTree
# offset 1S => 1 sector (1x512 byte)
# The bootloader can be at 5 different position: 1S, 34S, 4096S, 8192S, 12288S
# MBR disk use only the sector 0, so 1S is free
# GPT disk use sector 0-33S, so first free slot is 34S
# Current bootloader is about 1.8MB, so if we put it at 4096S and 12288S we
# have 4MiB between the first bootloader and the second copy of it
# tfa = TrustedFirmware-A
part --offset 4096S --source rawcopy --sourceparams="file=flash-image.bin"
part --offset 12288S --source rawcopy --sourceparams="file=flash-image.bin"
# Then we put the boot script 4MiB after the second copy of the bootloader
# We use the standard u-boot distro boot feature, so we need
# an ext2/3/4 or FAT partition marked with the MBR bootable flag, or
# GPT legacy_bios_bootable attribute - https://github.com/u-boot/u-boot/blob/v2019.10/doc/README.distro
part /boot/uboot-scr --offset 20480S --source bootimg-partition --fstype=ext4 --fixed-size=50M --active
# Then the rootfs
part / --source rootfs --label root --fstype=ext4

1
templates/bblayers.conf.sample
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@ -8,4 +8,5 @@ BBFILES ?= ""
BBLAYERS ?= " \
##OEROOT##/meta \
##OEROOT##/../meta-belden-coreos \
##OEROOT##/../meta-belden-marvell-bsp \
"

1
templates/local.conf.sample
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@ -25,6 +25,7 @@
#MACHINE ?= "qemuppc"
#MACHINE ?= "qemux86"
#MACHINE ?= "qemux86-64"
#MACHINE ?= "cn9130-cf-pro"
#
# This sets the default machine to be qemuarm64 if no other machine is selected:
MACHINE ??= "qemuarm64"