Pull request #113: Synchonize kirkstone with master
Merge in ICO/coreos from synchonize_kirkstone_with_master to kirkstone * commit '0f498e388e89d2e9db72e4edefd04b998aa32f2d': (24 commits) fix(coreos-keygen): add error-handling fix(3rd-party): automatic update of CoreOS submodules feat(efibootguard): single image with automatic partition switch feat(coreos-installer): add coreos-installer and emmc support feat(vscode): add more recommended extention docs(quick-build): change sbsign to sbsigntool, because the debian packet manager can not find sbsign fix(u-boot): revert to u-boot 2019.10 because of several issues with 2023.04 fix(3rd-party): automatic update of CoreOS submodules fix(linux-netmodule): add CVE_VERSION to recipe that the CVE checkeer can match the kernel version fix(swupdate): adjust bbapend to match new swupdate version feat(layers): move third party layers to external-layers fix(coreos-image-testable): phy firmware not available in coreos-image-testable fix(3rd-party): automatic update of CoreOS submodules fix(.gitmodules): fix branch name of meta-efibootguard fix(cn9131-bldn-mbv): fix IMAGE_INSTALL assignement refactor(cn9131): remove unnecessary files feat(cn913x): defconfig cleanup, solidrun kernel cfg additions, copper and sfp patch fix(cn9131-bldn-mbv): add phy firmware handling feat(wic): allow to configure the rootfs partition size fix(cn913x-bldn-mbv): fix machine and phy ...
This commit is contained in:
Patrick Vogelaar
commit
4ea91ae4ae
|
|
@ -4,3 +4,4 @@ documentation/_build/
|
|||
documentation/oe-logs
|
||||
documentation/oe-workdir
|
||||
__pycache__
|
||||
.venv/
|
||||
|
|
|
|||
|
|
@ -3,22 +3,22 @@
|
|||
url = ssh://git@bitbucket.gad.local:7999/ico/bitbake.git
|
||||
branch = 2.0
|
||||
[submodule "layers/openembedded-core"]
|
||||
path = layers/openembedded-core
|
||||
path = external-layers/openembedded-core
|
||||
url = ssh://git@bitbucket.gad.local:7999/ico/openembedded-core.git
|
||||
branch = kirkstone
|
||||
[submodule "layers/meta-openembedded"]
|
||||
path = layers/meta-openembedded
|
||||
path = external-layers/meta-openembedded
|
||||
url = ssh://git@bitbucket.gad.local:7999/ico/meta-openembedded.git
|
||||
branch = kirkstone
|
||||
[submodule "layers/meta-virtualization"]
|
||||
path = layers/meta-virtualization
|
||||
path = external-layers/meta-virtualization
|
||||
url = ssh://git@bitbucket.gad.local:7999/ico/meta-virtualization.git
|
||||
branch = kirkstone
|
||||
[submodule "layers/meta-efibootguard"]
|
||||
path = layers/meta-efibootguard
|
||||
path = external-layers/meta-efibootguard
|
||||
url = ssh://git@bitbucket.gad.local:7999/ico/meta-efibootguard.git
|
||||
branch = coreos/master
|
||||
branch = master
|
||||
[submodule "layers/meta-swupdate"]
|
||||
path = layers/meta-swupdate
|
||||
path = external-layers/meta-swupdate
|
||||
url = ssh://git@bitbucket.gad.local:7999/ico/meta-swupdate.git
|
||||
branch = kirkstone
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
{
|
||||
"recommendations": [
|
||||
"ms-vscode.makefile-tools",
|
||||
"timonwong.shellcheck"
|
||||
"timonwong.shellcheck",
|
||||
"eugenwiens.bitbake",
|
||||
"kweihmann.oelint-vscode",
|
||||
"lextudio.restructuredtext",
|
||||
"trond-snekvik.simple-rst"
|
||||
]
|
||||
}
|
||||
|
|
@ -3,7 +3,10 @@
|
|||
"**/build/cache/**": true,
|
||||
"**/build/downloads/**": true,
|
||||
"**/build/sstate-cache/**": true,
|
||||
"**/build/tmp/**": true
|
||||
"**/build/tmp/**": true,
|
||||
"**/documentation/_build/**": true,
|
||||
"**/build/workspace": true
|
||||
},
|
||||
"python.formatting.provider": "black"
|
||||
"python.formatting.provider": "black",
|
||||
"editor.rulers": [80,100,120]
|
||||
}
|
||||
2
bitbake
2
bitbake
|
|
@ -1 +1 @@
|
|||
Subproject commit 0c6f86b60cfba67c20733516957c0a654eb2b44c
|
||||
Subproject commit 907416ee1062f87f5844ab0638b54616abfc1a22
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||||
|
|
@ -26,7 +26,7 @@ COREOS_ROOT=$(readlink -f "${COREOS_ROOT}")
|
|||
# Set the path to bitbake, openembedded-core and the template directory
|
||||
# All theses values can be overriden by the caller of coreos-init-build-env
|
||||
BITBAKEDIR="${BITBAKEDIR:-${COREOS_ROOT}/bitbake}"
|
||||
OEROOT="${OEROOT:-${COREOS_ROOT}/layers/openembedded-core}"
|
||||
OEROOT="${OEROOT:-${COREOS_ROOT}/external-layers/openembedded-core}"
|
||||
TEMPLATECONF="${TEMPLATECONF:-${COREOS_ROOT}/templates}"
|
||||
|
||||
# Sanity checks
|
||||
|
|
@ -84,6 +84,13 @@ coreos_path_add "${COREOS_ROOT}/scripts"
|
|||
# Add support for ##COREOS_LAYERSDIR## inside of bblayer template
|
||||
coreos-bblayers-envsub COREOS_LAYERSDIR "${COREOS_ROOT}/layers"
|
||||
|
||||
# Add support for ##COREOS_EXTLAYERSDIR## inside of bblayer template
|
||||
coreos-bblayers-envsub COREOS_EXTLAYERSDIR "${COREOS_ROOT}/external-layers"
|
||||
|
||||
# Generate the ${BUILDDIR}/key directory. The scripts doesn't generate anything it
|
||||
# the directory already exist, so it's safe to call it everytime
|
||||
coreos-keygen > /dev/null 2> /dev/null
|
||||
# stdout is redirected to reduce the amount of output but not stderr
|
||||
coreos-keygen > /dev/null || {
|
||||
echo "The coreos-keygen script has failed" >&2
|
||||
return 1
|
||||
}
|
||||
|
|
@ -63,6 +63,11 @@ machine.
|
|||
Firmware requirements
|
||||
---------------------
|
||||
|
||||
.. warning::
|
||||
|
||||
CoreOS support at the moment only hardware that contains a block storage
|
||||
device (SD Card, eMMC, ...) formatted with GPT. MBR disk or MTD device are
|
||||
not supported.
|
||||
|
||||
ARM32 / AArch32 based machine
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -70,10 +75,7 @@ ARM32 / AArch32 based machine
|
|||
The firmware for ARM32 should implement a subset of the UEFI specification, as
|
||||
defined by the EBBR Specification. As this architecure is used on old hardware,
|
||||
it's ok to use the part of the specification that are marked as deprecated or
|
||||
legacy like:
|
||||
|
||||
- MBR partitionning instead of GPT
|
||||
- Fixed offsets to firmware data
|
||||
legacy.
|
||||
|
||||
We require the firmware to provide a DeviceTree based system description and not
|
||||
an ACPI based table (as allowed by the specification).
|
||||
|
|
|
|||
|
|
@ -12,3 +12,4 @@ CoreOS Optional Components
|
|||
Network Manager: NetworkManager <networkmanager>
|
||||
SSH Server: OpenSSH <openssh>
|
||||
Container: Podman <podman>
|
||||
CoreOS Installer <installer>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
.. index:: COREOS_INSTALLER
|
||||
|
||||
CoreOS Installer
|
||||
****************
|
||||
|
||||
The CoreOS installer is a set of script running on the target and a
|
||||
corresponding bitbake image that is used into the bootstrap process of CoreOS.
|
||||
|
||||
coreos-image-installer
|
||||
======================
|
||||
|
||||
The CoreOS installer image is a single binary EFI file that include a kernel,
|
||||
device tree and an initramfs with all the tools needed to install CoreOS.
|
||||
|
||||
An installer image is automatically built in parallel of a normal image.
|
||||
This can be deactivated by setting `COREOS_IMAGE_GENERATE_INSTALLER` to 0.
|
||||
|
||||
The installer image build by default only a single EFI binary named
|
||||
coreos-installer-MACHINE.efi. An SDCard image can be generate if
|
||||
`COREOS_INSTALLER_WKS_FILE` is set to a wks file.
|
||||
|
||||
coreos-installer
|
||||
================
|
||||
|
||||
The coreos-installer recipe installs some script that is used at startup
|
||||
to automatically format the internal emmc of the device. It also contains
|
||||
a swupdate configuration file to setup swupdate correctly for that use case.
|
||||
|
||||
coreos-installer-config
|
||||
=======================
|
||||
|
||||
The coreos-installer-config recipe installs device specific configuration file
|
||||
used by the coreos-installer. This includes the partitionner config file. Distro
|
||||
and project based on CoreOS can change the partionning scheme or partition size
|
||||
by installing their own version of this package using a `bbappend file`.
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
.. _beaglebone:
|
||||
|
||||
**********
|
||||
BeagleBone
|
||||
**********
|
||||
|
||||
.. important::
|
||||
|
||||
The BeagleBone target uses an old TI AM3358 ARM 32 BIT CPU. This processor
|
||||
of the AM335x family is used in a lot of current and legacy device at
|
||||
Hirschmann and NetModule. Thus we only support this target to ensure
|
||||
that our architecture is working on older architecture too.
|
||||
|
||||
CoreOS build instruction
|
||||
========================
|
||||
|
||||
.. code-block::
|
||||
|
||||
MACHINE=beaglebone bitbake coreos-image-all-features
|
||||
cd tmp/deploy/images/beaglebone
|
||||
|
||||
.. list-table:: Image artifacts for BeagleBone
|
||||
:widths: 25 75
|
||||
:header-rows: 1
|
||||
|
||||
* - Filename
|
||||
- Description
|
||||
* - <IMAGE>-beaglebone.swu
|
||||
- System image bundle used by the CoreOS installer or the CoreOS updater
|
||||
* - <IMAGE>-beaglebone.wic.xz
|
||||
- System image for SDCard
|
||||
* - coreos-image-installer-beaglebone.wic.xz
|
||||
- CoreOS installer image for SD Card
|
||||
|
||||
.. hint::
|
||||
|
||||
Only the .swu image is need if you have already a working installation of CoreOS
|
||||
running on the board that you want to update.
|
||||
|
||||
CoreOS Pre-installation guide
|
||||
=============================
|
||||
|
||||
If you want to use the internal emmc storage as boot target, you will need to
|
||||
flash coreos-image-installer-beaglebone.wic.xz to your SDCard using bmaptool.
|
||||
|
||||
If you want to use the sdcard as boot target, you will need to flash
|
||||
<IMAGE>-beaglebone.wic.xz to your SDCard using bmaptool.
|
||||
|
||||
By default the board boot on the internal emmc storage. To boot with a SDCard
|
||||
instead, you will need to push the S2 button (boot switch) while powering up the
|
||||
board.
|
||||
|
||||
.. image:: beaglebone/beaglebone-s2-switch.png
|
||||
|
||||
Serial access is available on the 5-pin header. See
|
||||
`this page <https://elinux.org/Beagleboard:BeagleBone_Black_Serial>`_ for
|
||||
more info on the serial connector.
|
||||
|
||||
Now that you have the installer running, CoreOS can be installed by following
|
||||
the :ref:`generic installation manual<Installation Manual>` using the SDCard
|
||||
mehtod.
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 246 KiB |
|
|
@ -0,0 +1,126 @@
|
|||
.. _netmodule-hw34:
|
||||
|
||||
*******************************
|
||||
NetModule HW34 (XG900 A-Sample)
|
||||
*******************************
|
||||
|
||||
.. important::
|
||||
|
||||
netmodule-hw34 support is currently only available on the features branch
|
||||
feat/netmodule-bsp
|
||||
|
||||
.. image:: netmodule-hw34/hw34.png
|
||||
|
||||
CoreOS build instruction
|
||||
========================
|
||||
|
||||
.. code-block::
|
||||
|
||||
MACHINE=netmodule-hw34 bitbake coreos-image-all-features
|
||||
cd tmp/deploy/images/netmodule-hw34
|
||||
|
||||
.. list-table:: Image artifacts for NetModule HW32
|
||||
:widths: 25 75
|
||||
:header-rows: 1
|
||||
|
||||
* - Filename
|
||||
- Description
|
||||
* - <IMAGE>-netmodule-hw34.swu
|
||||
- System image bundle used by the CoreOS installer or the CoreOS updater
|
||||
* - coreos-installer-netmodule-hw34.efi
|
||||
- CoreOS installer bundled in a single EFI binary
|
||||
* - tiboot3.bin
|
||||
- SPL Bootloader for the wakeup domain (arm32 R5 core)
|
||||
* - tispl.bin
|
||||
- SPL bootloader for the main domain (aarch64 main core)
|
||||
* - u-boot.bin
|
||||
- Third stage bootloader the main domain (aarch64 main core)
|
||||
|
||||
.. hint::
|
||||
|
||||
Only the .swu image is need if you have already a working installation of CoreOS
|
||||
running on the board that you want to update.
|
||||
|
||||
CoreOS Pre-installation guide
|
||||
=============================
|
||||
|
||||
The CoreOS installation process expect a working EFI firmware based on u-boot
|
||||
running on the board.
|
||||
|
||||
For board that have no firmware or a defect firmware, we can provide the firmware by
|
||||
booting over USB.
|
||||
|
||||
First, we need to put the board in USB Boot mode by modifying the dip-switch
|
||||
on the back of the board:
|
||||
|
||||
.. code-block::
|
||||
|
||||
ON
|
||||
S500 ▄ ▀ ▄ ▀ ▄ ▄ ▄ ▄
|
||||
1 2 3 4 5 6 7 8
|
||||
|
||||
.. hint::
|
||||
|
||||
Unflashed board or board without a valid tiboot3.bin image will default to
|
||||
USB boot mode, so settings the dip-switch may be skipped in this case.
|
||||
|
||||
Then you need to populate the jumper X600 near the USB port:
|
||||
|
||||
.. image:: netmodule-hw34/hw34-usb-device.png
|
||||
|
||||
Then power-up the board by first apply 12V throug the main connector, then
|
||||
connect a USB-C cable. Console access to the board can be accessed using the
|
||||
serial port on the main connector.
|
||||
|
||||
|
||||
.. important::
|
||||
|
||||
When removing the power, ensure that the USB cable is removed first. Otherwise
|
||||
the processor will not get shutdown properly
|
||||
|
||||
|
||||
Now you should see the board from you computer:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
lsusb | grep DFU
|
||||
Bus 003 Device 048: ID 0451:6165 Texas Instruments, Inc. AM64x DFU
|
||||
|
||||
Now we start downloading the bootloaders into RAM by using dfu-utils:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
dfu-util -D tiboot3.bin -a 0
|
||||
dfu-util -D tispl.bin -a 0
|
||||
|
||||
# Eject and start execution of tispl
|
||||
dfu-util -e -a 0
|
||||
dfu-util -D u-boot.img -a 1
|
||||
|
||||
# Eject ans tart of u-boot.img
|
||||
dfu-util -e -a 1
|
||||
|
||||
.. hint::
|
||||
|
||||
The firmware was uploaded to the RAM, thus will not survice a reboot.
|
||||
|
||||
|
||||
Now that we have a firmware running, CoreOS can be installed by following
|
||||
the :ref:`generic installation manual<Installation Manual>`.
|
||||
|
||||
|
||||
CoreOS Post-Installation
|
||||
========================
|
||||
|
||||
When the installation of CoreOS is done, power down the board by first
|
||||
removing the USB-C cable then the main power.
|
||||
|
||||
Now, put the board back in emmc boot mode:
|
||||
|
||||
.. code-block::
|
||||
|
||||
ON
|
||||
S500 ▀ ▄ ▄ ▀ ▄ ▄ ▄ ▄
|
||||
1 2 3 4 5 6 7 8
|
||||
|
||||
Then power-up the board again and CoreOS should boot.
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 3.3 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 2.4 MiB |
|
|
@ -0,0 +1,33 @@
|
|||
******************
|
||||
Supported Hardware
|
||||
******************
|
||||
|
||||
.. _Hardware Overview:
|
||||
.. list-table:: Supported BitBake MACHINE
|
||||
:widths: 25 75 25
|
||||
:header-rows: 1
|
||||
|
||||
* - BitBake MACHINE
|
||||
- Compatible hardware
|
||||
- Documentation
|
||||
* - cn9131-bldn-mbv
|
||||
- Falcon A3 Sample
|
||||
-
|
||||
* - netmodule-hw34
|
||||
- NetModule HW34 (XG900 Sample)
|
||||
- :ref:`🔗 links <netmodule-hw34>`
|
||||
* - cn9130-cf-pro
|
||||
- Solidrun cn9130-cf-pro
|
||||
-
|
||||
* - beaglebone
|
||||
- Beaglebone, Beaglebone Black, Beaglebone Green
|
||||
- :ref:`🔗 links <beaglebone>`
|
||||
* - vm-x64
|
||||
- Virtual Machine
|
||||
-
|
||||
|
||||
.. hint::
|
||||
|
||||
Please contact the CoreOS team when starting a new project based on CoreOS
|
||||
or want to contribute the hardware support for an existing Hardware.
|
||||
|
||||
|
|
@ -28,20 +28,28 @@ same structures.
|
|||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Software Components
|
||||
|
||||
Core Components <components/core/index>
|
||||
Optional Components <components/optional/index>
|
||||
:caption: Supported Hardware
|
||||
|
||||
Overview <hardware/overview>
|
||||
NetModule HW34 (XG900 Sample) <hardware/netmodule-hw34>
|
||||
BeagleBone <hardware/beaglebone>
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Manuals
|
||||
|
||||
Installation Manual <installation/index>
|
||||
Reference Manual <ref-manual/index>
|
||||
Boot Concepts <boot/index>
|
||||
Best Practices <best_practices/index>
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Software Components
|
||||
|
||||
Core Components <components/core/index>
|
||||
Optional Components <components/optional/index>
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
:caption: Indexes
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
.. _Installation Manual:
|
||||
|
||||
======================================
|
||||
Belden CoreOS EMMC Installation Manual
|
||||
======================================
|
||||
|
||||
.. important::
|
||||
|
||||
This manual expect that the board you want to install CoreOS on have a
|
||||
running UEFI firmware based on u-boot. Information about how to get console
|
||||
access and a running firmware can be found for your hardware in the
|
||||
:ref:`Hardware Overview <Hardware Overview>`
|
||||
|
||||
|
|
||||
|
||||
.. toctree::
|
||||
:caption: Table of Contents
|
||||
:numbered:
|
||||
|
||||
starting
|
||||
partitionning
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
************
|
||||
Installation
|
||||
************
|
||||
|
||||
The installer automatically creates all the needed partitions when starting up.
|
||||
|
||||
Now you have to upload the .swu file to start the flashing process.
|
||||
|
||||
Choose one of these methods to upload the system image to the installer:
|
||||
|
||||
Upload the .swu file over the network using a browser
|
||||
=====================================================
|
||||
|
||||
|
||||
Now you can install the desired CoreOS version by uploading the desired
|
||||
.swu file to the board using a browser, by going to http://<TARGET_IP>:8080
|
||||
|
||||
Upload the .swu file over the network using devtool
|
||||
===================================================
|
||||
|
||||
If you have a working build environement, you can upload the image using
|
||||
the devtool command:
|
||||
|
||||
.. code-block::
|
||||
|
||||
MACHINE=<MACHINE> devtool swupdate-www-push <IMAGE> <TARGET_IP>
|
||||
|
||||
|
||||
.. hint::
|
||||
Replace <IMAGE> with the image recipe name, eg: coreos-image-all-features
|
||||
Replace <MACHINE> by the machine name (if not set in local.conf)
|
||||
Replace <TARGET_IP> by the IP adress of the board
|
||||
|
||||
Upload the .swu file over the network using coreos-device
|
||||
=========================================================
|
||||
|
||||
If you don't have a working build environement, you can upload the image using
|
||||
the coreos-device python script:
|
||||
|
||||
.. code-block::
|
||||
|
||||
./coreos-device swupdate-www-push <SWU_PATH> <TARGET_IP>
|
||||
|
||||
.. hint::
|
||||
Replace <SWU_PATH> with the the path to the SWU, eg: ./coreos-image-all-features-<MACHINE>.swu
|
||||
Replace <TARGET_IP> by the IP adress of the board
|
||||
|
||||
.. hint::
|
||||
You will find the coreos-device script under the scripts directory inside
|
||||
the CoreOS repository.
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
**********************
|
||||
Starting the installer
|
||||
**********************
|
||||
|
||||
Choose one of these methods to start the bootloader:
|
||||
|
||||
Starting the installer over the network with TFTP
|
||||
=================================================
|
||||
|
||||
Put the coreos-installer EFI bundle (coreos-installer-<MACHINE>.efi) into an
|
||||
accessible TFTP server, then enter the following command into u-boot:
|
||||
|
||||
.. code-block::
|
||||
|
||||
setenv ipaddr <TARGET_IP>; setenv serverip <SERVER_IP>;
|
||||
tftp $loadaddr coreos-installer-<MACHINE>.efi
|
||||
bootefi $loadaddr
|
||||
|
||||
.. hint::
|
||||
|
||||
Replace <TARGET_IP> by a valid IP adress for the target, eg: 192.168.1.1
|
||||
Replace <SERVER_IP> by the IP adress of the server, eg: 192.168.1.254
|
||||
Replace <MACHINE> by the name of the machine set in bitbake
|
||||
|
||||
Starting the installer over the network with DHCP/BOOTP/TFTP
|
||||
============================================================
|
||||
|
||||
Use a DHCP/BOOTP/TFTP server to configure automatically the device. You can
|
||||
use dnsmasq for this task.
|
||||
|
||||
|
||||
.. code-block: ini
|
||||
|
||||
interface=<INTERFACE>
|
||||
|
||||
dhcp-range=<INTERFACE>,10.237.30.2,10.237.30.100,4h
|
||||
dhcp-range=<INTERFACE>,10.237.40.2,10.237.40.100,4h
|
||||
|
||||
enable-tftp
|
||||
dhcp-boot=tag:<INTERFACE>,coreos-installer-<MACHINE>.efi
|
||||
tftp-root=/var/lib/tftpboot
|
||||
|
||||
.. hint::
|
||||
|
||||
Replace <INTERFACE> by the name of the network interface that is connected
|
||||
to the target. Eg: enp3s0
|
||||
Replace <MACHINE> by the name of the machine set in bitbake
|
||||
|
||||
Put the coreos-installer EFI bundle (coreos-installer-<MACHINE>.efi) into the
|
||||
/var/lib/tftpboot folder then enter the following command into u-boot:
|
||||
|
||||
.. code-block::
|
||||
|
||||
setenv autoload yes
|
||||
setenv autostart no
|
||||
dhcp
|
||||
bootefi $loadaddr
|
||||
|
||||
Starting the installer using an SD Card
|
||||
=======================================
|
||||
|
||||
Flash the coreos-image-installer.wic.xz into an SDCard and put the board
|
||||
in SDCard boot mode. Insert the SDCard and power up the board. The CoreOS
|
||||
installer should start automatically.
|
||||
|
|
@ -46,7 +46,7 @@ Theses packages are needed on your build machine:
|
|||
chrpath socat cpio python3 python3-pip python3-pexpect xz-utils \
|
||||
debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa \
|
||||
libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
|
||||
liblz4-tool bmap-tools efitools openssl sbsign python3-click \
|
||||
liblz4-tool bmap-tools efitools openssl sbsigntool python3-click \
|
||||
python3-aiohttp
|
||||
|
||||
Use Git to clone CoreOS
|
||||
|
|
|
|||
|
|
@ -10,9 +10,14 @@ to Belden CoreOS.
|
|||
Machine Features
|
||||
================
|
||||
|
||||
CoreOS doesn't define any custom machine feature for now, but the
|
||||
:external:ref:`MACHINE_FEATURES <ref-features-machine>` of OpenEmbedded-Core
|
||||
can be used.
|
||||
can be used with CoreOS.
|
||||
|
||||
In addition, those CoreOS specific MACHINE_FEATURES can be used too:
|
||||
|
||||
- *sdcard:* the machine as an internal SD Card or MicroSD Slot.
|
||||
- *emmc:* the machine as an internal emmc based storage
|
||||
|
||||
|
||||
.. index:: DISTRO_FEATURES
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit e3581b11d30d91d0363acb48a6aee47043b7e0bc
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 346753705e49a2486867dc150181a1c7f4d69377
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit eaa4dcbac224c9f5e7da784dcda78b67f117cf63
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit af02908efda1580e77b3fdeed25b124a2b8d9482
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit 8ce2b1a3083f61e5a3df3a80c3de7d294bc71bb5
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
SWUPDATE_IMAGES += "MLO"
|
||||
SWUPDATE_IMAGES += "u-boot-beaglebone"
|
||||
SWUPDATE_IMAGES_FSTYPES[MLO] = ""
|
||||
SWUPDATE_IMAGES_FSTYPES[u-boot-beaglebone] = ".img"
|
||||
|
||||
COREOS_SWUPDATE_EXTENDS_FOR:append = "beaglebone"
|
||||
|
||||
def coreos_swupdate_extends_images_for_beaglebone(d,s):
|
||||
mlo = {
|
||||
"filename" : "MLO",
|
||||
"installed-directly" : "true",
|
||||
"device" : "/dev/disk/by-partlabel/mlo",
|
||||
"type" : "raw",
|
||||
"sha256" : swupdate_get_sha256(d, s, "MLO"),
|
||||
}
|
||||
|
||||
uboot = {
|
||||
"filename" : "u-boot-beaglebone.img",
|
||||
"installed-directly" : "true",
|
||||
"device" : "/dev/disk/by-partlabel/uboot",
|
||||
"type" : "raw",
|
||||
"sha256" : swupdate_get_sha256(d, s, "u-boot-beaglebone.img"),
|
||||
}
|
||||
|
||||
return [mlo, uboot]
|
||||
|
|
@ -11,6 +11,7 @@ include conf/machine/include/arm/armv7a/tune-cortexa8.inc
|
|||
|
||||
IMAGE_FSTYPES += "wic wic.xz wic.bmap"
|
||||
WKS_FILE ?= "beaglebone-sdcard.wks.in"
|
||||
COREOS_INSTALLER_WKS_FILE ?= "beaglebone-sdcard-installer.wks"
|
||||
MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image kernel-devicetree"
|
||||
do_image_wic[depends] += "mtools-native:do_populate_sysroot dosfstools-native:do_populate_sysroot gptfdisk-native:do_populate_sysroot virtual/bootloader:do_deploy"
|
||||
do_image_wic[recrdeptask] += "do_bootimg"
|
||||
|
|
@ -36,9 +37,6 @@ UBOOT_LOADADDRESS = "0x80008000"
|
|||
|
||||
MACHINE_FEATURES = "usbgadget usbhost vfat alsa"
|
||||
|
||||
IMAGE_BOOT_FILES ?= "u-boot.${UBOOT_SUFFIX} ${SPL_BINARY}"
|
||||
IMAGE_EFI_BOOT_FILES ?= "${KERNEL_DEVICETREE}"
|
||||
|
||||
# support runqemu
|
||||
EXTRA_IMAGEDEPENDS += "qemu-native qemu-helper-native"
|
||||
IMAGE_CLASSES += "qemuboot"
|
||||
|
|
@ -59,12 +57,7 @@ QB_TCPSERIAL_OPT = "-device virtio-serial-device -chardev socket,id=virtcon,port
|
|||
# No watchdog available yet
|
||||
EFIBOOTGUARD_TIMEOUT ?= "0"
|
||||
|
||||
# MBR disk can't select the root device by partition label as MBR doesn't have
|
||||
# a partition label. Using filesystem label only work with an initramfs and we
|
||||
# don't support it yet.
|
||||
COREOS_PLATFORM0_ROOT ?= "/dev/mmcblk0p3"
|
||||
COREOS_PLATFORM1_ROOT ?= "/dev/mmcblk0p4"
|
||||
COREOS_IMAGE_SWUPDATE_EXTRACLASSES += "coreos-image-swupdate-beaglebone"
|
||||
|
||||
require conf/machine/include/coreos-generic-features/efi.inc
|
||||
require conf/machine/include/coreos-generic-features/legacy-mbr-disk.inc
|
||||
require conf/machine/include/coreos-generic-features/emmc.inc
|
||||
require conf/machine/include/coreos-generic-features/partitions.inc
|
||||
|
|
|
|||
|
|
@ -4,11 +4,3 @@
|
|||
MACHINE_FEATURES:append = " efi"
|
||||
|
||||
do_image_wic[depends] += "efibootguard-native:do_populate_sysroot efibootguard:do_deploy"
|
||||
|
||||
# Variable used in WKS file
|
||||
|
||||
WKS_PART_EFI ??= 'part --source efibootguard-efi --label efi --align 1024 --part-type=EF00'
|
||||
WKS_PART_ROOT_A ??= 'part / --source rootfs --fstype=ext4 --label platform0 --align 1024'
|
||||
WKS_PART_ROOT_B ??= 'part --fstype=ext4 --label platform1 --align 1024'
|
||||
WKS_PART_EFIBOOTGUARD_A ??= 'part --source efibootguard-boot --label boot0 --align 1024 --part-type=0700 --sourceparams "watchdog=${EFIBOOTGUARD_TIMEOUT},revision=2,kernel=kernel0-${MACHINE}.efi;KERNEL0.EFI"'
|
||||
WKS_PART_EFIBOOTGUARD_B ??= 'part --source efibootguard-boot --label boot1 --align 1024 --part-type=0700 --sourceparams "watchdog=${EFIBOOTGUARD_TIMEOUT},revision=1,kernel=kernel1-${MACHINE}.efi;KERNEL1.EFI"'
|
||||
|
|
|
|||
|
|
@ -1,7 +0,0 @@
|
|||
# This configuration file should be included for all hardware that has an
|
||||
# integrated emmc
|
||||
|
||||
MACHINE_FEATURES += "emmc"
|
||||
|
||||
# Generate a SWU image to flash the emmc
|
||||
do_image[depends] += "coreos-emmc-flasher-${MACHINE}:do_swuimage"
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
|
||||
# MBR disk are still supported by CoreOS, but only for legacy product
|
||||
# This ensure that efibootguard / swupdate work with MBR disk
|
||||
|
||||
# Do not include this file in a machine configuration if the machine support
|
||||
# a GPT disk instead
|
||||
COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY ?= "/dev/disk/by-label"
|
||||
|
||||
# MBR can't disk can't use partition label, but may use filesystem label
|
||||
# This will only work with an initramfs. If no initramfs is used, this will
|
||||
# have to be set to the right disk device inside the machine configuration
|
||||
# like that COREOS_PLATFORMx_ROOT = "/dev/mmcblk<DISK>p<PART>"
|
||||
COREOS_PLATFORM0_ROOT ?= "LABEL=platform0"
|
||||
COREOS_PLATFORM1_ROOT ?= "LABEL=platform1"
|
||||
|
||||
# MBR disk can't use --part-type but can use system-id
|
||||
WKS_PART_EFI ?= 'part --source efibootguard-efi --label efi --system-id 0xef'
|
||||
WKS_PART_EFIBOOTGUARD_A ?= 'part --source efibootguard-boot --label boot0 --sourceparams "watchdog=${EFIBOOTGUARD_TIMEOUT},revision=2,kernel=kernel0-${MACHINE}.efi;KERNEL0.EFI"'
|
||||
WKS_PART_EFIBOOTGUARD_B ?= 'part --source efibootguard-boot --label boot1 --sourceparams "watchdog=${EFIBOOTGUARD_TIMEOUT},revision=1,kernel=kernel1-${MACHINE}.efi;KERNEL1.EFI"'
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
# Variable used in WKS file
|
||||
|
||||
WKS_PART_EFI ??= 'part --source efibootguard-efi --label efi --part-type=EF00'
|
||||
WKS_PART_EFIBOOTGUARD_A ??= 'part --source efibootguard-boot --label ebg0 --part-type=0700 --sourceparams "args=coreos.root=rootfs0,watchdog=${EFIBOOTGUARD_TIMEOUT},revision=2,kernel=kernel-${MACHINE}.efi;KERNEL.EFI"'
|
||||
WKS_PART_EFIBOOTGUARD_B ??= 'part --source efibootguard-boot --label ebg1 --part-type=0700 --sourceparams "args=coreos.root=rootfs1,watchdog=${EFIBOOTGUARD_TIMEOUT},revision=1,kernel=kernel-${MACHINE}.efi;KERNEL.EFI"'
|
||||
WKS_PART_ROOT_A ??= 'part / --source rootfs --fstype=ext4 --label rootfs0'
|
||||
WKS_PART_ROOT_B ??= 'part --fstype=ext4 --label rootfs1'
|
||||
WKS_PART_ROOT_SIZE ??= '2G'
|
||||
|
||||
SFDISK_PART_EFI ??= 'type=C12A7328-F81F-11D2-BA4B-00A0C93EC93B, name="efi"'
|
||||
SFDISK_PART_EFIBOOTGUARD_A ??= 'type=EBD0A0A2-B9E5-4433-87C0-68B6B72699C7, name="ebg0"'
|
||||
SFDISK_PART_EFIBOOTGUARD_B ??= 'type=EBD0A0A2-B9E5-4433-87C0-68B6B72699C7, name="ebg1"'
|
||||
SFDISK_PART_ROOT_A ??= 'type=0FC63DAF-8483-4772-8E79-3D69D8477DE4, name="rootfs0"'
|
||||
SFDISK_PART_ROOT_B ??= 'type=0FC63DAF-8483-4772-8E79-3D69D8477DE4, name="rootfs0"'
|
||||
|
|
@ -22,3 +22,4 @@ do_image_wic[recrdeptask] += "do_bootimg"
|
|||
COREOS_EFI_SECUREBOOT_INSTALL_PUBKEY_IN_EFIDIR = "1"
|
||||
|
||||
require conf/machine/include/coreos-generic-features/efi.inc
|
||||
require conf/machine/include/coreos-generic-features/partitions.inc
|
||||
|
|
|
|||
|
|
@ -1,6 +0,0 @@
|
|||
COMPATIBLE_MACHINE = "beaglebone"
|
||||
|
||||
require coreos-emmc-flasher.inc
|
||||
require coreos-emmc-flasher-uboot.inc
|
||||
|
||||
SWUPDATE_IMAGES += "MLO"
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
software =
|
||||
{
|
||||
version = "@@DISTRO_VERSION@@";
|
||||
@@MACHINE@@ = {
|
||||
hardware-compatibility: ["1.0"];
|
||||
factory = {
|
||||
emmc = {
|
||||
partitions: (
|
||||
{
|
||||
type = "diskpart";
|
||||
device = "/dev/mmcblk1";
|
||||
properties: {
|
||||
labeltype = "dos";
|
||||
partition-1 = [ "size=32M", "start=133120", "name=efi", "type=0xef", "fstype=fat16"];
|
||||
};
|
||||
}
|
||||
);
|
||||
images: (
|
||||
{
|
||||
filename = "MLO";
|
||||
device = "/dev/mmcblk1";
|
||||
offset = "128K";
|
||||
sha256 = "$swupdate_get_sha256(MLO)";
|
||||
},
|
||||
{
|
||||
filename = "u-boot-beaglebone.img";
|
||||
device = "/dev/mmcblk1";
|
||||
offset = "384K";
|
||||
sha256 = "$swupdate_get_sha256(u-boot-beaglebone.img)";
|
||||
|
||||
}
|
||||
);
|
||||
files: (
|
||||
{
|
||||
filename = "efibootguardarm.efi";
|
||||
path = "/EFI/BOOT/bootarm.efi";
|
||||
device = "/dev/mmcblk1p1";
|
||||
filesystem = "vfat";
|
||||
sha256 = "$swupdate_get_sha256(efibootguardarm.efi)";
|
||||
properties: {
|
||||
create-destination = "true";
|
||||
}
|
||||
}
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
# Machine that use u-boot can include this file after
|
||||
# coreo-swupdate-flasher.inc
|
||||
|
||||
# Add support to flash u-boot
|
||||
IMAGE_DEPENDS += "virtual/bootloader"
|
||||
|
||||
UBOOT_SUFFIX ??= "img"
|
||||
SWUPDATE_IMAGES += "u-boot"
|
||||
SWUPDATE_IMAGES_FSTYPES[u-boot] = ".${UBOOT_SUFFIX}"
|
||||
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
|
||||
DESCRIPTION = "SWU Image generation to flash the internal emmc"
|
||||
SECTION = "bootloaders"
|
||||
LICENSE = "CLOSED"
|
||||
PR = "r1"
|
||||
|
||||
SRC_URI = " \
|
||||
file://sw-description \
|
||||
"
|
||||
|
||||
# efibootguard
|
||||
# ==============================================================================
|
||||
# efibootguard support is not machine depends so it can be done here
|
||||
|
||||
require conf/image-uefi.conf
|
||||
|
||||
# The efibootguard binary has to be embedded into the image. swupdate will check
|
||||
# that the binary exist
|
||||
IMAGE_DEPENDS += "efibootguard"
|
||||
SWUPDATE_IMAGES += "efibootguard${EFI_ARCH}"
|
||||
|
||||
# Override or variable are not supported in var[flag] statement, but having more
|
||||
# flags than necessary doesn't do any arm
|
||||
SWUPDATE_IMAGES_FSTYPES[efibootguardx64] = ".efi"
|
||||
SWUPDATE_IMAGES_FSTYPES[efibootguardaa64] = ".efi"
|
||||
SWUPDATE_IMAGES_FSTYPES[efibootguardarm] = ".efi"
|
||||
|
||||
# Image generated should be named coreos-swupdater-flasher-${MACHINE}
|
||||
# and not the default coreos-swupdate-flasher-${MACHINE}-${MACHINE}
|
||||
IMAGE_BASENAME ?= "coreos-emmc-flasher"
|
||||
inherit swupdate
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
label: gpt
|
||||
device: /dev/mmcblk1
|
||||
unit: sectors
|
||||
first-lba: 34
|
||||
last-lba: 7471070
|
||||
sector-size: 512
|
||||
|
||||
# EBBR 2.1.0 section 4.1.1 mandate the use of an unused type UUID and to set
|
||||
# the RequiredPartition label for part of the firmware stored in the main disk
|
||||
# https://arm-software.github.io/ebbr/#section-gpt-parts
|
||||
# next two type were generated
|
||||
/dev/mmcblk1p1 : start= 256, size= 512, type=4DA6E9DA-C803-4BE4-BAC4-8192717C5EB0, name="mlo", attrs="RequiredPartition"
|
||||
/dev/mmcblk1p2 : start= 768, size= 8192, type=5B97345D-B7A1-47D3-A491-ED40F4841639, name="uboot", attrs="RequiredPartition"
|
||||
|
||||
/dev/mmcblk1p3 : start= 8960, size= 131072, ${SFDISK_PART_EFI}
|
||||
/dev/mmcblk1p4 : start= 140032, size= 262144, ${SFDISK_PART_EFIBOOTGUARD_A}
|
||||
/dev/mmcblk1p5 : start= 402176, size= 262144, ${SFDISK_PART_EFIBOOTGUARD_B}
|
||||
/dev/mmcblk1p6 : start= 664320, size= 3403375, ${SFDISK_PART_ROOT_A}
|
||||
/dev/mmcblk1p7 : start= 4067695, size= 3403375, ${SFDISK_PART_ROOT_B}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
FILESEXTRAPATHS:prepend := "${THISDIR}/coreos-installer-config:"
|
||||
|
||||
SRC_URI:append:beaglebone = " file://beaglebone_1.0.sfdisk"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# short-description: Create SD card image for Beaglebone
|
||||
# long-description: Creates a partitioned SD card image for Beaglebone.
|
||||
|
||||
# offset 1S => 1 sector (1x512 byte)
|
||||
# The bootloader can be at 4 different position in raw mode: 0S, 256S, 512S, 768S
|
||||
# MBR disk use only the sector 0, so 1S is free
|
||||
# GPT disk use sector 0-33S, so first free slot is 256S
|
||||
# Offset are from the BBB default settings
|
||||
|
||||
# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
# Don't name partition in the installer disk image, otherwise the installer may not work as it rely on partition label!
|
||||
# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
|
||||
part --offset 256S --source rawcopy --sourceparams="file=MLO" --ondisk mmcblk0 --fixed-size 256K
|
||||
part --offset 768S --source rawcopy --sourceparams="file=u-boot.img" --ondisk mmcblk0 --fixed-size 4M
|
||||
|
||||
# Let's define a 4MiB maximum size for the bootloader
|
||||
# 4MiB => 4*1024*1024/512=8192S | 768S + 8192S => 8960S
|
||||
part --source bootimg-partition --part-type=EF00 --ondisk mmcblk0 --offset 8960S --fixed-size 125M
|
||||
bootloader --ptable gpt
|
||||
|
|
@ -1,11 +1,20 @@
|
|||
# short-description: Create SD card image for Beaglebone
|
||||
# long-description: Creates a partitioned SD card image for Beaglebone.
|
||||
# Boot files are located in the first vfat partition.
|
||||
|
||||
part --source bootimg-partition --ondisk mmcblk0 --fstype=vfat --label boot --active --align 4 --size 32M --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_EFI} --ondisk mmcblk0 --align 1024 --size 32M --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_A} --ondisk mmcblk0 --size 2G --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_B} --ondisk mmcblk0 --size 2G --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_EFIBOOTGUARD_A} --ondisk mmcblk0 --align 1024 --size 128M --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_EFIBOOTGUARD_B} --ondisk mmcblk0 --align 1024 --size 128M --extra-space 0 --overhead-factor 1
|
||||
bootloader --ptable msdos
|
||||
# offset 1S => 1 sector (1x512 byte)
|
||||
# The bootloader can be at 4 different position in raw mode: 0S, 256S, 512S, 768S
|
||||
# MBR disk use only the sector 0, so 1S is free
|
||||
# GPT disk use sector 0-33S, so first free slot is 256S
|
||||
# Offset are from the BBB default settings
|
||||
part --offset 256S --source rawcopy --sourceparams="file=MLO" --ondisk mmcblk0 --fixed-size 256K --part-name "mlo"
|
||||
part --offset 768S --source rawcopy --sourceparams="file=u-boot.img" --ondisk mmcblk0 --fixed-size 4M --part-name "uboot"
|
||||
|
||||
|
||||
# Let's define a 4MiB maximum size for the bootloader
|
||||
# 4MiB => 4*1024*1024/512=8192S | 768S + 8192S => 8960S
|
||||
${WKS_PART_EFI} --ondisk mmcblk0 --offset 8960S --fixed-size 32M
|
||||
${WKS_PART_EFIBOOTGUARD_A} --ondisk mmcblk0 --fixed-size 128M
|
||||
${WKS_PART_EFIBOOTGUARD_B} --ondisk mmcblk0 --fixed-size 128M
|
||||
${WKS_PART_ROOT_A} --ondisk mmcblk0 --fixed-size ${WKS_PART_ROOT_SIZE}
|
||||
${WKS_PART_ROOT_B} --ondisk mmcblk0 --fixed-size ${WKS_PART_ROOT_SIZE}
|
||||
bootloader --ptable gpt
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
# short-description: Create an EFI disk image for genericx86*
|
||||
# long-description: Creates a partitioned EFI disk image for genericx86* machines
|
||||
${WKS_PART_EFI} --ondisk sda --align 1024 --size 64M --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_A} --ondisk sda --size 2G --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_B} --ondisk sda --size 2G --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_A} --ondisk sda --size ${WKS_PART_ROOT_SIZE} --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_ROOT_B} --ondisk sda --size ${WKS_PART_ROOT_SIZE} --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_EFIBOOTGUARD_A} --ondisk sda --align 1024 --size 128M --extra-space 0 --overhead-factor 1
|
||||
${WKS_PART_EFIBOOTGUARD_B} --ondisk sda --align 1024 --size 128M --extra-space 0 --overhead-factor 1
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,12 @@ def get_coreos_ci_artifacts(d):
|
|||
if d.getVar('COREOS_IMAGE_GENERATE_SWU') == '1':
|
||||
artifacts.append(d.getVar('IMAGE_LINK_NAME') + '.swu')
|
||||
|
||||
# CoreOS Installer
|
||||
# ==========================================================================
|
||||
|
||||
if d.getVar('COREOS_IMAGE_GENERATE_INSTALLER') == '1':
|
||||
artifacts.append('coreos-installer-' + d.getVar('MACHINE') + '.efi')
|
||||
|
||||
# Kernel
|
||||
# ==========================================================================
|
||||
|
||||
|
|
@ -40,8 +46,7 @@ def get_coreos_ci_artifacts(d):
|
|||
artifacts.append(kernel_imagetype + '-' + machine + kernel_image_bin_ext)
|
||||
|
||||
if d.getVar('COREOS_IMAGE_GENERATE_UKI') == '1':
|
||||
artifacts.append(d.getVar('COREOS_KERNEL0_FILENAME'))
|
||||
artifacts.append(d.getVar('COREOS_KERNEL1_FILENAME'))
|
||||
artifacts.append(d.getVar('COREOS_KERNEL_FILENAME'))
|
||||
|
||||
# Bootloaders
|
||||
# ==========================================================================
|
||||
|
|
|
|||
|
|
@ -7,9 +7,6 @@
|
|||
# Swupdate image generation
|
||||
# ==============================================================================
|
||||
|
||||
# Machine using MBR override this value, see legacy-mbr-disk.inc
|
||||
COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY ??= "/dev/disk/by-partlabel"
|
||||
|
||||
IMAGE_FSTYPES:append = " ext4.zst"
|
||||
python () {
|
||||
image = d.getVar('IMAGE_BASENAME')
|
||||
|
|
@ -19,16 +16,58 @@ python () {
|
|||
inherit swupdate-image
|
||||
|
||||
# Ensure than variable used in the sw-description files are watched for change
|
||||
do_swuimage[vardeps] += "COREOS_KERNEL0_FILENAME COREOS_KERNEL1_FILENAME EFIBOOTGUARD_TIMEOUT COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY APPEND"
|
||||
do_swuimage[vardeps] += "COREOS_KERNEL_FILENAME EFIBOOTGUARD_TIMEOUT EFIDIR EFI_BOOT_IMAGE COREOS_EFIBOOTGUARD_FILENAME"
|
||||
do_swuimage[deptask] += "do_bundle_uki"
|
||||
SWUPDATE_IMAGES += "${COREOS_KERNEL0_NAME} ${COREOS_KERNEL1_NAME}"
|
||||
|
||||
COREOS_EFIBOOTGUARD_NAME ?= "efibootguard${EFI_ARCH}"
|
||||
COREOS_EFIBOOTGUARD_EXT ?= ".efi"
|
||||
COREOS_EFIBOOTGUARD_FILENAME = "${COREOS_EFIBOOTGUARD_NAME}${COREOS_EFIBOOTGUARD_EXT}"
|
||||
|
||||
SWUPDATE_IMAGES += "${COREOS_KERNEL_NAME} ${COREOS_EFIBOOTGUARD_NAME}"
|
||||
|
||||
python () {
|
||||
kernel0 = d.getVar('COREOS_KERNEL0_NAME')
|
||||
kernel1 = d.getVar('COREOS_KERNEL1_NAME')
|
||||
kernel = d.getVar('COREOS_KERNEL_NAME')
|
||||
kernelext = d.getVar('COREOS_KERNEL_EXT')
|
||||
d.setVarFlag("SWUPDATE_IMAGES_FSTYPES", kernel0, kernelext)
|
||||
d.setVarFlag("SWUPDATE_IMAGES_FSTYPES", kernel1, kernelext)
|
||||
d.setVarFlag("SWUPDATE_IMAGES_FSTYPES", kernel, kernelext)
|
||||
|
||||
efibootguard = d.getVar('COREOS_EFIBOOTGUARD_NAME')
|
||||
efibootguardext = d.getVar('COREOS_EFIBOOTGUARD_EXT')
|
||||
d.setVarFlag("SWUPDATE_IMAGES_FSTYPES", efibootguard, efibootguardext)
|
||||
}
|
||||
|
||||
FILESEXTRAPATHS:append := ":${COREOS_ROOT}/layers/meta-belden-coreos/files"
|
||||
|
||||
# Space seperated list of extension points
|
||||
COREOS_SWUPDATE_EXTENDS_FOR ??= ""
|
||||
|
||||
def coreos_swupdate_extends(d, s, key):
|
||||
"""
|
||||
Extends the swupdate for each extension points defined by COREOS_SWUPDATE_EXTENDS_FOR
|
||||
"""
|
||||
extends_for = d.getVar('COREOS_SWUPDATE_EXTENDS_FOR', True).replace("-", "_").split()
|
||||
|
||||
def kv_to_sw_description(kv):
|
||||
swdescr = ",{\n"
|
||||
for key, value in kv.items():
|
||||
swdescr += f'{key} = "{value}";\n'
|
||||
swdescr += "}\n"
|
||||
return swdescr
|
||||
|
||||
text = ""
|
||||
|
||||
# BSP and Distro can extends the swupdate by implementing some python
|
||||
# function that return a list of dictionary.
|
||||
for extension_point in extends_for:
|
||||
try:
|
||||
kv_list = globals()[f"coreos_swupdate_extends_{key}_for_{extension_point}"](d,s)
|
||||
except KeyError:
|
||||
# Don't fail if the extension is not implemented
|
||||
pass
|
||||
else:
|
||||
for kv in kv_list:
|
||||
text += kv_to_sw_description(kv)
|
||||
|
||||
return text
|
||||
|
||||
COREOS_IMAGE_SWUPDATE_EXTRACLASSES ?= ""
|
||||
inherit ${COREOS_IMAGE_SWUPDATE_EXTRACLASSES}
|
||||
|
|
|
|||
|
|
@ -10,32 +10,28 @@ inherit coreos-efi-sbsign
|
|||
# ==============================================================================
|
||||
|
||||
COREOS_KERNEL_EXT ??= ".efi"
|
||||
COREOS_KERNEL0_NAME ??= "kernel0-${MACHINE}"
|
||||
COREOS_KERNEL1_NAME ??= "kernel1-${MACHINE}"
|
||||
COREOS_KERNEL0_FILENAME ??= "${COREOS_KERNEL0_NAME}${COREOS_KERNEL_EXT}"
|
||||
COREOS_KERNEL0 ??= "${DEPLOY_DIR_IMAGE}/${COREOS_KERNEL0_FILENAME}"
|
||||
COREOS_KERNEL1_FILENAME ??= "${COREOS_KERNEL1_NAME}${COREOS_KERNEL_EXT}"
|
||||
COREOS_KERNEL1 ??= "${DEPLOY_DIR_IMAGE}/${COREOS_KERNEL1_FILENAME}"
|
||||
COREOS_KERNEL_NAME ??= "kernel-${MACHINE}"
|
||||
COREOS_KERNEL_FILENAME ??= "${COREOS_KERNEL_NAME}${COREOS_KERNEL_EXT}"
|
||||
COREOS_KERNEL ??= "${DEPLOY_DIR_IMAGE}/${COREOS_KERNEL_FILENAME}"
|
||||
|
||||
# Kernel command line
|
||||
# ==============================================================================
|
||||
|
||||
APPEND += "rootwait "
|
||||
COREOS_PLATFORM0_ROOT ??= "PARTLABEL=platform0"
|
||||
COREOS_PLATFORM1_ROOT ??= "PARTLABEL=platform1"
|
||||
COREOS_KERNEL0_CMDLINE ??= "root=${COREOS_PLATFORM0_ROOT} ${APPEND}"
|
||||
COREOS_KERNEL1_CMDLINE ??= "root=${COREOS_PLATFORM1_ROOT} ${APPEND}"
|
||||
# AUTOLABEL will be replaced by the right PARTLABEL (rootfs0 or rootfs1) at
|
||||
# runtime in the efibootguard UKI stub
|
||||
COREOS_ROOTFS_ROOT ??= "PARTLABEL=AUTOLABEL"
|
||||
COREOS_KERNEL_CMDLINE ??= "root=${COREOS_ROOTFS_ROOT} ${APPEND} rootwait"
|
||||
|
||||
COREOS_UKI_PART_KERNEL_FILENAME ??= "${KERNEL_IMAGETYPE}-${MACHINE}${KERNEL_IMAGE_BIN_EXT}"
|
||||
COREOS_UKI_PART_KERNEL ??= "${DEPLOY_DIR_IMAGE}/${COREOS_UKI_PART_KERNEL_FILENAME}"
|
||||
COREOS_UKI_PART_STUB_FILENAME ??= "kernel-stub${EFI_ARCH}.efi"
|
||||
COREOS_UKI_PART_STUB ??= "${STAGING_LIBDIR}/efibootguard/${COREOS_UKI_PART_STUB_FILENAME}"
|
||||
|
||||
COREOS_UKI_PART_INITRAMFS ??= ""
|
||||
|
||||
# UKI Generation
|
||||
# ==============================================================================
|
||||
|
||||
do_bundle_uki() {
|
||||
do_image_uki() {
|
||||
deployDir="${DEPLOY_DIR_IMAGE}"
|
||||
|
||||
# Create an array with device tree if any
|
||||
|
|
@ -49,26 +45,35 @@ do_bundle_uki() {
|
|||
|
||||
echo "kernel: ${COREOS_UKI_PART_KERNEL_FILENAME}"
|
||||
echo "dtb: ${DTB_PARAMS}"
|
||||
echo "cmdline0: ${COREOS_KERNEL0_CMDLINE}"
|
||||
echo "cmdline1: ${COREOS_KERNEL1_CMDLINE}"
|
||||
echo "cmdline: ${COREOS_KERNEL_CMDLINE}"
|
||||
echo "initramfs: ${COREOS_UKI_PART_INITRAMFS}"
|
||||
|
||||
if [ ! -z "${COREOS_UKI_PART_INITRAMFS}" ]; then
|
||||
DTB_PARAMS="${DTB_PARAMS} --initrd=${COREOS_UKI_PART_INITRAMFS}"
|
||||
fi
|
||||
|
||||
echo "initramfs: ${INITRAMFS_PARAMS}"
|
||||
|
||||
bg_gen_unified_kernel \
|
||||
"${COREOS_UKI_PART_STUB}" \
|
||||
"${COREOS_UKI_PART_KERNEL}" \
|
||||
"${COREOS_KERNEL0}" \
|
||||
--cmdline "${COREOS_KERNEL0_CMDLINE}" \
|
||||
"${COREOS_KERNEL}" \
|
||||
--cmdline "${COREOS_KERNEL_CMDLINE}" \
|
||||
${DTB_PARAMS}
|
||||
|
||||
bg_gen_unified_kernel \
|
||||
"${COREOS_UKI_PART_STUB}" \
|
||||
"${COREOS_UKI_PART_KERNEL}" \
|
||||
"${COREOS_KERNEL1}" \
|
||||
--cmdline "${COREOS_KERNEL1_CMDLINE}" \
|
||||
${DTB_PARAMS}
|
||||
|
||||
coreos_efi_secureboot_sign_app "${deployDir}/${COREOS_KERNEL0_FILENAME}"
|
||||
coreos_efi_secureboot_sign_app "${deployDir}/${COREOS_KERNEL1_FILENAME}"
|
||||
coreos_efi_secureboot_sign_app "${deployDir}/${COREOS_KERNEL_FILENAME}"
|
||||
}
|
||||
|
||||
do_bundle_uki[depends] += "virtual/kernel:do_deploy efibootguard-native:do_populate_sysroot efibootguard:do_populate_sysroot"
|
||||
addtask bundle_uki after do_rootfs before do_image
|
||||
do_image_uki[depends] += "virtual/kernel:do_deploy efibootguard-native:do_populate_sysroot efibootguard:do_populate_sysroot"
|
||||
|
||||
|
||||
addtask image_uki after do_image before do_image_complete
|
||||
|
||||
# UKI image is normally embedded into a WIC image
|
||||
do_image_wic[recrdeptask] += "do_image_uki"
|
||||
|
||||
# UKI image is normally embedded into a SWU image
|
||||
do_image_swu[recrdeptask] += "${@'do_image_uki' if d.getVar('COREOS_IMAGE_GENERATE_SWU') == '1' else ''}"
|
||||
|
||||
# UKI image may embedded the rootfs as a cpio archive, in this case do_image_uki should run after do_image_cpio
|
||||
do_image_uki[recrdeptask] += "${@'do_image_cpio' if d.getVar('COREOS_UKI_PART_INITRAMFS') else ''}"
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ FEATURE_PACKAGES_cockpit = "packagegroup-coreos-cockpit ${@get_feature_packages_
|
|||
# *-dev-tools FEATURES_PACKAGES for any image features
|
||||
FEATURE_PACKAGES_dev-tools = "${@get_feature_packages_with_suffix('dev-tools', d)}"
|
||||
|
||||
|
||||
def get_feature_packages_with_suffix(suffix, d):
|
||||
"""
|
||||
For each feature inside IMAGE_FEATURES, look if a FEATURE_PACKAGE variable
|
||||
|
|
@ -89,9 +90,13 @@ IMAGE_ROOTFS_EXTRA_SPACE:append = " ${@bb.utils.contains('DISTRO_FEATURES', 'sys
|
|||
# ==============================================================================
|
||||
|
||||
# Support for Unified Kernel Image and Swupdate are optional
|
||||
COREOS_IMAGE_GENERATE_INSTALLER ?= "1"
|
||||
COREOS_IMAGE_GENERATE_UKI ?= "1"
|
||||
COREOS_IMAGE_GENERATE_SWU ?= "1"
|
||||
|
||||
# Generate the installer image if needed
|
||||
do_build[depends] += "${@'coreos-image-installer:do_build' if d.getVar('COREOS_IMAGE_GENERATE_INSTALLER') == '1' else ''}"
|
||||
|
||||
COREOS_IMAGE_EXTRACLASSES += "${@'coreos-image-uki' if d.getVar('COREOS_IMAGE_GENERATE_UKI') == '1' else ''}"
|
||||
COREOS_IMAGE_EXTRACLASSES += "${@'coreos-image-swupdate' if d.getVar('COREOS_IMAGE_GENERATE_SWU') == '1' else ''}"
|
||||
|
||||
|
|
|
|||
|
|
@ -78,3 +78,10 @@ INHERIT += "coreos-efi-secureboot"
|
|||
#PREFERRED_PROVIDER_virtual/runc = "crun"
|
||||
PACKAGECONFIG:append:pn-podman = " rootless"
|
||||
DISTRO_FEATURES_DEFAULT += "virtualization seccomp ipv6"
|
||||
|
||||
# CoreOS specific options
|
||||
# ==============================================================================
|
||||
|
||||
# Distro based on CoreOS can provide their own configuration files for the
|
||||
# CoreOS installer by overriding this variable
|
||||
PREFERRED_PROVIDER_coreos-installer-config ??= "coreos-installer-config"
|
||||
|
|
|
|||
|
|
@ -12,26 +12,39 @@ software =
|
|||
installed-directly = true;
|
||||
# partlabel are stored inside the GPT partition table.
|
||||
# The partition table is flashed only once and never updated
|
||||
device = "@@COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY@@/platform0";
|
||||
device = "/dev/disk/by-partlabel/rootfs0";
|
||||
type = "raw";
|
||||
sha256 = "$swupdate_get_sha256(@@PN@@-@@MACHINE@@.ext4.zst)";
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(images)
|
||||
);
|
||||
|
||||
files: (
|
||||
{
|
||||
filename = "@@COREOS_KERNEL0_FILENAME@@";
|
||||
filename = "@@COREOS_KERNEL_FILENAME@@";
|
||||
path = "/KERNEL.EFI";
|
||||
device = "@@COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY@@/boot0";
|
||||
device = "/dev/disk/by-partlabel/ebg0";
|
||||
filesystem = "vfat";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_KERNEL0_FILENAME@@)";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_KERNEL_FILENAME@@)";
|
||||
},
|
||||
{
|
||||
filename = "@@COREOS_EFIBOOTGUARD_FILENAME@@";
|
||||
path = "@@EFIDIR@@/@@EFI_BOOT_IMAGE@@";
|
||||
device = "/dev/disk/by-partlabel/efi";
|
||||
filesystem = "vfat";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_EFIBOOTGUARD_FILENAME@@)";
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(files)
|
||||
);
|
||||
|
||||
bootenv: (
|
||||
{
|
||||
name = "kernelparams";
|
||||
value = "root=PARTLABEL=platform0 @@APPEND@@";
|
||||
value = "coreos.root=rootfs0";
|
||||
},
|
||||
{
|
||||
name = "watchdog_timeout_sec";
|
||||
|
|
@ -39,9 +52,12 @@ software =
|
|||
},
|
||||
{
|
||||
name = "kernelfile";
|
||||
value = "C:BOOT0:KERNEL.EFI";
|
||||
value = "C:EBG0:KERNEL.EFI";
|
||||
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(bootenv)
|
||||
);
|
||||
}
|
||||
|
||||
|
|
@ -53,25 +69,38 @@ software =
|
|||
installed-directly = true;
|
||||
# partlabel are stored inside the GPT partition table.
|
||||
# The partition table is flashed only once and never updated
|
||||
device = "@@COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY@@/platform1";
|
||||
device = "/dev/disk/by-partlabel/rootfs1";
|
||||
type = "raw";
|
||||
sha256 = "$swupdate_get_sha256(@@PN@@-@@MACHINE@@.ext4.zst)";
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(images)
|
||||
);
|
||||
|
||||
files: (
|
||||
{
|
||||
filename = "@@COREOS_KERNEL1_FILENAME@@";
|
||||
filename = "@@COREOS_KERNEL_FILENAME@@";
|
||||
path = "/KERNEL.EFI";
|
||||
device = "@@COREOS_DISK_PARTLABEL_LOOKUP_DIRECTORY@@/boot1";
|
||||
device = "/dev/disk/by-partlabel/ebg1";
|
||||
filesystem = "vfat";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_KERNEL1_FILENAME@@)";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_KERNEL_FILENAME@@)";
|
||||
},
|
||||
{
|
||||
filename = "@@COREOS_EFIBOOTGUARD_FILENAME@@";
|
||||
path = "@@EFIDIR@@/@@EFI_BOOT_IMAGE@@";
|
||||
device = "/dev/disk/by-partlabel/efi";
|
||||
filesystem = "vfat";
|
||||
sha256 = "$swupdate_get_sha256(@@COREOS_EFIBOOTGUARD_FILENAME@@)";
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(files)
|
||||
);
|
||||
bootenv: (
|
||||
{
|
||||
name = "kernelparams";
|
||||
value = "root=PARTLABEL=platform1 @@APPEND@@";
|
||||
value = "coreos.root=rootfs1";
|
||||
},
|
||||
{
|
||||
name = "watchdog_timeout_sec";
|
||||
|
|
@ -79,9 +108,12 @@ software =
|
|||
},
|
||||
{
|
||||
name = "kernelfile";
|
||||
value = "C:BOOT1:KERNEL.EFI";
|
||||
value = "C:EBG1:KERNEL.EFI";
|
||||
|
||||
}
|
||||
# Don't remove the trailing whitspace on the next line otherwise
|
||||
# it will not work due to a regex bug in meta-swupdate
|
||||
$coreos_swupdate_extends(bootenv)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -272,40 +272,24 @@ def efibootguard_generate_uki(args, config, basepath, workspace):
|
|||
|
||||
keydir = os.path.relpath(rd.getVar("COREOS_EFI_SECUREBOOT_KEYDIR"))
|
||||
|
||||
uki0 = UKIGeneratorArgs(
|
||||
uki = UKIGeneratorArgs(
|
||||
kernel=kernel,
|
||||
output=os.path.relpath(rd.getVar("COREOS_KERNEL0")),
|
||||
cmdline=rd.getVar("COREOS_KERNEL0_CMDLINE"),
|
||||
output=os.path.relpath(rd.getVar("COREOS_KERNEL")),
|
||||
cmdline=rd.getVar("COREOS_KERNEL_CMDLINE"),
|
||||
dtb=dtb,
|
||||
stub=stub,
|
||||
root=rd.getVar("COREOS_PLATFORM0_ROOT"),
|
||||
build_binary=build_binary,
|
||||
keydir=keydir,
|
||||
)
|
||||
uki1 = UKIGeneratorArgs(
|
||||
kernel=kernel,
|
||||
output=os.path.relpath(rd.getVar("COREOS_KERNEL1")),
|
||||
cmdline=rd.getVar("COREOS_KERNEL1_CMDLINE"),
|
||||
dtb=dtb,
|
||||
stub=stub,
|
||||
root=rd.getVar("COREOS_PLATFORM1_ROOT"),
|
||||
root=rd.getVar("COREOS_ROOTFS_ROOT"),
|
||||
build_binary=build_binary,
|
||||
keydir=keydir,
|
||||
)
|
||||
|
||||
print(f"Applying passed parameters...")
|
||||
uki0.process_args(args)
|
||||
uki1.process_args(args)
|
||||
uki.process_args(args)
|
||||
|
||||
print(f"KERNEL0 image will be generated with the following settings:")
|
||||
printi(f"{uki0}", 1)
|
||||
print()
|
||||
print(f"KERNEL1 image will be generated with the following settings:")
|
||||
printi(f"{uki1}", 1)
|
||||
print(f"KERNEL image will be generated with the following settings:")
|
||||
printi(f"{uki}", 1)
|
||||
print()
|
||||
|
||||
print(f"Generating the files...")
|
||||
r = uki0.build_and_sign()
|
||||
r += uki1.build_and_sign()
|
||||
return uki0.build_and_sign()
|
||||
|
||||
return r
|
||||
|
|
|
|||
|
|
@ -0,0 +1,93 @@
|
|||
From 2e8b73826c6ecaf5168002a18282ba7e4ac95e76 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Mon, 12 Jun 2023 16:29:49 +0200
|
||||
Subject: [PATCH] coreos: add a coreos specific rootfs switch to the UKI stub
|
||||
|
||||
The unified kernel stub can now replace the substring "AUTOLABEL"
|
||||
in the built-in kernel command line by either rootfs0 and rootfs1
|
||||
by looking the LoadOption string passed by ther firmware:
|
||||
- LoadOptions contain "coreos.root=rootfs0", all occurences of
|
||||
"AUTOLABEL" are replaced by "rootfs0"
|
||||
- LoadOptions contain "coreos.root=rootfs1", all occurences of
|
||||
"AUTOLABEL" are replaced by "rootfs1".
|
||||
- LoadOptions is empty, the kernel command line will be used as is.
|
||||
|
||||
In all other case, the stub will exist without booting the kernel
|
||||
with a INVALID PARAMETER error.
|
||||
---
|
||||
kernel-stub/main.c | 55 +++++++++++++++++++++++++++++++++++++++++-----
|
||||
1 file changed, 50 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/kernel-stub/main.c b/kernel-stub/main.c
|
||||
index c0be1f6..6f456d3 100644
|
||||
--- a/kernel-stub/main.c
|
||||
+++ b/kernel-stub/main.c
|
||||
@@ -128,11 +128,6 @@ EFI_STATUS efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE *system_table)
|
||||
error_exit(L"Error getting LoadedImageProtocol", status);
|
||||
}
|
||||
|
||||
- /* consider zero-termination for string length */
|
||||
- if (stub_image->LoadOptionsSize > sizeof(CHAR16)) {
|
||||
- info(L"WARNING: Passed command line options ignored, only built-in used");
|
||||
- }
|
||||
-
|
||||
pe_header = get_pe_header(stub_image->ImageBase);
|
||||
for (n = 0, section = get_sections(pe_header);
|
||||
n < pe_header->Coff.NumberOfSections;
|
||||
@@ -161,6 +156,56 @@ EFI_STATUS efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE *system_table)
|
||||
kernel_image.LoadOptions = (UINT8 *) stub_image->ImageBase +
|
||||
cmdline_section->VirtualAddress;
|
||||
kernel_image.LoadOptionsSize = cmdline_section->VirtualSize;
|
||||
+
|
||||
+ /* CoreOS utilize the option passed from efibootguard to customize the kernel
|
||||
+ * command line.
|
||||
+ *
|
||||
+ * Allowed option are:
|
||||
+ * 'coreos.root=rootfs0' => replace "AUTOLABEL" with "rootfs0 " in place in the kernel CLI
|
||||
+ * 'coreos.root=rootfs1' => replace "AUTOLABEL" with "rootfs1 " in place in the kernel CLI
|
||||
+ * '' => no option passed
|
||||
+ *
|
||||
+ * Using another option string will return without booting the kernel
|
||||
+ *
|
||||
+ * hint: LoadOptions is a null-terminated wide string
|
||||
+ * hint: sizeof return the number of byte. StrLen the number of characters
|
||||
+ */
|
||||
+ if (stub_image->LoadOptionsSize > sizeof(CHAR16)) {
|
||||
+
|
||||
+ // !!! symbol and rootfs must have the same length !!!
|
||||
+ const CHAR16 symbol[] = L"AUTOLABEL";
|
||||
+ CHAR16 rootfs[] = L"rootfsX ";
|
||||
+
|
||||
+ if (StrnCmp(L"coreos.root=rootfs0", stub_image->LoadOptions, stub_image->LoadOptionsSize) == 0) {
|
||||
+ rootfs[6] = L'0';
|
||||
+ } else if (StrnCmp(L"coreos.root=rootfs1", stub_image->LoadOptions, stub_image->LoadOptionsSize) == 0) {
|
||||
+ rootfs[6] = L'1';
|
||||
+ } else {
|
||||
+ error_exit(L"LoadOptions is not valid", EFI_INVALID_PARAMETER);
|
||||
+ }
|
||||
+
|
||||
+ /* Replace symbol by rootfs (AUTOLABEL by either rootfs0 or rootfs1) */
|
||||
+ CHAR16 * str = kernel_image.LoadOptions;
|
||||
+ UINTN len = kernel_image.LoadOptionsSize;
|
||||
+ while (*str && len) {
|
||||
+
|
||||
+ /* Ensure that the string still contains enough char for the symbol */
|
||||
+ if(len < sizeof(symbol)) {
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if(StrnCmp(str, &symbol, StrLen(symbol)) == 0) {
|
||||
+ /* Replace symbol by rootfs, works because symbole and rootfs has the same length */
|
||||
+ StrnCpy(str, rootfs, StrLen(rootfs));
|
||||
+ }
|
||||
+
|
||||
+ str += 1;
|
||||
+ len -= sizeof(CHAR16);
|
||||
+ }
|
||||
+
|
||||
+ }
|
||||
+
|
||||
+ Print(L"Unified kernel stub: Kernel Options: %s\n", kernel_image.LoadOptions);
|
||||
}
|
||||
|
||||
if (initrd_section) {
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
|
||||
|
||||
SRC_URI += "file://0001-coreos-add-a-coreos-specific-rootfs-switch-to-the-UK.patch"
|
||||
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
DESCRIPTION = "Initramfs image with the CoreOS emmc installer"
|
||||
|
||||
|
||||
|
||||
# Don't reboot the device at reboot and don't do A/B switching
|
||||
BAD_RECOMMENDATIONS = "swupdate-progress swupdate-coreos-config"
|
||||
|
||||
export IMAGE_BASENAME = "${MLPREFIX}${PN}"
|
||||
IMAGE_NAME_SUFFIX ?= ""
|
||||
IMAGE_LINGUAS = ""
|
||||
|
||||
LICENSE = "MIT"
|
||||
|
||||
IMAGE_FSTYPES = "cpio.gz"
|
||||
|
||||
# Support for generating a SDCard installer is optional
|
||||
COREOS_INSTALLER_WKS_FILE ??= ""
|
||||
WKS_FILE = "${COREOS_INSTALLER_WKS_FILE}"
|
||||
IMAGE_FSTYPES += "${@'wic.xz wic.bmap' if d.getVar('COREOS_INSTALLER_WKS_FILE') else ''}"
|
||||
IMAGE_BOOT_FILES = "${COREOS_KERNEL_FILENAME};EFI/BOOT/${EFI_BOOT_IMAGE}"
|
||||
|
||||
COREOS_IMAGE_GENERATE_UKI = "1"
|
||||
|
||||
# Avoid dependancy loop, we are already in an installer image, so we don't need
|
||||
# to bundle another one
|
||||
COREOS_IMAGE_GENERATE_INSTALLER = "0"
|
||||
|
||||
# IMGDEPLOYDIR has to be used instead of DEPLOY_DIR_IMAGE here, because it will
|
||||
# run during image generation
|
||||
COREOS_UKI_PART_INITRAMFS = "${IMGDEPLOYDIR}/${IMAGE_BASENAME}-${MACHINE}.cpio.gz"
|
||||
COREOS_IMAGE_GENERATE_SWU = "0"
|
||||
|
||||
# Change generated UKI filename and reset the bundled command line to "APPEND"
|
||||
# to ensure that root is not set in the kernel command line
|
||||
COREOS_KERNEL_NAME ?= "coreos-installer-${MACHINE}"
|
||||
COREOS_KERNEL_CMDLINE ?= "${APPEND}"
|
||||
|
||||
inherit coreos-image
|
||||
|
||||
# Only install a reduced set of package and feature to keep image size small
|
||||
IMAGE_INSTALL = "packagegroup-coreos-boot coreos-installer swupdate-www util-linux-sfdisk util-linux-fdisk util-linux-cfdisk efibootguard efibootguard-tools"
|
||||
IMAGE_FEATURES = "debug-tweaks swupdate networkmanager"
|
||||
NO_RECOMMENDATIONS = "1"
|
||||
|
||||
IMAGE_ROOTFS_SIZE = "8192"
|
||||
INITRAMFS_MAXSIZE = "976562"
|
||||
IMAGE_ROOTFS_EXTRA_SPACE = "0"
|
||||
|
||||
# Use the same restriction as initramfs-module-install
|
||||
COMPATIBLE_HOST = '(x86_64.*|i.86.*|arm.*|aarch64.*)-(linux.*|freebsd.*)'
|
||||
|
|
@ -3,14 +3,15 @@ DESCRIPTION = "Install swupdate and related components"
|
|||
|
||||
inherit packagegroup
|
||||
|
||||
|
||||
PACKAGES = "\
|
||||
${PN} \
|
||||
"
|
||||
|
||||
RDEPENDS:${PN} = "\
|
||||
swupdate \
|
||||
swupdate-progress \
|
||||
swupdate-client \
|
||||
swupdate-lua \
|
||||
"
|
||||
|
||||
# swupdate-progress will reboot the device at the end of the update
|
||||
RRECOMMENDS:${PN} = "swupdate-progress"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
DESCRIPTION = "CoreOS Installer configuration files"
|
||||
SECTION = "coreos"
|
||||
LICENSE = "CLOSED"
|
||||
|
||||
# This file can be included by a CoreOS based distro to ship a customized
|
||||
# version
|
||||
RPROVIDES:${PN} += "coreos-installer-config"
|
||||
PROVIDES += "coreos-installer-config"
|
||||
|
||||
# This package is intended to ship machine specific configuration file
|
||||
# See bbappend in BSP layers
|
||||
PACKAGE_ARCH = "${MACHINE_ARCH}"
|
||||
|
||||
# If the BSP doesn't provide a machine specific configuration file, this
|
||||
# package will be empty
|
||||
ALLOW_EMPTY:${PN} = "1"
|
||||
|
||||
# Don't run default configure and compile task
|
||||
do_configure[noexex] = "1"
|
||||
|
||||
python do_compile() {
|
||||
from pathlib import Path
|
||||
|
||||
workdir = Path(d.getVar('WORKDIR', True))
|
||||
machine = d.getVar('MACHINE', True)
|
||||
b = Path(d.getVar('B', True))
|
||||
for input_path in workdir.glob(f'{machine}_*.sfdisk'):
|
||||
output_path = b / input_path.relative_to(workdir)
|
||||
process_sfdisk_file(d, input_path, output_path)
|
||||
|
||||
}
|
||||
|
||||
def process_sfdisk_file(d, input_path, output_path):
|
||||
"""
|
||||
Read the file from input_path and write it to output_path with bitbake
|
||||
variable expanded
|
||||
"""
|
||||
with open(output_path, "w") as output_file:
|
||||
with open(input_path, "r") as input_file:
|
||||
for line in input_file.readlines():
|
||||
output_file.write(d.expand(line))
|
||||
|
||||
do_install() {
|
||||
install -d ${D}${sysconfdir}
|
||||
|
||||
# Install all files for the current machine but don't fail if no file is
|
||||
# found
|
||||
install -m 755 ${B}/${MACHINE}_*.sfdisk ${D}${sysconfdir}/ || true
|
||||
}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
# Code is in an include file as they can be reused by a CoreOS distro to ship
|
||||
# an alternative provided for coreos-installer-config using PREFERRED_PROVIDER
|
||||
require coreos-installer-config.inc
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#!/usr/bin/env sh
|
||||
|
||||
# Read /etc/hwrevision and turn it into a stripped string
|
||||
# with the format ${MACHINE}_${VERSION}
|
||||
HWREVISION=$(tr ' ' '_' < /etc/hwrevision | tr -d '[:space:]')
|
||||
|
||||
# Format the disk
|
||||
SFDISK_DUMP_FILE="/etc/${HWREVISION}.sfdisk"
|
||||
|
||||
if [ ! -f "${SFDISK_DUMP_FILE}" ]
|
||||
then
|
||||
echo "Configuration file ${SFDISK_DUMP_FILE} not found"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
DISK=$(grep "^device:\s" < "${SFDISK_DUMP_FILE}" | cut -d ' ' -f 2)
|
||||
|
||||
echo "Flashing ${SFDISK_DUMP_FILE} to ${DISK}"
|
||||
cat "${SFDISK_DUMP_FILE}"
|
||||
sfdisk "${DISK}" < "${SFDISK_DUMP_FILE}"
|
||||
|
||||
# Give the kernel some time to reload the partition
|
||||
sleep 3
|
||||
|
||||
# Create EFI and EFIBootGuard partition as FAT16
|
||||
mkfs.fat -F 16 -n EFI /dev/disk/by-partlabel/efi
|
||||
mkfs.fat -F 16 -n EBG0 /dev/disk/by-partlabel/ebg0
|
||||
mkfs.fat -F 16 -n EBG1 /dev/disk/by-partlabel/ebg1
|
||||
|
||||
mkdir -p /mnt/ebg0
|
||||
mkdir -p /mnt/ebg1
|
||||
mkdir -p /mnt/efi
|
||||
|
||||
mount /dev/disk/by-partlabel/ebg0 /mnt/ebg0
|
||||
mount /dev/disk/by-partlabel/ebg1 /mnt/ebg1
|
||||
mount /dev/disk/by-partlabel/efi /mnt/efi
|
||||
|
||||
mkdir -p /mnt/efi/EFI/BOOT
|
||||
|
||||
echo -n "EBG0" | iconv -f ascii -t UTF-16LE > /mnt/ebg0/EFILABEL
|
||||
bg_setenv -f /mnt/ebg0/BGENV.DAT -r 0 -s FAILED
|
||||
|
||||
echo -n "EBG1" | iconv -f ascii -t UTF-16LE > /mnt/ebg1/EFILABEL
|
||||
bg_setenv -f /mnt/ebg1/BGENV.DAT -r 0 -s FAILED
|
||||
|
||||
umount /mnt/ebg0
|
||||
umount /mnt/ebg1
|
||||
umount /mnt/efi
|
||||
|
||||
SWUPDATE_ARGS="${SWUPDATE_ARGS} -e stable,copy0"
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
DESCRIPTION = "CoreOS Installer scripts"
|
||||
LICENSE = "CLOSED"
|
||||
SECTION = "coreos"
|
||||
|
||||
SRC_URI+= " \
|
||||
file://25-installer-config.sh \
|
||||
"
|
||||
|
||||
# This package ship an alternate configuration for SWUpade to disable A/B
|
||||
# switching and always flash A
|
||||
RCONFLICTS:${PN}= "swupdate-coreos-config"
|
||||
|
||||
FILES:${PN} = " \
|
||||
${libdir}/swupdate/conf.d/25-installer-config.sh \
|
||||
"
|
||||
|
||||
# glibc-utils provide iconv
|
||||
# glibc-gconv-utf-16 provide utf-16 support to iconv
|
||||
RDEPENDS:${PN} = "coreos-installer-config dosfstools util-linux-lsblk util-linux-sfdisk glibc-utils glibc-gconv-utf-16"
|
||||
|
||||
do_install() {
|
||||
install -d ${D}${libdir}/swupdate/conf.d
|
||||
install -m 755 ${WORKDIR}/25-installer-config.sh ${D}${libdir}/swupdate/conf.d/
|
||||
}
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From 323c7fdda60758506dea9da6c477e42a0dbe86ca Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Wed, 22 Feb 2023 13:22:27 +0100
|
||||
Subject: [PATCH] fs: add support to create FAT16 partition
|
||||
|
||||
Currently swupdate can create vfat partition using an embedded
|
||||
copy of the fat_fs library. The partition created by fat_fs is
|
||||
can be any FAT format (12/16/32) based on the partition size.
|
||||
|
||||
As the partition created by fat_fs was not readable by U-Boot,
|
||||
this commit add a new "fat16" filesystem type that use the
|
||||
external binary mkfs.fat to always create FAT16 partition.
|
||||
---
|
||||
fs/diskformat.c | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
diff --git a/fs/diskformat.c b/fs/diskformat.c
|
||||
index 8d58fc3..f98c9d7 100644
|
||||
--- a/fs/diskformat.c
|
||||
+++ b/fs/diskformat.c
|
||||
@@ -19,6 +19,21 @@ static inline int ext_mkfs_short(const char *device_name, const char *fstype)
|
||||
}
|
||||
#endif
|
||||
|
||||
+int fat_mkfs_extern(const char *device_name, const char *fstype)
|
||||
+{
|
||||
+ char cmd[100] = "mkfs.fat -F ";
|
||||
+ if(strcmp(fstype, "fat16") == 0){
|
||||
+ strcat(cmd, "16 ");
|
||||
+ } else {
|
||||
+ ERROR("fat_mkfs_extern: unsupported fstype %s", fstype);
|
||||
+ return -1;
|
||||
+ }
|
||||
+ strncat(cmd, device_name, sizeof(cmd) - strlen(cmd) - 1);
|
||||
+
|
||||
+ TRACE("fat_mkfs_extern: running %s", cmd);
|
||||
+ return system(cmd);
|
||||
+}
|
||||
+
|
||||
struct supported_filesystems {
|
||||
const char *fstype;
|
||||
int (*mkfs)(const char *device_name, const char *fstype);
|
||||
@@ -28,6 +43,7 @@ static struct supported_filesystems fs[] = {
|
||||
#if defined(CONFIG_FAT_FILESYSTEM)
|
||||
{"vfat", fat_mkfs},
|
||||
#endif
|
||||
+ {"fat16", fat_mkfs_extern},
|
||||
#if defined(CONFIG_EXT_FILESYSTEM)
|
||||
{"ext2", ext_mkfs_short},
|
||||
{"ext3", ext_mkfs_short},
|
||||
|
|
@ -17,18 +17,18 @@ echo "Root partition is on device ${DISK_DEVICE_NAME} - type ${DISK_PARTITION_TY
|
|||
if [ "${DISK_PARTITION_TYPE}" == "gpt" ]; then
|
||||
ROOT_PARTLABEL=$(lsblk -dno PARTLABEL "${ROOT_PART}")
|
||||
else
|
||||
echo "Using MBR disk is less reliable than GPT disk!"
|
||||
ROOT_PARTLABEL=$(lsblk -dno LABEL "${ROOT_PART}")
|
||||
echo "Using MBR is not supported"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
echo "Root partition label is ${ROOT_PARTLABEL}"
|
||||
|
||||
case $ROOT_PARTLABEL in
|
||||
platform0 )
|
||||
rootfs0 )
|
||||
echo "We are running copy0 -> Use copy1 in the SWU file"
|
||||
SWUPDATE_ARGS="${SWUPDATE_ARGS} -e stable,copy1"
|
||||
;;
|
||||
platform1 )
|
||||
rootfs1 )
|
||||
echo "We are running copy1 -> Use copy0 in the SWU file"
|
||||
SWUPDATE_ARGS="${SWUPDATE_ARGS} -e stable,copy0"
|
||||
;;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# File in the swupdate subdirectory of this recipe should overwrite the
|
||||
# same file in meta-swupdate
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/swupdate:"
|
||||
|
||||
SRC_URI += "\
|
||||
file://50-webserver-config.sh \
|
||||
file://25-sw-collections-config.sh \
|
||||
"
|
||||
|
||||
PACKAGES =+ "${PN}-coreos-config ${PN}-coreos-installer-config"
|
||||
|
||||
|
||||
# Don't use /www as the web root
|
||||
wwwdir = "${datadir}/swupdate-www"
|
||||
|
||||
# Add the hwrevision files to the main package to prevent
|
||||
# installation of .swu image built for another machine
|
||||
FILES:${PN} += "${sysconfdir}/hwrevision"
|
||||
|
||||
# If we install the webserver package, it should be started automatically
|
||||
FILES:${PN}-www += "${libdir}/swupdate/conf.d/50-webserver-config.sh"
|
||||
|
||||
FILES:${PN}-coreos-config += "${libdir}/swupdate/conf.d/25-sw-collections-config.sh"
|
||||
|
||||
RDEPENDS:${PN}:append = " efibootguard"
|
||||
|
||||
# lsblk is used in sw-collections-config.sh
|
||||
RDEPENDS:${PN}-coreos-config += "util-linux-lsblk"
|
||||
|
||||
# Recommends by default the configuration used for normal image
|
||||
# that contain the A/B update path switch
|
||||
RRECOMMENDS:${PN} += "${PN}-coreos-config"
|
||||
|
||||
# The installer configuration should prevent the normal A/B switch
|
||||
# configuration to be installed
|
||||
RCONFLICTS:${PN}-coreos-installer-config = "${PN}-coreos-config"
|
||||
|
||||
do_install:append() {
|
||||
# Probably replace revision with the value of the device tree
|
||||
install -m 755 ${WORKDIR}/50-webserver-config.sh ${D}${libdir}/swupdate/conf.d/
|
||||
install -m 755 ${WORKDIR}/25-sw-collections-config.sh ${D}${libdir}/swupdate/conf.d/
|
||||
echo "${MACHINE} 1.0" > ${D}${sysconfdir}/hwrevision
|
||||
}
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
# File in the swupdate subdirectory of this recipe should overwrite the
|
||||
# same file in meta-swupdate
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/swupdate:"
|
||||
RDEPENDS:${PN}:append = " efibootguard"
|
||||
|
||||
SRC_URI += "file://webserver-config.sh \
|
||||
file://sw-collections-config.sh \
|
||||
file://0001-fs-add-support-to-create-FAT16-partition.patch \
|
||||
"
|
||||
|
||||
# 0001-fs-add-support-to-create-FAT16-partition.patch depends on the
|
||||
# mkfs.fat binary
|
||||
RDEPENDS:${PN} += "dosfstools"
|
||||
|
||||
# Don't use /www as the web root
|
||||
wwwdir = "/usr/share/swupdate-www"
|
||||
|
||||
FILES:${PN} += " \
|
||||
${SWUPDATE_SW_VERSIONS_FILE} \
|
||||
${SWUPDATE_HW_COMPATIBILITY_FILE} \
|
||||
${libdir}/swupdate/conf.d/sw-collections-config.sh \
|
||||
"
|
||||
|
||||
FILES:${PN}-www += " \
|
||||
${libdir}/swupdate/conf.d/webserver-config.sh \
|
||||
"
|
||||
|
||||
do_install:append() {
|
||||
# Probably replace revision with the value of the device tree
|
||||
install -m 755 ${WORKDIR}/webserver-config.sh ${D}${libdir}/swupdate/conf.d/
|
||||
|
||||
install -m 755 ${WORKDIR}/sw-collections-config.sh ${D}${libdir}/swupdate/conf.d/
|
||||
echo "${MACHINE} 1.0" > ${D}${SWUPDATE_HW_COMPATIBILITY_FILE}
|
||||
}
|
||||
|
||||
PR = "r1"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
|
||||
SWUPDATE_IMAGES += "flash-image"
|
||||
SWUPDATE_IMAGES_FSTYPES[flash-image] = ".bin"
|
||||
|
||||
COREOS_SWUPDATE_EXTENDS_FOR:append = "cn913x"
|
||||
|
||||
def coreos_swupdate_extends_images_for_cn913x(d,s):
|
||||
boot0 = {
|
||||
"filename" : "flash-image.bin",
|
||||
"installed-directly" : "true",
|
||||
"device" : "/dev/disk/by-partlabel/fw0",
|
||||
"type" : "raw",
|
||||
"sha256" : swupdate_get_sha256(d, s, "flash-image.bin"),
|
||||
}
|
||||
|
||||
boot1 = boot0.copy()
|
||||
boot1["device"] = "/dev/disk/by-partlabel/fw1"
|
||||
|
||||
|
||||
return [boot0, boot1]
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#@TYPE: Machine
|
||||
#@NAME: cn9130-bldn-mbv
|
||||
#@DESCRIPTION: CN9130 SOM based on Bldn MBV-A/B
|
||||
#
|
||||
|
||||
require conf/machine/include/cn913x.inc
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#@TYPE: Machine
|
||||
#@NAME: cn9131-bldn-mbv
|
||||
#@DESCRIPTION: CN9131 SOM based on Bldn MBV-A/B
|
||||
#
|
||||
|
||||
require conf/machine/include/cn913x.inc
|
||||
|
||||
### Device specific settings
|
||||
# Needed for phy firmware
|
||||
MACHINE_EXTRA_RDEPENDS += "linux-firmware-microchip"
|
||||
|
|
@ -11,7 +11,7 @@ require conf/machine/include/soc-family.inc
|
|||
# *****************************************************************************
|
||||
|
||||
PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
|
||||
PREFERRED_VERSION_u-boot ?= "2023.04-marvell"
|
||||
PREFERRED_VERSION_u-boot ?= "2019.10-solidrun"
|
||||
|
||||
# All cn913x use the same defconfig for u-boot, but another devicetree by
|
||||
# settings UBOOT_BUILDENV_DEVICE_TREE in the machine configuration file
|
||||
|
|
@ -51,10 +51,13 @@ APPEND += "console=ttyS0,115200"
|
|||
# for a wic image
|
||||
do_image_wic[depends] += "trusted-firmware-a:do_deploy"
|
||||
WKS_FILE = "cn913x-sdcard.wks.in"
|
||||
COREOS_INSTALLER_WKS_FILE ?= "cn913x-sdcard-installer.wks"
|
||||
IMAGE_FSTYPES += "wic.xz wic.bmap"
|
||||
|
||||
MACHINE_ESSENTIAL_EXTRA_RDEPENDS += " kernel-modules kernel-devicetree"
|
||||
COREOS_IMAGE_SWUPDATE_EXTRACLASSES += " coreos-image-swupdate-cn913x"
|
||||
|
||||
# No watchdog available yet
|
||||
EFIBOOTGUARD_TIMEOUT ?= "0"
|
||||
require conf/machine/include/coreos-generic-features/efi.inc
|
||||
require conf/machine/include/coreos-generic-features/partitions.inc
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@ COMPATIBLE_MACHINE = "cn913x"
|
|||
|
||||
DEPENDS += "mv-ddr-marvell coreutils-native"
|
||||
|
||||
CP_NUM:cn9132 = "3"
|
||||
CP_NUM:cn9130 = "1"
|
||||
CP_NUM:cn9131-bldn-mbv = "2"
|
||||
CP_NUM:cn9130-cf-pro = "1"
|
||||
|
||||
TFA_PLATFORM = "t9130"
|
||||
TFA_BUILD_TARGET = "all mrvl_flash"
|
||||
|
|
@ -27,4 +27,4 @@ TFA_UBOOT = "1"
|
|||
TFA_UEFI = "0"
|
||||
|
||||
|
||||
EXTRA_OEMAKE += "MV_DDR_PATH=${PKG_CONFIG_SYSROOT_DIR}/usr/src/mv-ddr-marvell CP_NUM=${CP_NUM} SCP_BL2=${WORKDIR}/mrvl_scp_bl2.img"
|
||||
EXTRA_OEMAKE += "USE_COHERENT_MEM=0 LOG_LEVEL=20 MV_DDR_PATH=${PKG_CONFIG_SYSROOT_DIR}/usr/src/mv-ddr-marvell CP_NUM=${CP_NUM} SCP_BL2=${WORKDIR}/mrvl_scp_bl2.img"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
From 0e0801291261a2c1267a42905d647cc0d1140791 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Robinson <pbrobinson@gmail.com>
|
||||
Date: Thu, 30 Jan 2020 09:37:15 +0000
|
||||
Subject: [PATCH] Remove redundant YYLOC global declaration
|
||||
|
||||
Same as the upstream fix for building dtc with gcc 10.
|
||||
|
||||
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
||||
---
|
||||
scripts/dtc/dtc-lexer.l | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
|
||||
index fd825ebba6..24af549977 100644
|
||||
--- a/scripts/dtc/dtc-lexer.l
|
||||
+++ b/scripts/dtc/dtc-lexer.l
|
||||
@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n
|
||||
#include "srcpos.h"
|
||||
#include "dtc-parser.tab.h"
|
||||
|
||||
-YYLTYPE yylloc;
|
||||
extern bool treesource_error;
|
||||
|
||||
/* CAUTION: this will stop working if we ever use yyless() or yyunput() */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
From 841657cef0b50f6e3af4d3d3c829e438fbac7cc3 Mon Sep 17 00:00:00 2001
|
||||
From: Patrick Vogelaar <patrick.vogelaar@belden.com>
|
||||
Date: Wed, 19 Apr 2023 09:07:10 +0200
|
||||
Subject: [PATCH] fix u-boot device tree compatible
|
||||
|
||||
---
|
||||
arch/arm/dts/cn9131-bldn-mbv.dts | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
index d10c7f032e..74322805db 100644
|
||||
--- a/arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
+++ b/arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
@@ -11,8 +11,10 @@
|
||||
|
||||
/ {
|
||||
model = "Belden CN9131 based Platform";
|
||||
- compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
|
||||
- "marvell,armada-ap806";
|
||||
+ compatible = "solidrun,cn9131-bldn-mbv", "marvell,cn9130-db",
|
||||
+ "marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
|
||||
+ "marvell,armada-ap806-quad", "marvell,armada-ap806",
|
||||
+ "marvell,armada70x0";
|
||||
};
|
||||
|
||||
&cp1_comphy {
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
From 0017797ce718f4512271deddde75120c57623049 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Tue, 24 Jan 2023 15:22:58 +0100
|
||||
Subject: [PATCH] cn9130: fix compatible node inside dts
|
||||
|
||||
---
|
||||
arch/arm/dts/cn9130-bldn-mbv.dts | 7 ++++---
|
||||
arch/arm/dts/cn9130-cex7-A.dts | 7 ++++---
|
||||
arch/arm/dts/cn9130-cf-pro.dts | 7 ++++---
|
||||
3 files changed, 12 insertions(+), 9 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
index 9e10eab008..a91c490218 100644
|
||||
--- a/arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
+++ b/arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
@@ -10,9 +10,10 @@
|
||||
|
||||
/ {
|
||||
model = "Belden CN9130 based SOM and Carrier MBV-A/B";
|
||||
- compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
- "marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
- "marvell,armada-ap806", "marvell,armada70x0";
|
||||
+ compatible = "solidrun,cn9130-bldn-mbv", "marvell,cn9130-db",
|
||||
+ "marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
|
||||
+ "marvell,armada-ap806-quad", "marvell,armada-ap806",
|
||||
+ "marvell,armada70x0";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
diff --git a/arch/arm/dts/cn9130-cex7-A.dts b/arch/arm/dts/cn9130-cex7-A.dts
|
||||
index 209e485822..9995a586f6 100644
|
||||
--- a/arch/arm/dts/cn9130-cex7-A.dts
|
||||
+++ b/arch/arm/dts/cn9130-cex7-A.dts
|
||||
@@ -10,9 +10,10 @@
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 based COM express type 7";
|
||||
- compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
- "marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
- "marvell,armada-ap806", "marvell,armada70x0";
|
||||
+ compatible = "solidrun,cn9130-cex7", "marvell,cn9130-db",
|
||||
+ "marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
|
||||
+ "marvell,armada-ap806-quad", "marvell,armada-ap806",
|
||||
+ "marvell,armada70x0";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
|
||||
index 6931818cf6..dae7a75076 100644
|
||||
--- a/arch/arm/dts/cn9130-cf-pro.dts
|
||||
+++ b/arch/arm/dts/cn9130-cf-pro.dts
|
||||
@@ -10,9 +10,10 @@
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 based SOM ClearFog Pro";
|
||||
- compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
- "marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
- "marvell,armada-ap806", "marvell,armada70x0";
|
||||
+ compatible = "solidrun,cn9130-cf-pro", "marvell,cn9130-db",
|
||||
+ "marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
|
||||
+ "marvell,armada-ap806-quad", "marvell,armada-ap806",
|
||||
+ "marvell,armada70x0";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
From 8b62e225c541fdfcc764582ee80bf0d8a0b6bc65 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Mon, 25 Jul 2022 15:02:00 +0200
|
||||
Subject: [PATCH] sr_cn913x_cex7: enable VERSION_VARIABLE
|
||||
|
||||
---
|
||||
configs/sr_cn913x_cex7_defconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index 3e01b31371..a7c6c9f93e 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -115,3 +115,4 @@ CONFIG_ZSTD=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
+CONFIG_VERSION_VARIABLE=y
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From ca34fc483e68e332c5aa6c3cc98e04604216d846 Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Fri, 15 Jul 2022 15:36:12 +0200
|
||||
Subject: [PATCH] sr_cn913x_cex7: enable more image formats
|
||||
|
||||
---
|
||||
configs/sr_cn913x_cex7_defconfig | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index d7445e9476..3e01b31371 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -105,3 +105,13 @@ CONFIG_I2C_EEPROM=y
|
||||
CONFIG_CMD_TLV_EEPROM=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+# Custom
|
||||
+CONFIG_BZIP2=y
|
||||
+CONFIG_GZIP=y
|
||||
+CONFIG_LZ4=y
|
||||
+CONFIG_LZMA=y
|
||||
+CONFIG_LZO=y
|
||||
+CONFIG_ZSTD=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
From 7e4c3c48c4ed9dcecf5228c6b4480a7c01fc6dca Mon Sep 17 00:00:00 2001
|
||||
From: Samuel Dolt <samuel.dolt@netmodule.com>
|
||||
Date: Tue, 19 Jul 2022 11:21:37 +0200
|
||||
Subject: [PATCH] octeontx2_cn913x: increase CONFIG_SYS_BOOTM_LEN to 32MB
|
||||
|
||||
---
|
||||
include/configs/octeontx2_cn913x.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
|
||||
index d01644fcb5..9edf57c6c2 100644
|
||||
--- a/include/configs/octeontx2_cn913x.h
|
||||
+++ b/include/configs/octeontx2_cn913x.h
|
||||
@@ -22,6 +22,8 @@
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
|
||||
+#define CONFIG_SYS_BOOTM_LEN 0x3200000 /* 32MB */
|
||||
+
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,27 @@
|
|||
From 0dce367ced42c77d4de5c17b52605c6c003a4b20 Mon Sep 17 00:00:00 2001
|
||||
From: Sven Auhagen <Sven.Auhagen@voleatech.de>
|
||||
Date: Sun, 12 Sep 2021 09:25:44 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom
|
||||
|
||||
The function show_eeprom is missing int i if debug is enabled.
|
||||
|
||||
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
|
||||
Reviewed-by: Stefan Roese <sr@denx.de>
|
||||
---
|
||||
cmd/tlv_eeprom.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
|
||||
index 211ab2680f..96d40f4f4d 100644
|
||||
--- a/cmd/tlv_eeprom.c
|
||||
+++ b/cmd/tlv_eeprom.c
|
||||
@@ -166,6 +166,9 @@ static void show_eeprom(u8 *eeprom)
|
||||
{
|
||||
int tlv_end;
|
||||
int curr_tlv;
|
||||
+#ifdef DEBUG
|
||||
+ int i;
|
||||
+#endif
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
struct tlvinfo_tlv *eeprom_tlv;
|
||||
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
From 3a807537ace144e802e3421b29f3eea0e48d2f1f Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Thu, 17 Mar 2022 11:52:34 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable current_dev
|
||||
|
||||
Make tlv_eeprom command device selection an explicit parameter of all
|
||||
function calls.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
cmd/tlv_eeprom.c | 50 ++++++++++++++++++++++----------------------
|
||||
include/tlv_eeprom.h | 3 ++-
|
||||
2 files changed, 27 insertions(+), 26 deletions(-)
|
||||
|
||||
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
|
||||
index 96d40f4f4d..05d28c26c8 100644
|
||||
--- a/cmd/tlv_eeprom.c
|
||||
+++ b/cmd/tlv_eeprom.c
|
||||
@@ -26,18 +26,18 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* File scope function prototypes */
|
||||
static bool is_checksum_valid(u8 *eeprom);
|
||||
-static int read_eeprom(u8 *eeprom);
|
||||
-static void show_eeprom(u8 *eeprom);
|
||||
+static int read_eeprom(int devnum, u8 *eeprom);
|
||||
+static void show_eeprom(int devnum, u8 *eeprom);
|
||||
static void decode_tlv(struct tlvinfo_tlv *tlv);
|
||||
static void update_crc(u8 *eeprom);
|
||||
-static int prog_eeprom(u8 *eeprom);
|
||||
+static int prog_eeprom(int devnum, u8 *eeprom);
|
||||
static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
|
||||
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
|
||||
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
|
||||
static int set_mac(char *buf, const char *string);
|
||||
static int set_date(char *buf, const char *string);
|
||||
static int set_bytes(char *buf, const char *string, int *converted_accum);
|
||||
-static void show_tlv_devices(void);
|
||||
+static void show_tlv_devices(int current_dev);
|
||||
|
||||
/* Set to 1 if we've read EEPROM into memory */
|
||||
static int has_been_read;
|
||||
@@ -45,7 +45,6 @@ static int has_been_read;
|
||||
static u8 eeprom[TLV_INFO_MAX_LEN];
|
||||
|
||||
static struct udevice *tlv_devices[MAX_TLV_DEVICES];
|
||||
-static unsigned int current_dev;
|
||||
|
||||
#define to_header(p) ((struct tlvinfo_header *)p)
|
||||
#define to_entry(p) ((struct tlvinfo_tlv *)p)
|
||||
@@ -122,7 +121,7 @@ static bool is_checksum_valid(u8 *eeprom)
|
||||
*
|
||||
* Read the EEPROM into memory, if it hasn't already been read.
|
||||
*/
|
||||
-static int read_eeprom(u8 *eeprom)
|
||||
+static int read_eeprom(int devnum, u8 *eeprom)
|
||||
{
|
||||
int ret;
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
@@ -132,12 +131,11 @@ static int read_eeprom(u8 *eeprom)
|
||||
return 0;
|
||||
|
||||
/* Read the header */
|
||||
- ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, current_dev);
|
||||
+ ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
|
||||
/* If the header was successfully read, read the TLVs */
|
||||
if (ret == 0 && is_valid_tlvinfo_header(eeprom_hdr))
|
||||
ret = read_tlv_eeprom((void *)eeprom_tlv, HDR_SIZE,
|
||||
- be16_to_cpu(eeprom_hdr->totallen),
|
||||
- current_dev);
|
||||
+ be16_to_cpu(eeprom_hdr->totallen), devnum);
|
||||
|
||||
// If the contents are invalid, start over with default contents
|
||||
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
|
||||
@@ -162,7 +160,7 @@ static int read_eeprom(u8 *eeprom)
|
||||
*
|
||||
* Display the contents of the EEPROM
|
||||
*/
|
||||
-static void show_eeprom(u8 *eeprom)
|
||||
+static void show_eeprom(int devnum, u8 *eeprom)
|
||||
{
|
||||
int tlv_end;
|
||||
int curr_tlv;
|
||||
@@ -177,7 +175,7 @@ static void show_eeprom(u8 *eeprom)
|
||||
return;
|
||||
}
|
||||
|
||||
- printf("TLV: %u\n", current_dev);
|
||||
+ printf("TLV: %u\n", devnum);
|
||||
printf("TlvInfo Header:\n");
|
||||
printf(" Id String: %s\n", eeprom_hdr->signature);
|
||||
printf(" Version: %d\n", eeprom_hdr->version);
|
||||
@@ -386,7 +384,7 @@ static void update_crc(u8 *eeprom)
|
||||
*
|
||||
* Write the EEPROM data from CPU memory to the hardware.
|
||||
*/
|
||||
-static int prog_eeprom(u8 *eeprom)
|
||||
+static int prog_eeprom(int devnum, u8 *eeprom)
|
||||
{
|
||||
int ret = 0;
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
@@ -395,7 +393,7 @@ static int prog_eeprom(u8 *eeprom)
|
||||
update_crc(eeprom);
|
||||
|
||||
eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
|
||||
- ret = write_tlv_eeprom(eeprom, eeprom_len);
|
||||
+ ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
|
||||
if (ret) {
|
||||
printf("Programming failed.\n");
|
||||
return -1;
|
||||
@@ -430,11 +428,12 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
char cmd;
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
+ static unsigned int current_dev = 0;
|
||||
|
||||
// If no arguments, read the EERPOM and display its contents
|
||||
if (argc == 1) {
|
||||
- read_eeprom(eeprom);
|
||||
- show_eeprom(eeprom);
|
||||
+ read_eeprom(current_dev, eeprom);
|
||||
+ show_eeprom(current_dev, eeprom);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -445,7 +444,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
// Read the EEPROM contents
|
||||
if (cmd == 'r') {
|
||||
has_been_read = 0;
|
||||
- if (!read_eeprom(eeprom))
|
||||
+ if (!read_eeprom(current_dev, eeprom))
|
||||
printf("EEPROM data loaded from device to memory.\n");
|
||||
return 0;
|
||||
}
|
||||
@@ -460,7 +459,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
if (argc == 2) {
|
||||
switch (cmd) {
|
||||
case 'w': /* write */
|
||||
- prog_eeprom(eeprom);
|
||||
+ prog_eeprom(current_dev, eeprom);
|
||||
break;
|
||||
case 'e': /* erase */
|
||||
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
|
||||
@@ -473,7 +472,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
show_tlv_code_list();
|
||||
break;
|
||||
case 'd': /* dev */
|
||||
- show_tlv_devices();
|
||||
+ show_tlv_devices(current_dev);
|
||||
break;
|
||||
default:
|
||||
cmd_usage(cmdtp);
|
||||
@@ -883,7 +882,7 @@ static int set_bytes(char *buf, const char *string, int *converted_accum)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static void show_tlv_devices(void)
|
||||
+static void show_tlv_devices(int current_dev)
|
||||
{
|
||||
unsigned int dev;
|
||||
|
||||
@@ -953,14 +952,14 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev_num)
|
||||
/**
|
||||
* write_tlv_eeprom - write the hwinfo to i2c EEPROM
|
||||
*/
|
||||
-int write_tlv_eeprom(void *eeprom, int len)
|
||||
+int write_tlv_eeprom(void *eeprom, int len, int dev)
|
||||
{
|
||||
if (!(gd->flags & GD_FLG_RELOC))
|
||||
return -ENODEV;
|
||||
- if (!tlv_devices[current_dev])
|
||||
+ if (!tlv_devices[dev])
|
||||
return -ENODEV;
|
||||
|
||||
- return i2c_eeprom_write(tlv_devices[current_dev], 0, eeprom, len);
|
||||
+ return i2c_eeprom_write(tlv_devices[dev], 0, eeprom, len);
|
||||
}
|
||||
|
||||
int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
|
||||
@@ -1015,10 +1014,11 @@ int mac_read_from_eeprom(void)
|
||||
int maccount;
|
||||
u8 macbase[6];
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
+ int devnum = 0; // TODO: support multiple EEPROMs
|
||||
|
||||
puts("EEPROM: ");
|
||||
|
||||
- if (read_eeprom(eeprom)) {
|
||||
+ if (read_eeprom(devnum, eeprom)) {
|
||||
printf("Read failed.\n");
|
||||
return -1;
|
||||
}
|
||||
@@ -1083,7 +1083,7 @@ int mac_read_from_eeprom(void)
|
||||
*
|
||||
* This function must be called after relocation.
|
||||
*/
|
||||
-int populate_serial_number(void)
|
||||
+int populate_serial_number(int devnum)
|
||||
{
|
||||
char serialstr[257];
|
||||
int eeprom_index;
|
||||
@@ -1092,7 +1092,7 @@ int populate_serial_number(void)
|
||||
if (env_get("serial#"))
|
||||
return 0;
|
||||
|
||||
- if (read_eeprom(eeprom)) {
|
||||
+ if (read_eeprom(devnum, eeprom)) {
|
||||
printf("Read failed.\n");
|
||||
return -1;
|
||||
}
|
||||
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
|
||||
index 1de2fe2337..aa96c9e8d4 100644
|
||||
--- a/include/tlv_eeprom.h
|
||||
+++ b/include/tlv_eeprom.h
|
||||
@@ -84,11 +84,12 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev);
|
||||
* write_tlv_eeprom - Write the entire EEPROM binary data to the hardware
|
||||
* @eeprom: Pointer to buffer to hold the binary data
|
||||
* @len : Maximum size of buffer
|
||||
+ * @dev : EEPROM device to write
|
||||
*
|
||||
* Note: this routine does not validate the EEPROM data.
|
||||
*
|
||||
*/
|
||||
-int write_tlv_eeprom(void *eeprom, int len);
|
||||
+int write_tlv_eeprom(void *eeprom, int len, int dev);
|
||||
|
||||
/**
|
||||
* read_tlvinfo_tlv_eeprom - Read the TLV from EEPROM, and validate
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
From 28da9685c7e65f70065319921ccaf2d2aea7b185 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Thu, 17 Mar 2022 12:49:46 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable has_been_read
|
||||
|
||||
has_been_read is only used as an optimization for do_tlv_eeprom.
|
||||
Explicitly use and set inside this function, thus making read_eeprom
|
||||
stateless.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
cmd/tlv_eeprom.c | 25 ++++++++++++-------------
|
||||
1 file changed, 12 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
|
||||
index 05d28c26c8..70c1a2e7df 100644
|
||||
--- a/cmd/tlv_eeprom.c
|
||||
+++ b/cmd/tlv_eeprom.c
|
||||
@@ -39,8 +39,6 @@ static int set_date(char *buf, const char *string);
|
||||
static int set_bytes(char *buf, const char *string, int *converted_accum);
|
||||
static void show_tlv_devices(int current_dev);
|
||||
|
||||
-/* Set to 1 if we've read EEPROM into memory */
|
||||
-static int has_been_read;
|
||||
/* The EERPOM contents after being read into memory */
|
||||
static u8 eeprom[TLV_INFO_MAX_LEN];
|
||||
|
||||
@@ -127,9 +125,6 @@ static int read_eeprom(int devnum, u8 *eeprom)
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
struct tlvinfo_tlv *eeprom_tlv = to_entry(&eeprom[HDR_SIZE]);
|
||||
|
||||
- if (has_been_read)
|
||||
- return 0;
|
||||
-
|
||||
/* Read the header */
|
||||
ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
|
||||
/* If the header was successfully read, read the TLVs */
|
||||
@@ -146,10 +141,8 @@ static int read_eeprom(int devnum, u8 *eeprom)
|
||||
update_crc(eeprom);
|
||||
}
|
||||
|
||||
- has_been_read = 1;
|
||||
-
|
||||
#ifdef DEBUG
|
||||
- show_eeprom(eeprom);
|
||||
+ show_eeprom(devnum, eeprom);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
@@ -429,10 +422,15 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
char cmd;
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
static unsigned int current_dev = 0;
|
||||
+ /* Set to devnum if we've read EEPROM into memory */
|
||||
+ static int has_been_read = -1;
|
||||
|
||||
// If no arguments, read the EERPOM and display its contents
|
||||
if (argc == 1) {
|
||||
- read_eeprom(current_dev, eeprom);
|
||||
+ if(has_been_read != current_dev) {
|
||||
+ read_eeprom(current_dev, eeprom);
|
||||
+ has_been_read = current_dev;
|
||||
+ }
|
||||
show_eeprom(current_dev, eeprom);
|
||||
return 0;
|
||||
}
|
||||
@@ -443,14 +441,16 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
|
||||
// Read the EEPROM contents
|
||||
if (cmd == 'r') {
|
||||
- has_been_read = 0;
|
||||
- if (!read_eeprom(current_dev, eeprom))
|
||||
+ has_been_read = -1;
|
||||
+ if (!read_eeprom(current_dev, eeprom)) {
|
||||
printf("EEPROM data loaded from device to memory.\n");
|
||||
+ has_been_read = current_dev;
|
||||
+ }
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Subsequent commands require that the EEPROM has already been read.
|
||||
- if (!has_been_read) {
|
||||
+ if (has_been_read != current_dev) {
|
||||
printf("Please read the EEPROM data first, using the 'tlv_eeprom read' command.\n");
|
||||
return 0;
|
||||
}
|
||||
@@ -506,7 +506,6 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
return 0;
|
||||
}
|
||||
current_dev = devnum;
|
||||
- has_been_read = 0;
|
||||
} else {
|
||||
cmd_usage(cmdtp);
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
From 6578def0ace0d030a02b8c45031d41c5d2ef517e Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Thu, 17 Mar 2022 14:23:22 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom: do_tlv_eeprom: stop using non-api
|
||||
read_eeprom function
|
||||
|
||||
IN the scope of do_tlv_eeprom, the error-checking provided by the
|
||||
read_eeprom function is not required.
|
||||
Instead use the API function read_tlv_eeprom.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
cmd/tlv_eeprom.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
|
||||
index 70c1a2e7df..8a926ba224 100644
|
||||
--- a/cmd/tlv_eeprom.c
|
||||
+++ b/cmd/tlv_eeprom.c
|
||||
@@ -428,7 +428,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
// If no arguments, read the EERPOM and display its contents
|
||||
if (argc == 1) {
|
||||
if(has_been_read != current_dev) {
|
||||
- read_eeprom(current_dev, eeprom);
|
||||
+ read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev);
|
||||
has_been_read = current_dev;
|
||||
}
|
||||
show_eeprom(current_dev, eeprom);
|
||||
@@ -442,7 +442,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
// Read the EEPROM contents
|
||||
if (cmd == 'r') {
|
||||
has_been_read = -1;
|
||||
- if (!read_eeprom(current_dev, eeprom)) {
|
||||
+ if (read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev) == 0) {
|
||||
printf("EEPROM data loaded from device to memory.\n");
|
||||
has_been_read = current_dev;
|
||||
}
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
From 62114ab82feaf919138d2d4377344072c95571de Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Thu, 17 Mar 2022 16:09:02 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom: convert functions used by command to api
|
||||
functions
|
||||
|
||||
- prog_eeprom: write_tlvinfo_tlv_eeprom
|
||||
- update_crc: tlvinfo_update_crc
|
||||
- is_valid_tlv: is_valid_tlvinfo_entry
|
||||
- is_checksum_valid: tlvinfo_check_crc
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
cmd/tlv_eeprom.c | 56 +++++++++++++++----------------------------
|
||||
include/tlv_eeprom.h | 57 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
2 files changed, 76 insertions(+), 37 deletions(-)
|
||||
|
||||
diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
|
||||
index 8a926ba224..271fefc0c6 100644
|
||||
--- a/cmd/tlv_eeprom.c
|
||||
+++ b/cmd/tlv_eeprom.c
|
||||
@@ -25,13 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define MAX_TLV_DEVICES 2
|
||||
|
||||
/* File scope function prototypes */
|
||||
-static bool is_checksum_valid(u8 *eeprom);
|
||||
static int read_eeprom(int devnum, u8 *eeprom);
|
||||
static void show_eeprom(int devnum, u8 *eeprom);
|
||||
static void decode_tlv(struct tlvinfo_tlv *tlv);
|
||||
-static void update_crc(u8 *eeprom);
|
||||
-static int prog_eeprom(int devnum, u8 *eeprom);
|
||||
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
|
||||
static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
|
||||
static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
|
||||
static int set_mac(char *buf, const char *string);
|
||||
@@ -55,18 +51,6 @@ static inline bool is_digit(char c)
|
||||
return (c >= '0' && c <= '9');
|
||||
}
|
||||
|
||||
-/**
|
||||
- * is_valid_tlv
|
||||
- *
|
||||
- * Perform basic sanity checks on a TLV field. The TLV is pointed to
|
||||
- * by the parameter provided.
|
||||
- * 1. The type code is not reserved (0x00 or 0xFF)
|
||||
- */
|
||||
-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
|
||||
-{
|
||||
- return((tlv->type != 0x00) && (tlv->type != 0xFF));
|
||||
-}
|
||||
-
|
||||
/**
|
||||
* is_hex
|
||||
*
|
||||
@@ -80,14 +64,12 @@ static inline u8 is_hex(char p)
|
||||
}
|
||||
|
||||
/**
|
||||
- * is_checksum_valid
|
||||
- *
|
||||
* Validate the checksum in the provided TlvInfo EEPROM data. First,
|
||||
* verify that the TlvInfo header is valid, then make sure the last
|
||||
* TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
|
||||
* and compare it to the value stored in the EEPROM CRC-32 TLV.
|
||||
*/
|
||||
-static bool is_checksum_valid(u8 *eeprom)
|
||||
+bool tlvinfo_check_crc(u8 *eeprom)
|
||||
{
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
struct tlvinfo_tlv *eeprom_crc;
|
||||
@@ -134,11 +116,11 @@ static int read_eeprom(int devnum, u8 *eeprom)
|
||||
|
||||
// If the contents are invalid, start over with default contents
|
||||
if (!is_valid_tlvinfo_header(eeprom_hdr) ||
|
||||
- !is_checksum_valid(eeprom)) {
|
||||
+ !tlvinfo_check_crc(eeprom)) {
|
||||
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
|
||||
eeprom_hdr->version = TLV_INFO_VERSION;
|
||||
eeprom_hdr->totallen = cpu_to_be16(0);
|
||||
- update_crc(eeprom);
|
||||
+ tlvinfo_update_crc(eeprom);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
@@ -180,7 +162,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
|
||||
tlv_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
|
||||
while (curr_tlv < tlv_end) {
|
||||
eeprom_tlv = to_entry(&eeprom[curr_tlv]);
|
||||
- if (!is_valid_tlv(eeprom_tlv)) {
|
||||
+ if (!is_valid_tlvinfo_entry(eeprom_tlv)) {
|
||||
printf("Invalid TLV field starting at EEPROM offset %d\n",
|
||||
curr_tlv);
|
||||
return;
|
||||
@@ -190,7 +172,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
|
||||
}
|
||||
|
||||
printf("Checksum is %s.\n",
|
||||
- is_checksum_valid(eeprom) ? "valid" : "invalid");
|
||||
+ tlvinfo_check_crc(eeprom) ? "valid" : "invalid");
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("EEPROM dump: (0x%x bytes)", TLV_INFO_MAX_LEN);
|
||||
@@ -337,13 +319,13 @@ static void decode_tlv(struct tlvinfo_tlv *tlv)
|
||||
}
|
||||
|
||||
/**
|
||||
- * update_crc
|
||||
+ * tlvinfo_update_crc
|
||||
*
|
||||
* This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
|
||||
* one is added. This function should be called after each update to the
|
||||
* EEPROM structure, to make sure the CRC is always correct.
|
||||
*/
|
||||
-static void update_crc(u8 *eeprom)
|
||||
+void tlvinfo_update_crc(u8 *eeprom)
|
||||
{
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
struct tlvinfo_tlv *eeprom_crc;
|
||||
@@ -373,20 +355,20 @@ static void update_crc(u8 *eeprom)
|
||||
}
|
||||
|
||||
/**
|
||||
- * prog_eeprom
|
||||
+ * write_tlvinfo_tlv_eeprom
|
||||
*
|
||||
- * Write the EEPROM data from CPU memory to the hardware.
|
||||
+ * Write the TLV data from CPU memory to the hardware.
|
||||
*/
|
||||
-static int prog_eeprom(int devnum, u8 *eeprom)
|
||||
+int write_tlvinfo_tlv_eeprom(void *eeprom, int dev)
|
||||
{
|
||||
int ret = 0;
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
int eeprom_len;
|
||||
|
||||
- update_crc(eeprom);
|
||||
+ tlvinfo_update_crc(eeprom);
|
||||
|
||||
eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
|
||||
- ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
|
||||
+ ret = write_tlv_eeprom(eeprom, eeprom_len, dev);
|
||||
if (ret) {
|
||||
printf("Programming failed.\n");
|
||||
return -1;
|
||||
@@ -459,13 +441,13 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
||||
if (argc == 2) {
|
||||
switch (cmd) {
|
||||
case 'w': /* write */
|
||||
- prog_eeprom(current_dev, eeprom);
|
||||
+ write_tlvinfo_tlv_eeprom(eeprom, current_dev);
|
||||
break;
|
||||
case 'e': /* erase */
|
||||
strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
|
||||
eeprom_hdr->version = TLV_INFO_VERSION;
|
||||
eeprom_hdr->totallen = cpu_to_be16(0);
|
||||
- update_crc(eeprom);
|
||||
+ tlvinfo_update_crc(eeprom);
|
||||
printf("EEPROM data in memory reset.\n");
|
||||
break;
|
||||
case 'l': /* list */
|
||||
@@ -546,7 +528,7 @@ U_BOOT_CMD(tlv_eeprom, 4, 1, do_tlv_eeprom,
|
||||
* An offset from the beginning of the EEPROM is returned in the
|
||||
* eeprom_index parameter if the TLV is found.
|
||||
*/
|
||||
-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
|
||||
+bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
|
||||
{
|
||||
struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
|
||||
struct tlvinfo_tlv *eeprom_tlv;
|
||||
@@ -558,7 +540,7 @@ static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
|
||||
eeprom_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
|
||||
while (*eeprom_index < eeprom_end) {
|
||||
eeprom_tlv = to_entry(&eeprom[*eeprom_index]);
|
||||
- if (!is_valid_tlv(eeprom_tlv))
|
||||
+ if (!is_valid_tlvinfo_entry(eeprom_tlv))
|
||||
return false;
|
||||
if (eeprom_tlv->type == tcode)
|
||||
return true;
|
||||
@@ -591,7 +573,7 @@ static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code)
|
||||
eeprom_hdr->totallen =
|
||||
cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) -
|
||||
tlength);
|
||||
- update_crc(eeprom);
|
||||
+ tlvinfo_update_crc(eeprom);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
@@ -692,7 +674,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval)
|
||||
// Update the total length and calculate (add) a new CRC-32 TLV
|
||||
eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) +
|
||||
ENT_SIZE + new_tlv_len);
|
||||
- update_crc(eeprom);
|
||||
+ tlvinfo_update_crc(eeprom);
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -983,7 +965,7 @@ int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
|
||||
be16_to_cpu(tlv_hdr->totallen), dev_num);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
- if (!is_checksum_valid(eeprom))
|
||||
+ if (!tlvinfo_check_crc(eeprom))
|
||||
return -EINVAL;
|
||||
|
||||
*hdr = tlv_hdr;
|
||||
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
|
||||
index aa96c9e8d4..eeb8af57f1 100644
|
||||
--- a/include/tlv_eeprom.h
|
||||
+++ b/include/tlv_eeprom.h
|
||||
@@ -111,6 +111,51 @@ int write_tlv_eeprom(void *eeprom, int len, int dev);
|
||||
int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
|
||||
struct tlvinfo_tlv **first_entry, int dev);
|
||||
|
||||
+/**
|
||||
+ * Write TLV data to the EEPROM.
|
||||
+ *
|
||||
+ * - Only writes length of actual tlv data
|
||||
+ * - updates checksum
|
||||
+ *
|
||||
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
|
||||
+ * of size at least TLV_INFO_MAX_LEN.
|
||||
+ * @dev : EEPROM device to write
|
||||
+ *
|
||||
+ */
|
||||
+int write_tlvinfo_tlv_eeprom(void *eeprom, int dev);
|
||||
+
|
||||
+/**
|
||||
+ * tlvinfo_find_tlv
|
||||
+ *
|
||||
+ * This function finds the TLV with the supplied code in the EERPOM.
|
||||
+ * An offset from the beginning of the EEPROM is returned in the
|
||||
+ * eeprom_index parameter if the TLV is found.
|
||||
+ */
|
||||
+bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
|
||||
+
|
||||
+/**
|
||||
+ * tlvinfo_update_crc
|
||||
+ *
|
||||
+ * This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
|
||||
+ * one is added. This function should be called after each update to the
|
||||
+ * EEPROM structure, to make sure the CRC is always correct.
|
||||
+ *
|
||||
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
|
||||
+ * of size at least TLV_INFO_MAX_LEN.
|
||||
+ */
|
||||
+void tlvinfo_update_crc(u8 *eeprom);
|
||||
+
|
||||
+/**
|
||||
+ * Validate the checksum in the provided TlvInfo EEPROM data. First,
|
||||
+ * verify that the TlvInfo header is valid, then make sure the last
|
||||
+ * TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
|
||||
+ * and compare it to the value stored in the EEPROM CRC-32 TLV.
|
||||
+ *
|
||||
+ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
|
||||
+ * of size at least TLV_INFO_MAX_LEN.
|
||||
+ */
|
||||
+bool tlvinfo_check_crc(u8 *eeprom);
|
||||
+
|
||||
#else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
|
||||
|
||||
static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
|
||||
@@ -150,4 +195,16 @@ static inline bool is_valid_tlvinfo_header(struct tlvinfo_header *hdr)
|
||||
(be16_to_cpu(hdr->totallen) <= TLV_TOTAL_LEN_MAX));
|
||||
}
|
||||
|
||||
+/**
|
||||
+ * is_valid_tlv
|
||||
+ *
|
||||
+ * Perform basic sanity checks on a TLV field. The TLV is pointed to
|
||||
+ * by the parameter provided.
|
||||
+ * 1. The type code is not reserved (0x00 or 0xFF)
|
||||
+ */
|
||||
+static inline bool is_valid_tlvinfo_entry(struct tlvinfo_tlv *tlv)
|
||||
+{
|
||||
+ return((tlv->type != 0x00) && (tlv->type != 0xFF));
|
||||
+}
|
||||
+
|
||||
#endif /* __TLV_EEPROM_H_ */
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
From 04ce313a110bae4262684666c245443182d6f0bc Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 20 Mar 2022 11:11:25 +0200
|
||||
Subject: [PATCH] cmd: tlv_eeprom: remove empty function implementations from
|
||||
header
|
||||
|
||||
tlv_eeprom exposed functions are independent from platforms, hence no
|
||||
stubs are required.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
include/tlv_eeprom.h | 24 ++----------------------
|
||||
1 file changed, 2 insertions(+), 22 deletions(-)
|
||||
|
||||
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
|
||||
index eeb8af57f1..201a2b44af 100644
|
||||
--- a/include/tlv_eeprom.h
|
||||
+++ b/include/tlv_eeprom.h
|
||||
@@ -65,7 +65,8 @@ struct __attribute__ ((__packed__)) tlvinfo_tlv {
|
||||
#define TLV_CODE_VENDOR_EXT 0xFD
|
||||
#define TLV_CODE_CRC_32 0xFE
|
||||
|
||||
-#if CONFIG_IS_ENABLED(CMD_TLV_EEPROM)
|
||||
+/* how many EEPROMs can be used */
|
||||
+#define TLV_MAX_DEVICES 2
|
||||
|
||||
/**
|
||||
* read_tlv_eeprom - Read the EEPROM binary data from the hardware
|
||||
@@ -156,27 +157,6 @@ void tlvinfo_update_crc(u8 *eeprom);
|
||||
*/
|
||||
bool tlvinfo_check_crc(u8 *eeprom);
|
||||
|
||||
-#else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
|
||||
-
|
||||
-static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
|
||||
-{
|
||||
- return -ENOTSUPP;
|
||||
-}
|
||||
-
|
||||
-static inline int write_tlv_eeprom(void *eeprom, int len)
|
||||
-{
|
||||
- return -ENOTSUPP;
|
||||
-}
|
||||
-
|
||||
-static inline int
|
||||
-read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
|
||||
- struct tlvinfo_tlv **first_entry, int dev)
|
||||
-{
|
||||
- return -ENOTSUPP;
|
||||
-}
|
||||
-
|
||||
-#endif /* CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
|
||||
-
|
||||
/**
|
||||
* is_valid_tlvinfo_header
|
||||
*
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,69 @@
|
|||
From 40355952340169930bfbd03a6ea4de3041c39754 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 20 Mar 2022 12:07:38 +0200
|
||||
Subject: [PATCH] lib: tlv_eeprom: add function for reading one entry into a C
|
||||
string
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
include/tlv_eeprom.h | 12 ++++++++++++
|
||||
lib/tlv/tlv_eeprom.c | 23 +++++++++++++++++++++++
|
||||
2 files changed, 35 insertions(+)
|
||||
|
||||
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
|
||||
index ee9f035c8c..c91618e480 100644
|
||||
--- a/include/tlv_eeprom.h
|
||||
+++ b/include/tlv_eeprom.h
|
||||
@@ -167,6 +167,18 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval);
|
||||
*/
|
||||
bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
|
||||
|
||||
+/**
|
||||
+ * Read the TLV entry with specified code to a buffer as terminated C string.
|
||||
+ * @eeprom: Pointer to buffer holding the TLV EEPROM binary data.
|
||||
+ * @code: The TLV Code of the entry to read.
|
||||
+ * @buffer: Pointer to buffer where the value will be stored. Must have capacity
|
||||
+ * for the string representation of the data including null terminator.
|
||||
+ * @length: size of the buffer where the value will be stored.
|
||||
+ *
|
||||
+ * Return length of string on success, -1 on error.
|
||||
+ */
|
||||
+ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length);
|
||||
+
|
||||
/**
|
||||
* tlvinfo_update_crc
|
||||
*
|
||||
diff --git a/lib/tlv/tlv_eeprom.c b/lib/tlv/tlv_eeprom.c
|
||||
index fe164cabe6..e2c7a0d664 100644
|
||||
--- a/lib/tlv/tlv_eeprom.c
|
||||
+++ b/lib/tlv/tlv_eeprom.c
|
||||
@@ -349,6 +349,29 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval)
|
||||
return true;
|
||||
}
|
||||
|
||||
+/**
|
||||
+ * Read the TLV entry with specified code to a buffer as terminated C string.
|
||||
+ */
|
||||
+ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length) {
|
||||
+ int index;
|
||||
+ struct tlvinfo_tlv *tlv;
|
||||
+
|
||||
+ // read sku from part-number field
|
||||
+ if(tlvinfo_find_tlv(eeprom, code, &index)) {
|
||||
+ tlv = (struct tlvinfo_tlv *) &eeprom[index];
|
||||
+ if(tlv->length > length) {
|
||||
+ pr_err("%s: tlv value (%d) larger than buffer (%zu)!\n", __func__, tlv->length+1, length);
|
||||
+ return -1;
|
||||
+ }
|
||||
+ memcpy(buffer, tlv->value, tlv->length);
|
||||
+ buffer[tlv->length] = 0;
|
||||
+
|
||||
+ return tlv->length;
|
||||
+ }
|
||||
+
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* set_mac
|
||||
*
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,111 @@
|
|||
From 79df8e99fb5cc4c0e2716b1051302f72df28ee04 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 13 Mar 2022 10:54:15 +0200
|
||||
Subject: [PATCH] add SoM and Carrier eeproms
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
arch/arm/dts/cn9130-cex7-A.dts | 11 ++++++-----
|
||||
arch/arm/dts/cn9130-cf-base.dts | 20 +++++++++++++++-----
|
||||
arch/arm/dts/cn9130-cf-pro.dts | 20 +++++++++++++++-----
|
||||
3 files changed, 36 insertions(+), 15 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/dts/cn9130-cex7-A.dts b/arch/arm/dts/cn9130-cex7-A.dts
|
||||
index 2db0fc802e..209e485822 100644
|
||||
--- a/arch/arm/dts/cn9130-cex7-A.dts
|
||||
+++ b/arch/arm/dts/cn9130-cex7-A.dts
|
||||
@@ -147,12 +147,13 @@
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
- eeprom0: eeprom@50 {
|
||||
- compatible = "atmel,24c64";
|
||||
- reg = <0x50>;
|
||||
- pagesize = <0x20>;
|
||||
- };
|
||||
|
||||
+ /* M24C0x-MWN */
|
||||
+ com_eeprom@50 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x50>;
|
||||
+ pagesize = <0x10>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
diff --git a/arch/arm/dts/cn9130-cf-base.dts b/arch/arm/dts/cn9130-cf-base.dts
|
||||
index a9d4a4491f..355c9d8ed0 100644
|
||||
--- a/arch/arm/dts/cn9130-cf-base.dts
|
||||
+++ b/arch/arm/dts/cn9130-cf-base.dts
|
||||
@@ -145,11 +145,7 @@
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
- eeprom0: eeprom@50 {
|
||||
- compatible = "atmel,24c64";
|
||||
- reg = <0x53>;
|
||||
- pagesize = <0x20>;
|
||||
- };
|
||||
+
|
||||
/*
|
||||
* PCA9655 GPIO expander, up to 1MHz clock.
|
||||
* 0-CON3 CLKREQ#
|
||||
@@ -225,6 +221,20 @@
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ /* 24AA025UID */
|
||||
+ carrier_eeprom@52 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x52>;
|
||||
+ pagesize = <8>;
|
||||
+ };
|
||||
+
|
||||
+ /* M24C02-WMN6TP */
|
||||
+ som_eeprom@53 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x53>;
|
||||
+ pagesize = <16>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
|
||||
index fb37dd833d..6931818cf6 100644
|
||||
--- a/arch/arm/dts/cn9130-cf-pro.dts
|
||||
+++ b/arch/arm/dts/cn9130-cf-pro.dts
|
||||
@@ -145,11 +145,7 @@
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
- eeprom0: eeprom@50 {
|
||||
- compatible = "atmel,24c64";
|
||||
- reg = <0x53>;
|
||||
- pagesize = <0x20>;
|
||||
- };
|
||||
+
|
||||
/*
|
||||
* PCA9655 GPIO expander, up to 1MHz clock.
|
||||
* 0-CON3 CLKREQ#
|
||||
@@ -231,6 +227,20 @@
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ /* 24AA025UID */
|
||||
+ carrier_eeprom@52 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x52>;
|
||||
+ pagesize = <8>;
|
||||
+ };
|
||||
+
|
||||
+ /* M24C02-WMN6TP */
|
||||
+ som_eeprom@53 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x53>;
|
||||
+ pagesize = <16>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
From a4fce9816a992f26044cef488b2617d7006535c2 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 13 Mar 2022 12:42:28 +0200
|
||||
Subject: [PATCH] find fdtfile from tlv eeprom
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
board/Marvell/octeontx2_cn913x/board.c | 97 ++++++++++++++++++++++++++
|
||||
configs/sr_cn913x_cex7_defconfig | 2 +
|
||||
2 files changed, 99 insertions(+)
|
||||
|
||||
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
|
||||
index 27db37e86e..1e900d2aab 100644
|
||||
--- a/board/Marvell/octeontx2_cn913x/board.c
|
||||
+++ b/board/Marvell/octeontx2_cn913x/board.c
|
||||
@@ -8,11 +8,13 @@
|
||||
#include <common.h>
|
||||
#include <console.h>
|
||||
#include <dm.h>
|
||||
+#include <env.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <power/regulator.h>
|
||||
+#include <tlv_eeprom.h>
|
||||
#ifdef CONFIG_BOARD_CONFIG_EEPROM
|
||||
#include <mvebu/cfg_eeprom.h>
|
||||
#endif
|
||||
@@ -121,8 +123,103 @@ static int init_bootcmd_console(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
+/*
|
||||
+ * Read TLV formatted data from eeprom.
|
||||
+ * Only read as much data as indicated by the TLV header.
|
||||
+ */
|
||||
+// TODO: this should be a library function?!
|
||||
+static bool get_tlvinfo_from_eeprom(int index, u8 *buffer, size_t length) {
|
||||
+ struct tlvinfo_header *eeprom_hdr = (struct tlvinfo_header *) buffer;
|
||||
+ struct tlvinfo_tlv *eeprom_tlv = (struct tlvinfo_tlv *) &buffer[sizeof(struct tlvinfo_header)];
|
||||
+
|
||||
+ if(length < TLV_INFO_HEADER_SIZE) {
|
||||
+ pr_err("%s: buffer too small for tlv header!\n", __func__);
|
||||
+ return false;
|
||||
+ }
|
||||
+ if(read_tlv_eeprom((void *)eeprom_hdr, 0, TLV_INFO_HEADER_SIZE, index) != 0) {
|
||||
+ pr_err("%s: failed to read from eeprom!\n", __func__);
|
||||
+ return false;
|
||||
+ }
|
||||
+ if(!is_valid_tlvinfo_header(eeprom_hdr)) {
|
||||
+ pr_warn("%s: invalid tlv header!\n", __func__);
|
||||
+ return false;
|
||||
+ }
|
||||
+ if(length - TLV_INFO_HEADER_SIZE < be16_to_cpu(eeprom_hdr->totallen)) {
|
||||
+ pr_err("%s: buffer too small for tlv data!\n", __func__);
|
||||
+ return false;
|
||||
+ }
|
||||
+ if(read_tlv_eeprom((void *)eeprom_tlv, sizeof(struct tlvinfo_header), be16_to_cpu(eeprom_hdr->totallen), index) != 0) {
|
||||
+ pr_err("%s: failed to read from eeprom!\n", __func__);
|
||||
+ return false;
|
||||
+ }
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
+static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
|
||||
+ char cpu[5] = {0};
|
||||
+ char carrier[8] = {0};
|
||||
+ static u8 eeprom[TLV_INFO_MAX_LEN];
|
||||
+ char sku[257];
|
||||
+
|
||||
+ for(int i = 0; i < 2;i++) {
|
||||
+ // read eeprom
|
||||
+ if(!get_tlvinfo_from_eeprom(i, eeprom, sizeof(eeprom))) {
|
||||
+ pr_info("%s: failed to read eeprom %d\n", __func__, i);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ // read sku
|
||||
+ if(!tlvinfo_read_tlv(eeprom, TLV_CODE_PART_NUMBER, sku, sizeof(sku))) {
|
||||
+ pr_warn("%s: could not find sku in eeprom\n", __func__);
|
||||
+ continue;
|
||||
+ }
|
||||
+ pr_debug("%s: read sku %s\n", __func__, sku);
|
||||
+
|
||||
+ // parse sku - processor or carrier indicated at index 2-6
|
||||
+ if(memcmp(&sku[2], "CFCB", 4) == 0) {
|
||||
+ // Clearfog Base
|
||||
+ strcpy(carrier, "cf-base");
|
||||
+ } else if(memcmp(&sku[2], "CFCP", 4) == 0) {
|
||||
+ // Clearfog Pro
|
||||
+ strcpy(carrier, "cf-pro");
|
||||
+ } else if(memcmp(&sku[2], "C", 1) == 0) {
|
||||
+ // COM-Express 7 - C9130 / C9131 / C9132 ...
|
||||
+ memcpy(cpu, &sku[3], 4);
|
||||
+ strcpy(carrier, "cex7");
|
||||
+ } else if(memcmp(&sku[2], "S9130", 4) == 0) {
|
||||
+ // SoM - S9130 / S9131 / S9132 ...
|
||||
+ memcpy(cpu, &sku[3], 4);
|
||||
+ } else {
|
||||
+ pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if(!cpu[0]) {
|
||||
+ pr_err("%s: could not identify SoC, defaulting to %s!\n", __func__, "CN9130");
|
||||
+ strcpy(cpu, "9130");
|
||||
+ }
|
||||
+
|
||||
+ if(!carrier[0]) {
|
||||
+ pr_err("%s: could not identify carrier, defaulting to %s!\n", __func__, "Clearfog Pro");
|
||||
+ strcpy(carrier, "cf-pro");
|
||||
+ }
|
||||
+
|
||||
+ // assemble fdtfile
|
||||
+ if(snprintf(buffer, length, "marvell/cn%s-%s.dtb", cpu, carrier) >= length) {
|
||||
+ pr_err("%s: fdtfile buffer too small, result truncated!\n", __func__);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int board_late_init(void)
|
||||
{
|
||||
+ char fdtfile[32] = {0};
|
||||
+
|
||||
+ // identify device
|
||||
+ get_fdtfile_from_tlv_eeprom(fdtfile, sizeof(fdtfile));
|
||||
+ if (!env_get("fdtfile"))
|
||||
+ env_set("fdtfile", fdtfile);
|
||||
+
|
||||
#if CONFIG_IS_ENABLED(OCTEONTX_SERIAL_BOOTCMD)
|
||||
if (init_bootcmd_console())
|
||||
printf("Failed to init bootcmd input\n");
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index 307cefef65..f971d9d4d0 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -102,3 +102,5 @@ CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
|
||||
+CONFIG_I2C_EEPROM=y
|
||||
+CONFIG_CMD_TLV_EEPROM=y
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
From 6516e51970deea70b79ebff44ad704b2be08e3fb Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Sun, 20 Mar 2022 15:02:03 +0200
|
||||
Subject: [PATCH] octeontx2_cn913x: support distro-boot
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
configs/sr_cn913x_cex7_defconfig | 1 -
|
||||
include/configs/octeontx2_cn913x.h | 12 ++++++++++++
|
||||
2 files changed, 12 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index f971d9d4d0..30e51c0026 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -11,7 +11,6 @@ CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
-CONFIG_BOOTCOMMAND="run get_images; run set_bootargs; booti $kernel_addr $ramfs_addr $fdt_addr"
|
||||
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
|
||||
index 2ae70e5efe..aa966bd292 100644
|
||||
--- a/include/configs/octeontx2_cn913x.h
|
||||
+++ b/include/configs/octeontx2_cn913x.h
|
||||
@@ -35,6 +35,18 @@
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
+#include <config_distro_bootcmd.h>
|
||||
+
|
||||
+#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
+ "console=" CONFIG_DEFAULT_CONSOLE "\0"\
|
||||
+ "kernel_addr_r=0x7000000\0" \
|
||||
+ "fdt_addr_r=0x6f00000\0" \
|
||||
+ "ramdisk_addr_r=0x9000000\0" \
|
||||
+ "scriptaddr=0x6e00000\0" \
|
||||
+ "pxefile_addr_r=0x6000000\0" \
|
||||
+ BOOTENV
|
||||
+
|
||||
/* RTC configuration */
|
||||
#ifdef CONFIG_MARVELL_RTC
|
||||
#define ERRATA_FE_3124064
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 03297ee2679e39da71dd39fb3076b305621c45d5 Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Tue, 22 Mar 2022 11:09:06 +0200
|
||||
Subject: [PATCH] octeontx2_cn913x: remove console variable
|
||||
|
||||
console is now properly selected by chosen nodei n device-tree rather
|
||||
than through bootargs.
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
include/configs/octeontx2_cn913x.h | 4 ----
|
||||
1 file changed, 4 deletions(-)
|
||||
|
||||
diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
|
||||
index aa966bd292..d01644fcb5 100644
|
||||
--- a/include/configs/octeontx2_cn913x.h
|
||||
+++ b/include/configs/octeontx2_cn913x.h
|
||||
@@ -8,9 +8,6 @@
|
||||
#ifndef _CONFIG_OCTEONTX2_CN913X_H
|
||||
#define _CONFIG_OCTEONTX2_CN913X_H
|
||||
|
||||
-#define CONFIG_DEFAULT_CONSOLE "console=ttyS0,115200 "\
|
||||
- "earlycon=uart8250,mmio32,0xf0512000"
|
||||
-
|
||||
#include <configs/mvebu_armada-common.h>
|
||||
|
||||
/*
|
||||
@@ -39,7 +36,6 @@
|
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
- "console=" CONFIG_DEFAULT_CONSOLE "\0"\
|
||||
"kernel_addr_r=0x7000000\0" \
|
||||
"fdt_addr_r=0x6f00000\0" \
|
||||
"ramdisk_addr_r=0x9000000\0" \
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
From 11a0fbc3e0ab35fbb5620e59fa65b201df26eabd Mon Sep 17 00:00:00 2001
|
||||
From: Josua Mayer <josua@solid-run.com>
|
||||
Date: Tue, 22 Mar 2022 11:12:12 +0200
|
||||
Subject: [PATCH] octeontx2_cn913x: enable mmc partconf command
|
||||
|
||||
Signed-off-by: Josua Mayer <josua@solid-run.com>
|
||||
---
|
||||
configs/sr_cn913x_cex7_defconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index 30e51c0026..24219ef45d 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -103,3 +103,4 @@ CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_CMD_TLV_EEPROM=y
|
||||
+CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
|
|
@ -0,0 +1,783 @@
|
|||
From c6279eb32f1d4f295c8f0335f4586ff92d3e4439 Mon Sep 17 00:00:00 2001
|
||||
From: Alon Rotman <alon.rotman@solid-run.com>
|
||||
Date: Thu, 7 Jul 2022 21:58:29 +0300
|
||||
Subject: [PATCH] uboot: add support cn9131-cf-solidwan
|
||||
|
||||
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
|
||||
---
|
||||
arch/arm/dts/Makefile | 7 +-
|
||||
arch/arm/dts/armada-cp110.dtsi | 14 +
|
||||
arch/arm/dts/cn9130-cf-solidwan.dts | 382 +++++++++++++++++++++++++
|
||||
arch/arm/dts/cn9130-som.dtsi | 9 +
|
||||
arch/arm/dts/cn9131-cf-solidwan.dts | 50 ++++
|
||||
arch/arm/dts/cn9131-cf-solidwan.dtsi | 214 ++++++++++++++
|
||||
board/Marvell/octeontx2_cn913x/board.c | 8 +-
|
||||
configs/sr_cn913x_cex7_defconfig | 1 +
|
||||
8 files changed, 683 insertions(+), 2 deletions(-)
|
||||
create mode 100644 arch/arm/dts/cn9130-cf-solidwan.dts
|
||||
create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dts
|
||||
create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dtsi
|
||||
|
||||
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
||||
index 246bd4665e..db8f42d94d 100644
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -242,7 +242,12 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
|
||||
cn9132-db-C.dtb \
|
||||
cn9132-cex7-A.dtb \
|
||||
cn9130-cf-pro.dtb \
|
||||
- cn9130-cf-base.dtb
|
||||
+ cn9130-cf-base.dtb \
|
||||
+ cn9130-bldn-mbv.dtb \
|
||||
+ cn9131-bldn-mbv.dtb \
|
||||
+ cn9130-cf-solidwan.dtb \
|
||||
+ cn9131-cf-solidwan.dtb
|
||||
+
|
||||
|
||||
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
|
||||
uniphier-ld11-global.dtb \
|
||||
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
|
||||
index af55c5573d..6abe8f0bea 100644
|
||||
--- a/arch/arm/dts/armada-cp110.dtsi
|
||||
+++ b/arch/arm/dts/armada-cp110.dtsi
|
||||
@@ -31,6 +31,11 @@
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
|
||||
|
||||
+
|
||||
+/* CP110_LABEL(ser1): ser@15
|
||||
+
|
||||
+*/
|
||||
+
|
||||
CP110_LABEL(mdio): mdio@12a200 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@@ -39,6 +44,15 @@
|
||||
mdio-name = CP110_STRING_LABEL(mdio);
|
||||
status = "disabled";
|
||||
};
|
||||
+ CP110_LABEL(mdio2): mdio@12a400 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ compatible = "marvell,orion-mdio";
|
||||
+ reg = <0x12a200 0x10>;
|
||||
+ mdio-name = CP110_STRING_LABEL(mdio);
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
|
||||
CP110_LABEL(xmdio): mdio@12a600 {
|
||||
#address-cells = <1>;
|
||||
diff --git a/arch/arm/dts/cn9130-cf-solidwan.dts b/arch/arm/dts/cn9130-cf-solidwan.dts
|
||||
new file mode 100644
|
||||
index 0000000000..c26bb15af9
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9130-cf-solidwan.dts
|
||||
@@ -0,0 +1,382 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2020 SolidRun ltd.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0
|
||||
+ * https://spdx.org/licenses
|
||||
+ */
|
||||
+
|
||||
+/* cn9130-cex7-A.dts */
|
||||
+#include "cn9130-som.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "SolidRun CN9130 based SOM ClearFog SolidWAN ";
|
||||
+ compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
+ "marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
+ "marvell,armada-ap806", "marvell,armada70x0";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ aliases {
|
||||
+ i2c0 = &cp0_i2c0;
|
||||
+ i2c1 = &cp0_i2c1;
|
||||
+ spi0 = &cp0_spi1;
|
||||
+ gpio0 = &ap_gpio0;
|
||||
+ gpio1 = &cp0_gpio0;
|
||||
+ gpio2 = &cp0_gpio1;
|
||||
+ };
|
||||
+
|
||||
+ memory@00000000 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x80000000>;
|
||||
+ };
|
||||
+
|
||||
+ cp0 {
|
||||
+ config-space {
|
||||
+ sdhci@780000 {
|
||||
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
+ vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
+ };
|
||||
+ ap_reg_mmc_vccq: ap_mmc_vccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "ap_mmc_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ };
|
||||
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp_sd_vcc";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "cp0_sd_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
+ enable-active-high;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ };
|
||||
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci1-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ gpio@440100 {
|
||||
+ p24 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <24 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "switch_reset";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/***** AP related configuration *****/
|
||||
+&ap_pinctl {
|
||||
+ /* MPP Bus:
|
||||
+ * SDIO [0-10, 12]
|
||||
+ * UART0 [11,19]
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
|
||||
+ 1 3 1 0 0 0 0 0 0 3 >;
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/* on-board eMMC */
|
||||
+&ap_sdhci0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
|
||||
+ vqmmc-supply = <&ap_reg_mmc_vccq>;
|
||||
+ bus-width = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+/*
|
||||
+&cp0_uart1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_uart1_pins>;
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+};
|
||||
+*/
|
||||
+
|
||||
+/****** CP related configuration ******/
|
||||
+
|
||||
+&cp0_pinctl {
|
||||
+ /* MPP Bus:
|
||||
+ * [0-1] SMI MDC/MDIO
|
||||
+ * [2-3] UART1 TX/RX
|
||||
+ * [4-5] UART1 RTS/CTS
|
||||
+ * [6-8] PTP
|
||||
+ * [10-11] GPIO - SPD Strap
|
||||
+ * [12-16] SPI1
|
||||
+ * [17-26] GPIO - Boot straps
|
||||
+ * [27-34] GPIO
|
||||
+ * [35-36] I2C1
|
||||
+ * [37-38] I2C1
|
||||
+ * [39] GPIO
|
||||
+ * [40] RCVR CLK
|
||||
+ * [41] GPIO VHV_EN
|
||||
+ * [43] SD CARD DT
|
||||
+ * [44-55] RGMII --> GPIOs
|
||||
+ * [56-61] SDIO
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 10 10 8 8 6 6 0 0 0 0
|
||||
+ 0 0 3 3 3 3 3 0 0 0
|
||||
+ 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 2 2 2 2 0
|
||||
+ 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 0 0xe 0xe 0xe 0xe
|
||||
+ 0xe 0xe 0 >;
|
||||
+};
|
||||
+
|
||||
+&cp0_i2c0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <100000>;
|
||||
+ eeprom0: eeprom@53 {
|
||||
+ compatible = "atmel,24c64";
|
||||
+ reg = <0x53>;
|
||||
+ pagesize = <0x20>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_i2c1 {
|
||||
+ /* connected to SFP0*/
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
+ clock-frequency = <100000>;
|
||||
+};
|
||||
+
|
||||
+/* SD CARD */
|
||||
+&cp0_sdhci0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_sdhci_pins
|
||||
+ &cp0_sdhci_cd_pins>;
|
||||
+ bus-width = <4>;
|
||||
+ status = "okay";
|
||||
+ no-1-8-v;
|
||||
+};
|
||||
+
|
||||
+/* SPI NOR */
|
||||
+&cp0_spi1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_spi1_pins
|
||||
+ &cp0_spi1_cs1_pins>;
|
||||
+ reg = <0x700680 0x50>, /* control */
|
||||
+ <0x2000000 0x1000000>, /* CS0 */
|
||||
+ <0x2000000 0x1000004>, /* CS1 */
|
||||
+ <0 0xffffffff>, /* CS2 */
|
||||
+ <0 0xffffffff>; /* CS3 */
|
||||
+ status = "okay";
|
||||
+
|
||||
+ spi-flash@0 {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ compatible = "jedec,spi-nor", "spi-flash";
|
||||
+ reg = <0x0>;
|
||||
+ /* On-board MUX does not allow higher frequencies */
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ };
|
||||
+ spi-flash@1 {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0x1>;
|
||||
+ /* On carrier MUX does not allow higher frequencies */
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cp0_comphy {
|
||||
+ phy0 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX0>;
|
||||
+ };
|
||||
+
|
||||
+ phy1 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII2>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+ };
|
||||
+
|
||||
+ phy2 {
|
||||
+ phy-type = <COMPHY_TYPE_SFI0>;
|
||||
+ phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
+ };
|
||||
+
|
||||
+ phy3 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII1>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+ };
|
||||
+
|
||||
+ phy4 {
|
||||
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
|
||||
+ };
|
||||
+
|
||||
+ phy5 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX2>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_ethernet {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #0 - PCIe X1 Gen3 M.2 Slot */
|
||||
+&cp0_pcie0 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+// pinctrl-0 = <&cp0_pci0_reset_pins>;
|
||||
+// marvell,reset-gpio = <&cp0_gpio0 6 GPIO_ACTIVE_LOW>; //MPP6
|
||||
+};
|
||||
+
|
||||
+/* SRDS #1 - 1GbE SGMII */
|
||||
+&cp0_eth2 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sgmii";
|
||||
+ phy = <&cp0_phy1>;
|
||||
+ // phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/* SRDS #2 - 10GE SFP+ */
|
||||
+&cp0_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sfi";
|
||||
+ compatible = "sff,sfp";
|
||||
+ i2c-bus = <&cp0_i2c1>;
|
||||
+ los-gpio = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
|
||||
+ mod-def0-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; //MPP32
|
||||
+ tx-disable-gpio = <&cp0_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
|
||||
+ tx-fault-gpio = <&cp0_gpio0 31 GPIO_ACTIVE_HIGH>; //MPP31
|
||||
+ maximum-power-milliwatt = <2000>;
|
||||
+};
|
||||
+
|
||||
+/* SRDS #3 - 1GE PHY over SGMII */
|
||||
+&cp0_eth1 {
|
||||
+ status = "okay";
|
||||
+ phy = <&cp0_phy0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
|
||||
+};
|
||||
+
|
||||
+/* SRDS #4 - USB 3.0 host on M.2 connector */
|
||||
+&cp0_usb3_1 {
|
||||
+ status = "okay";
|
||||
+ vbus-supply = <&cp0_reg_usb3_vbus1>;
|
||||
+};
|
||||
+&cp0_utmi0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&cp0_utmi1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+/*
|
||||
+&cp0_usb3_0 {
|
||||
+ status = "okay";
|
||||
+ vbus-supply = <&cp0_reg_usb3_vbus0>;
|
||||
+};
|
||||
+*/
|
||||
+
|
||||
+/* SRDS #5 - mini PCIE slot */
|
||||
+&cp0_pcie2 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+// pinctrl-0 = <&cp0_pci2_reset_pins>;
|
||||
+// marvell,reset-gpio = <&cp0_gpio0 8 GPIO_ACTIVE_LOW>; //MPP6
|
||||
+};
|
||||
+
|
||||
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
|
||||
+&cp0_mdio {
|
||||
+ status = "okay";
|
||||
+ pinctrl-0 = <&cp0_mdio_pins>;
|
||||
+ cp0_phy0: ethernet-phy@0 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+ cp0_phy1: ethernet-phy@1 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_pinctl {
|
||||
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
|
||||
+ bank-name ="cp0-110";
|
||||
+
|
||||
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
+ marvell,pins = < 37 38 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
+ marvell,pins = < 35 36 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
+ marvell,pins = < 56 57 58 59 60 61 >;
|
||||
+ marvell,function = <14>;
|
||||
+ };
|
||||
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
|
||||
+ marvell,pins = < 43 >;
|
||||
+ marvell,function = <1>;
|
||||
+ };
|
||||
+ cp0_spi1_pins: cp0-spi-pins-0 {
|
||||
+ marvell,pins = < 13 14 15 16 >;
|
||||
+ marvell,function = <3>;
|
||||
+ };
|
||||
+ cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
|
||||
+ marvell,pins = < 12 >;
|
||||
+ marvell,function = <3>;
|
||||
+ };
|
||||
+ cp0_mdio_pins: cp0-mdio-pins {
|
||||
+ marvell,pins = < 0 1 >;
|
||||
+ marvell,function = <10>;
|
||||
+ };
|
||||
+ cp0_pci0_reset_pins: pci0-reset-pins {
|
||||
+ marvell,pins = < 6 >;
|
||||
+ marvell,function = <0>;
|
||||
+ };
|
||||
+ cp0_pci2_reset_pins: pci2-reset-pins {
|
||||
+ marvell,pins = < 8 >;
|
||||
+ marvell,function = <0>;
|
||||
+ };
|
||||
+ cp0_uart1_pins: cp0-uart1-pins {
|
||||
+ marvell,pins = < 2 3 >;
|
||||
+ marvell,function = <8>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/cn9130-som.dtsi b/arch/arm/dts/cn9130-som.dtsi
|
||||
index 683821e0ea..ca69cd3ba0 100644
|
||||
--- a/arch/arm/dts/cn9130-som.dtsi
|
||||
+++ b/arch/arm/dts/cn9130-som.dtsi
|
||||
@@ -12,6 +12,15 @@
|
||||
#include "armada-ap807.dtsi"
|
||||
#include "armada-ap80x-quad.dtsi"
|
||||
|
||||
+
|
||||
+#undef CP110_NAME
|
||||
+#undef CP110_NUM
|
||||
+#undef CP110_PCIE_MEM_SIZE
|
||||
+#undef CP110_PCIEx_CPU_MEM_BASE
|
||||
+#undef CP110_PCIEx_BUS_MEM_BASE
|
||||
+
|
||||
+
|
||||
+
|
||||
/* This defines used to calculate the base address of each CP */
|
||||
#define CP110_BASE_OFFSET (0xf2000000)
|
||||
#define CP110_SPACE_SIZE (0x02000000)
|
||||
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dts b/arch/arm/dts/cn9131-cf-solidwan.dts
|
||||
new file mode 100644
|
||||
index 0000000000..95c3aec3c5
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9131-cf-solidwan.dts
|
||||
@@ -0,0 +1,50 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2020 SolidRun ltd.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0
|
||||
+ * https://spdx.org/licenses
|
||||
+ */
|
||||
+
|
||||
+/* cn9131-cex7-A */
|
||||
+
|
||||
+#include "cn9130-cf-solidwan.dts"
|
||||
+#include "cn9131-cf-solidwan.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Belden CN9131 based Platform";
|
||||
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
|
||||
+ "marvell,armada-ap806";
|
||||
+};
|
||||
+
|
||||
+&cp1_comphy {
|
||||
+ /* Serdes Configuration:
|
||||
+ * Lane 0: PCIe
|
||||
+ * Lane 1: SATA
|
||||
+ * Lane 2: USB3
|
||||
+ * Lane 3: SGMII
|
||||
+ * Lane 4: XFI
|
||||
+ * Lane 5: SGMII
|
||||
+ */
|
||||
+ phy0 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX0>;
|
||||
+ };
|
||||
+ phy1 {
|
||||
+ phy-type = <COMPHY_TYPE_SATA0>;
|
||||
+ };
|
||||
+ phy2 {
|
||||
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
|
||||
+ };
|
||||
+ phy3 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII1>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+ };
|
||||
+ phy4 {
|
||||
+ phy-type = <COMPHY_TYPE_SFI0>;
|
||||
+ phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
+ };
|
||||
+ phy5 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII2>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/cn9131-cf-solidwan.dtsi b/arch/arm/dts/cn9131-cf-solidwan.dtsi
|
||||
new file mode 100644
|
||||
index 0000000000..5f2ee49850
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9131-cf-solidwan.dtsi
|
||||
@@ -0,0 +1,214 @@
|
||||
+/*
|
||||
+* Copyright (C) 2020 SolidRun ltd.
|
||||
+*
|
||||
+* SPDX-License-Identifier: GPL-2.0
|
||||
+* https://spdx.org/licenses
|
||||
+*/
|
||||
+
|
||||
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1 */
|
||||
+
|
||||
+#undef CP110_NAME
|
||||
+#undef CP110_NUM
|
||||
+#undef CP110_PCIE_MEM_SIZE
|
||||
+#undef CP110_PCIEx_CPU_MEM_BASE
|
||||
+#undef CP110_PCIEx_BUS_MEM_BASE
|
||||
+
|
||||
+/* CP110-1 Settings */
|
||||
+#define CP110_NAME cp1
|
||||
+#define CP110_NUM 1
|
||||
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
|
||||
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
|
||||
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
|
||||
+
|
||||
+#include "armada-cp110.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "SolidRun CN9131 based SolidWan";
|
||||
+ compatible = "marvell,cn9131-db";
|
||||
+
|
||||
+ aliases {
|
||||
+ gpio3 = &cp1_gpio0;
|
||||
+ gpio4 = &cp1_gpio1;
|
||||
+ fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
|
||||
+ fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
|
||||
+ };
|
||||
+
|
||||
+ cp1 {
|
||||
+ config-space {
|
||||
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ pinctrl-names = "default";
|
||||
+// pinctrl-0 = <&cp1_xhci0_vbus_pins>;
|
||||
+ regulator-name = "cp1-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ pinctrl-names = "default";
|
||||
+// pinctrl-0 = <&cp1_xhci0_vbus_pins>;
|
||||
+ regulator-name = "cp1-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-min-microamp = <900000>;
|
||||
+ regulator-max-microamp = <900000>;
|
||||
+ regulator-force-boot-off;
|
||||
+// gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+&cp1_ld_efuse0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_ld_efuse1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_i2c1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp1_i2c1_pins>;
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <100000>;
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&cp1_utmi0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&cp1_utmi1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+/*
|
||||
+&cp1_usb3_1 {
|
||||
+ status = "okay";
|
||||
+ vbus-supply = <&cp1_reg_usb3_vbus1>;
|
||||
+};
|
||||
+*/
|
||||
+&cp1_pcie0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+ num-lanes = <1>;
|
||||
+ /* non-prefetchable memory */
|
||||
+ ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
|
||||
+// pinctrl-names = "default";
|
||||
+// marvell,reset-gpio = <&cp1_gpio0 29 GPIO_ACTIVE_LOW>;
|
||||
+};
|
||||
+
|
||||
+&cp1_pinctl {
|
||||
+ compatible = "marvell,mvebu-pinctrl",
|
||||
+ "marvell,cp115-standalone-pinctrl";
|
||||
+ bank-name ="cp1-110";
|
||||
+
|
||||
+ /* MPP Bus:
|
||||
+ * [1:0] UART0
|
||||
+ * [29:2] NC
|
||||
+ * [30:29] GPIO - M.2 Power off
|
||||
+ * [32:31] NC
|
||||
+ * [34:33] SFP GPIOs
|
||||
+ * [36:35] I2C
|
||||
+ * [38:37] SMI
|
||||
+ * [41:40] UART1
|
||||
+ * [48:42] NC
|
||||
+ * [50:49] SFP GPIOs
|
||||
+ * [62:51] NC
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x2 0x2 0x7 0x7 0x0
|
||||
+ 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 >;
|
||||
+
|
||||
+ cp1_uart0_pins: cp1-uart0-pins-1 {
|
||||
+ marvell,pins = < 0 1 >;
|
||||
+ marvell,function = <8>;
|
||||
+ };
|
||||
+ cp1_uart1_pins: cp1-uart1-pins-1 {
|
||||
+ marvell,pins = < 40 41 >;
|
||||
+ marvell,function = <7>;
|
||||
+ };
|
||||
+
|
||||
+ cp1_i2c1_pins: cp1-i2c-pins-1 {
|
||||
+ marvell,pins = < 35 36 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+
|
||||
+ cp1_mdio_pins: cp1-mdio-pins {
|
||||
+ marvell,pins = < 37 38 >;
|
||||
+ marvell,function = <7>;
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cp1_mdio2 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-0 = <&cp1_mdio_pins>;
|
||||
+ cp1_phy0: ethernet-phy@0 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+ cp1_phy1: ethernet-phy@1 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* SATA0 */
|
||||
+&cp1_sata0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp1_ethernet {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp1_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sfi";
|
||||
+ compatible = "sff,sfp";
|
||||
+ i2c-bus = <&cp1_i2c1>;
|
||||
+ los-gpio = <&cp1_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
|
||||
+ mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
|
||||
+ tx-disable-gpio = <&cp1_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
|
||||
+ tx-fault-gpio = <&cp1_gpio1 17 GPIO_ACTIVE_HIGH>; //MPP49
|
||||
+ maximum-power-milliwatt = <2000>;
|
||||
+};
|
||||
+
|
||||
+/* SERDES 3 SGMII */
|
||||
+&cp1_eth1 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sgmii";
|
||||
+ phy = <&cp1_phy0>;
|
||||
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
|
||||
+};
|
||||
+
|
||||
+/* SERDES 5 SGMII */
|
||||
+&cp1_eth2 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sgmii";
|
||||
+ phy = <&cp1_phy1>;
|
||||
+// phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
|
||||
+};
|
||||
+
|
||||
+/* M.2 LTE USB */
|
||||
+&cp1_usb3_0 {
|
||||
+ status = "okay";
|
||||
+ vbus-supply = <&cp1_reg_usb3_vbus0>;
|
||||
+};
|
||||
+
|
||||
+
|
||||
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
|
||||
index 1e900d2aab..cfd8d5f5fd 100644
|
||||
--- a/board/Marvell/octeontx2_cn913x/board.c
|
||||
+++ b/board/Marvell/octeontx2_cn913x/board.c
|
||||
@@ -188,8 +188,14 @@ static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
|
||||
memcpy(cpu, &sku[3], 4);
|
||||
strcpy(carrier, "cex7");
|
||||
} else if(memcmp(&sku[2], "S9130", 4) == 0) {
|
||||
- // SoM - S9130 / S9131 / S9132 ...
|
||||
+ // SoM - S9130
|
||||
memcpy(cpu, &sku[3], 4);
|
||||
+ } else if(memcmp(&sku[2], "CFSW", 4) == 0) {
|
||||
+ // SolidWan SOM S9131
|
||||
+ strcpy(carrier, "cf-swn");
|
||||
+ } else if(memcmp(&sku[2], "MBV", 3) == 0) {
|
||||
+ //BLDN MBV S9131
|
||||
+ strcpy(carrier, "bldn-mbv");
|
||||
} else {
|
||||
pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
|
||||
}
|
||||
diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
|
||||
index 24219ef45d..d7445e9476 100644
|
||||
--- a/configs/sr_cn913x_cex7_defconfig
|
||||
+++ b/configs/sr_cn913x_cex7_defconfig
|
||||
@@ -104,3 +104,4 @@ CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_CMD_TLV_EEPROM=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
|
|
@ -0,0 +1,779 @@
|
|||
From 70b50e2ac9671cbda2e9efd7ebef37eec66b8332 Mon Sep 17 00:00:00 2001
|
||||
From: Alon Rotman <alon.rotman@solid-run.com>
|
||||
Date: Thu, 7 Jul 2022 21:59:29 +0300
|
||||
Subject: [PATCH] uboot: add support bldn-mbv
|
||||
|
||||
Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
|
||||
---
|
||||
arch/arm/dts/cn9130-bldn-mbv.dts | 477 ++++++++++++++++++++++++++++++
|
||||
arch/arm/dts/cn9131-bldn-mbv.dts | 46 +++
|
||||
arch/arm/dts/cn9131-bldn-mbv.dtsi | 223 ++++++++++++++
|
||||
3 files changed, 746 insertions(+)
|
||||
create mode 100644 arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dtsi
|
||||
|
||||
diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
new file mode 100644
|
||||
index 0000000000..9e10eab008
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9130-bldn-mbv.dts
|
||||
@@ -0,0 +1,477 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2020 SolidRun ltd.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0
|
||||
+ * https://spdx.org/licenses
|
||||
+ */
|
||||
+
|
||||
+/* cn9130-som.dts */
|
||||
+#include "cn9130-som.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Belden CN9130 based SOM and Carrier MBV-A/B";
|
||||
+ compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
|
||||
+ "marvell,cn9030", "marvell,armada-ap806-quad",
|
||||
+ "marvell,armada-ap806", "marvell,armada70x0";
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ aliases {
|
||||
+ i2c0 = &cp0_i2c0;
|
||||
+ i2c1 = &cp0_i2c1;
|
||||
+ spi0 = &cp0_spi1;
|
||||
+ gpio0 = &ap_gpio0;
|
||||
+ gpio1 = &cp0_gpio0;
|
||||
+ gpio2 = &cp0_gpio1;
|
||||
+ };
|
||||
+
|
||||
+ memory@00000000 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x0 0x0 0x0 0x80000000>;
|
||||
+ };
|
||||
+
|
||||
+ cp0 {
|
||||
+ config-space {
|
||||
+ sdhci@780000 {
|
||||
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
|
||||
+ vmmc-supply = <&cp0_reg_sd_vcc>;
|
||||
+ };
|
||||
+ ap_reg_mmc_vccq: ap_mmc_vccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "ap_mmc_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ };
|
||||
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp_sd_vcc";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "cp0_sd_vccq";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
+ enable-active-high;
|
||||
+ states = <1800000 0x1
|
||||
+ 3300000 0x0>;
|
||||
+ };
|
||||
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "cp0-xhci1-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ gpio@440100 {
|
||||
+ p24 {
|
||||
+ gpio-hog;
|
||||
+ gpios = <24 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "switch_reset";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/***** AP related configuration *****/
|
||||
+&ap_pinctl {
|
||||
+ /* MPP Bus:
|
||||
+ * SDIO [0-10, 12]
|
||||
+ * UART0 [11,19]
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
|
||||
+ 1 3 1 0 0 0 0 0 0 3 >;
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/* on-board eMMC */
|
||||
+&ap_sdhci0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
|
||||
+ vqmmc-supply = <&ap_reg_mmc_vccq>;
|
||||
+ bus-width = <8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+/*
|
||||
+&cp0_uart1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_uart1_pins>;
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+};
|
||||
+*/
|
||||
+
|
||||
+/****** CP related configuration ******/
|
||||
+
|
||||
+&cp0_pinctl {
|
||||
+ /* MPP Bus:
|
||||
+ * [0-1] SMI MDC/MDIO
|
||||
+ * [2-3] UART1 TX/RX
|
||||
+ * [4-5] UART1 RTS/CTS - NC on carrier board
|
||||
+ * [6-8] PTP
|
||||
+ * [10-11] SPD Strap - GPIO
|
||||
+ * [12-16] SPI1
|
||||
+ * [17-26] Boot straps - GPIO
|
||||
+ * [35-36] I2C1
|
||||
+ * [37-38] I2C0
|
||||
+ * [40] RCVR CLK - NC
|
||||
+ * [41] VHV_EN - GPIO
|
||||
+ * [43] SD CARD DT
|
||||
+ * [44-55] RGMII
|
||||
+ * [56-61] SDIO
|
||||
+
|
||||
+ ***** GPIOs connected to CPLD******
|
||||
+ * [28] RESET_VSC8504_PHY
|
||||
+ * [31] CPLD_RESET_VSC8254_PHY
|
||||
+ * [32] INT_RELEASE
|
||||
+ * [33] CPLD_STATUS_INT
|
||||
+ * [34] CPLD_PWR_INT
|
||||
+ * [39] RESET_EMMC
|
||||
+ * [42] CPLD_DONE
|
||||
+ * [43] CPLD_PROG_N
|
||||
+
|
||||
+
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 0xa 0xa 8 8 6 6 9 9 9 0
|
||||
+ 0 0 3 3 3 3 3 0 0 0
|
||||
+ 0 0 0 0 0 0 0 0 0 0
|
||||
+ 0 0 0 0 0 2 2 2 2 0
|
||||
+ 2 0 0 1 1 1 1 1 1 1
|
||||
+ 1 1 1 1 1 1 0xe 0xe 0xe 0xe
|
||||
+ 0xe 0xe 0 >;
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&cp0_i2c0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <100000>;
|
||||
+ /* on som */
|
||||
+ eeprom0: eeprom@53 {
|
||||
+ compatible = "atmel,24c64";
|
||||
+ reg = <0x53>;
|
||||
+ pagesize = <0x20>;
|
||||
+ };
|
||||
+ /* on carrier */
|
||||
+ eeprom1: eeprom@50 {
|
||||
+ compatible = "i2c-eeprom";
|
||||
+ reg = <0x50>;
|
||||
+ pagesize = <0x16>;
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cp0_i2c1 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
+ clock-frequency = <100000>;
|
||||
+ rtc: rtc@68 {
|
||||
+ reg = <68>;
|
||||
+ compatible = "dallas,ds1339";
|
||||
+ /*connected to rtc DS1339U-33+*/
|
||||
+ };
|
||||
+ i2c-switch@e6 {
|
||||
+ compatible = "nxp,pca9543";
|
||||
+ reg = <0xe6>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ i2c_sfp0: i2c@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0>;
|
||||
+ /*connected to sfp cp0_eth0*/
|
||||
+ };
|
||||
+ i2c_sfp1: i2c@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <1>;
|
||||
+ /*connected to sfp cp1_eth1*/
|
||||
+ };
|
||||
+ };
|
||||
+ temp_sns:temp_sense@40 {
|
||||
+ reg = <40>;
|
||||
+
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* SD CARD */
|
||||
+&cp0_sdhci0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_sdhci_pins
|
||||
+ &cp0_sdhci_cd_pins>;
|
||||
+ bus-width = <4>;
|
||||
+ status = "okay";
|
||||
+ no-1-8-v;
|
||||
+ max-frequency = <25000000>;
|
||||
+};
|
||||
+
|
||||
+/* SPI NOR */
|
||||
+&cp0_spi1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp0_spi1_pins
|
||||
+ &cp0_spi1_cs1_pins>;
|
||||
+ reg = <0x700680 0x50>, /* control */
|
||||
+ <0x2000000 0x1000000>, /* CS0 */
|
||||
+ <0x2000000 0x1000004>, /* CS1 */
|
||||
+ <0 0xffffffff>, /* CS2 */
|
||||
+ <0 0xffffffff>; /* CS3 */
|
||||
+ status = "okay";
|
||||
+
|
||||
+ spi-flash@0 {
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x1>;
|
||||
+ compatible = "jedec,spi-nor", "spi-flash";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_comphy {
|
||||
+ phy0 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX0>;
|
||||
+ };
|
||||
+
|
||||
+ phy1 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII2>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+ };
|
||||
+
|
||||
+ phy2 {
|
||||
+ phy-type = <COMPHY_TYPE_SFI0>;
|
||||
+ phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
+ };
|
||||
+
|
||||
+ phy3 {
|
||||
+ phy-type = <COMPHY_TYPE_SGMII1>;
|
||||
+ phy-speed = <COMPHY_SPEED_1_25G>;
|
||||
+ };
|
||||
+
|
||||
+ phy4 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX1>;
|
||||
+ };
|
||||
+
|
||||
+ phy5 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX2>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_sata0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp0_usb3_0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&cp0_utmi0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&cp0_utmi1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp0_ethernet {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+
|
||||
+/* SRDS #0 - PCIe X1 mPCIe #0 */
|
||||
+&cp0_pcie0 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #1 - SGMII connected to VSC8584 1GbE PHY */
|
||||
+&cp0_eth2 {
|
||||
+ status = "okay";
|
||||
+// phy = <&cp0_vsc_phy19>; //address 0x0011001
|
||||
+ phy-mode = "sgmii";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #2 - 10GE SFP+ */
|
||||
+&cp0_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sfi";
|
||||
+ compatible = "sff,sfp";
|
||||
+
|
||||
+ /* for SFP direct connectivity */
|
||||
+// i2c-bus = <&i2c_sfp0>;
|
||||
+// mod-def0-gpio = <&cp0_gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
+
|
||||
+ /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
|
||||
+// phy = <&cp0_sfi_phy8>; //address 0x01000
|
||||
+};
|
||||
+
|
||||
+/* SRDS #3 - SGMII connected to VSC8584 1GbE PHY */
|
||||
+
|
||||
+&cp0_eth1 {
|
||||
+ status = "okay";
|
||||
+// phy = <&cp0_vsc_phy18>; //address 0x0011000
|
||||
+ phy-mode = "sgmii";
|
||||
+// phy = <&cp0_phy0>; // only for testing on cf-solidwan - to be removed for final dtb
|
||||
+};
|
||||
+
|
||||
+/* SRDS #4 - Extenssion conector */
|
||||
+&cp0_pcie1 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #5 - Extenssion connector */
|
||||
+&cp0_pcie2 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
|
||||
+&cp0_mdio {
|
||||
+ status = "disabled";
|
||||
+ pinctrl-0 = <&cp0_mdio_pins>;
|
||||
+
|
||||
+ /** only for testing on cf-solidwan - to be removed for final dtb */
|
||||
+/* cp0_phy0: ethernet-phy@0 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+ cp0_phy1: ethernet-phy@0 {
|
||||
+ marvell,reg-init = <3 16 0 0x1017>;
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+*/
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cp0_gpio0{
|
||||
+ phy_vsc8504_phy_reset {
|
||||
+ gpio-hog;
|
||||
+ gpios = <28 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "phy_vsc8504_phy_reset";
|
||||
+ };
|
||||
+ phy_vsc8254_phy_reset {
|
||||
+ gpio-hog;
|
||||
+ gpios = <31 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ line-name = "phy_vsc8254_phy_reset";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_gpio1{
|
||||
+ cpld_int_release {
|
||||
+ gpio-hog;
|
||||
+ gpios = <0 GPIO_ACTIVE_HIGH>; //MPP32
|
||||
+ output-high;
|
||||
+ line-name = "cpld_int_release";
|
||||
+ };
|
||||
+ cpld_status_int {
|
||||
+ gpio-hog;
|
||||
+ gpios = <1 GPIO_ACTIVE_HIGH>; //MPP33
|
||||
+ output-high;
|
||||
+ line-name = "cpld_status_int";
|
||||
+ };
|
||||
+ cpld_pwr_int {
|
||||
+ gpio-hog;
|
||||
+ gpios = <2 GPIO_ACTIVE_HIGH>; //MPP34
|
||||
+ output-high;
|
||||
+ line-name = "cpld_pwr_int";
|
||||
+ };
|
||||
+ cpld_reset_emmc{
|
||||
+ gpio-hog;
|
||||
+ gpios = <7 GPIO_ACTIVE_HIGH>; //MPP39
|
||||
+ output-high;
|
||||
+ line-name = "cpld_reset_emmc";
|
||||
+ };
|
||||
+ cpld_done {
|
||||
+ gpio-hog;
|
||||
+ gpios = <10 GPIO_ACTIVE_HIGH>; //MPP42
|
||||
+ input;
|
||||
+ line-name = "cpld_done";
|
||||
+ };
|
||||
+ cpld_prog_n {
|
||||
+ gpio-hog;
|
||||
+ gpios = <11 GPIO_ACTIVE_HIGH>; //MPP43
|
||||
+ output-high;
|
||||
+ line-name = "cpld_prog_n";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp0_pinctl {
|
||||
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
|
||||
+ bank-name ="cp0-110";
|
||||
+
|
||||
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
|
||||
+ marvell,pins = < 37 38 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
|
||||
+ marvell,pins = < 35 36 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
|
||||
+ marvell,pins = < 44 45 46 47 48 49 50 51
|
||||
+ 52 53 54 55 >;
|
||||
+ marvell,function = <1>;
|
||||
+ };
|
||||
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
|
||||
+ marvell,pins = < 56 57 58 59 60 61 >;
|
||||
+ marvell,function = <14>;
|
||||
+ };
|
||||
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
|
||||
+ marvell,pins = < 43 >;
|
||||
+ marvell,function = <1>;
|
||||
+ };
|
||||
+ cp0_spi1_pins: cp0-spi-pins-0 {
|
||||
+ marvell,pins = < 13 14 15 16 >;
|
||||
+ marvell,function = <3>;
|
||||
+ };
|
||||
+ cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
|
||||
+ marvell,pins = < 12 >;
|
||||
+ marvell,function = <3>;
|
||||
+ };
|
||||
+ cp0_mdio_pins: cp0-mdio-pins {
|
||||
+ marvell,pins = < 0 1 >;
|
||||
+ marvell,function = <10>;
|
||||
+ };
|
||||
+ cp0_ptp_pins: cp0-ptp-pins {
|
||||
+ marvell,pins = < 6 7 8 >;
|
||||
+ marvell,function = <9>;
|
||||
+ };
|
||||
+ cp0_uart1_pins: cp0-uart1-pins {
|
||||
+ marvell,pins = < 2 3 >;
|
||||
+ marvell,function = <8>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
new file mode 100644
|
||||
index 0000000000..d10c7f032e
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9131-bldn-mbv.dts
|
||||
@@ -0,0 +1,46 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2020 SolidRun ltd.
|
||||
+ *
|
||||
+ * SPDX-License-Identifier: GPL-2.0
|
||||
+ * https://spdx.org/licenses
|
||||
+ */
|
||||
+
|
||||
+/* cn9131-bldn mbv-a/b */
|
||||
+#include "cn9130-bldn-mbv.dts"
|
||||
+#include "cn9131-bldn-mbv.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Belden CN9131 based Platform";
|
||||
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
|
||||
+ "marvell,armada-ap806";
|
||||
+};
|
||||
+
|
||||
+&cp1_comphy {
|
||||
+ /* Serdes Configuration:
|
||||
+ * Lane 0: PCIe0 (x1)
|
||||
+ * Lane 1: USB3
|
||||
+ * Lane 2: ETH PORT 10GE
|
||||
+ * Lane 3: NC
|
||||
+ * Lane 4: PCIE1 X1
|
||||
+ * Lane 5: PCIe2 X1
|
||||
+ */
|
||||
+ phy0 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX0>;
|
||||
+ };
|
||||
+ phy1 {
|
||||
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
|
||||
+ };
|
||||
+ phy2 {
|
||||
+ phy-type = <COMPHY_TYPE_SFI0>;
|
||||
+ phy-speed = <COMPHY_SPEED_10_3125G>;
|
||||
+ };
|
||||
+ phy3 {
|
||||
+ phy-type = <COMPHY_TYPE_SATA1>;
|
||||
+ };
|
||||
+ phy4 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX1>;
|
||||
+ };
|
||||
+ phy5 {
|
||||
+ phy-type = <COMPHY_TYPE_PEX2>;
|
||||
+ };
|
||||
+};
|
||||
diff --git a/arch/arm/dts/cn9131-bldn-mbv.dtsi b/arch/arm/dts/cn9131-bldn-mbv.dtsi
|
||||
new file mode 100644
|
||||
index 0000000000..afd63d8ba6
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/cn9131-bldn-mbv.dtsi
|
||||
@@ -0,0 +1,223 @@
|
||||
+/*
|
||||
+* Copyright (C) 2020 SolidRun ltd.
|
||||
+*
|
||||
+* SPDX-License-Identifier: GPL-2.0
|
||||
+* https://spdx.org/licenses
|
||||
+*/
|
||||
+
|
||||
+/* Device Tree file for the cn1931 based belden mbv carrier board, cp1 */
|
||||
+
|
||||
+#undef CP110_NAME
|
||||
+#undef CP110_NUM
|
||||
+#undef CP110_PCIE_MEM_SIZE
|
||||
+#undef CP110_PCIEx_CPU_MEM_BASE
|
||||
+#undef CP110_PCIEx_BUS_MEM_BASE
|
||||
+
|
||||
+/* CP110-1 Settings */
|
||||
+#define CP110_NAME cp1
|
||||
+#define CP110_NUM 1
|
||||
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
|
||||
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
|
||||
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
|
||||
+
|
||||
+#include "armada-cp110.dtsi"
|
||||
+/ {
|
||||
+ model = "Belden CN9131 based MBV-A/B";
|
||||
+ compatible = "marvell,cn9131-db";
|
||||
+
|
||||
+ aliases {
|
||||
+ gpio3 = &cp1_gpio0;
|
||||
+ gpio4 = &cp1_gpio1;
|
||||
+ fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
|
||||
+ fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
|
||||
+ };
|
||||
+ cp1 {
|
||||
+ config-space {
|
||||
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "cp1-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ };
|
||||
+ cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "cp1-xhci0-vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ startup-delay-us = <100000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ };
|
||||
+
|
||||
+ cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-min-microamp = <900000>;
|
||||
+ regulator-max-microamp = <900000>;
|
||||
+ regulator-force-boot-off;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp1_ld_efuse0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_ld_efuse1 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_i2c1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&cp1_i2c1_pins>;
|
||||
+ status = "okay";
|
||||
+ clock-frequency = <100000>;
|
||||
+};
|
||||
+
|
||||
+&cp1_utmi0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+&cp1_utmi1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cp1_usb3_0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_xmdio {
|
||||
+ status = "okay";
|
||||
+ pinctrl-0 = <&cp1_xmdio_pins>;
|
||||
+ cp0_sfi_phy8: ethernet-phy@8 {
|
||||
+ reg = <8>;
|
||||
+ };
|
||||
+ cp1_sfi_phy9: ethernet-phy@9 {
|
||||
+ reg = <9>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cp1_mdio {
|
||||
+ status = "okay";
|
||||
+ pinctrl-0 = <&cp1_mdio_pins>;
|
||||
+ cp0_vsc_phy18: ethernet-phy@18 {
|
||||
+ reg = <18>;
|
||||
+ };
|
||||
+ cp0_vsc_phy19: ethernet-phy@19 {
|
||||
+ reg = <19>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+
|
||||
+&cp1_pinctl {
|
||||
+ compatible = "marvell,mvebu-pinctrl",
|
||||
+ "marvell,cp115-standalone-pinctrl";
|
||||
+ bank-name ="cp1-110";
|
||||
+
|
||||
+ /* MPP Bus:
|
||||
+ * [3:2] xmdio
|
||||
+ * [5:4] mdio
|
||||
+ * [36:35] i2c1
|
||||
+ * [43:40] rs232
|
||||
+ */
|
||||
+ /* 0 1 2 3 4 5 6 7 8 9 */
|
||||
+ pin-func = < 0x0 0x0 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x2 0x2 0x0 0x0 0x0
|
||||
+ 0x7 0x7 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 >;
|
||||
+
|
||||
+ cp1_i2c1_pins: cp1-i2c-pins-1 {
|
||||
+ marvell,pins = < 35 36 >;
|
||||
+ marvell,function = <2>;
|
||||
+ };
|
||||
+ cp1_xmdio_pins: cp1-xmdio-pins-0 {
|
||||
+ marvell,pins = < 2 3 >;
|
||||
+ marvell,function = <10>;
|
||||
+ };
|
||||
+ cp1_mdio_pins: cp1-mdio-pins-0 {
|
||||
+ marvell,pins = < 4 5 >;
|
||||
+ marvell,function = <10>;
|
||||
+ };
|
||||
+ cp1_uart1_pins: cp1-uart1-pins-0 {
|
||||
+ marvell,pins = < 40 41 42 43 >;
|
||||
+ marvell,function = <7>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* SATA0 */
|
||||
+&cp1_sata0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&cp1_ethernet {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #0 - PCIe Extenssion card */
|
||||
+&cp1_pcie0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+ ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
|
||||
+};
|
||||
+
|
||||
+/* SRDS #1 - USB Extenssion card */
|
||||
+&cp1_usb3_0 {
|
||||
+ status = "okay";
|
||||
+ vbus-supply = <&cp1_reg_usb3_vbus0>;
|
||||
+};
|
||||
+
|
||||
+/* SRDS #2 - 10GE SFP+ */
|
||||
+&cp1_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy-mode = "sfi";
|
||||
+ compatible = "sff,sfp";
|
||||
+
|
||||
+ /* for SFP direct connectivity */
|
||||
+// i2c-bus = <i2c_sfp1>;
|
||||
+// mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
|
||||
+// compatible = "sff,sfp";
|
||||
+// maximum-power-milliwatt = <2000>;
|
||||
+
|
||||
+ /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
|
||||
+ phy = <&cp1_sfi_phy9>; //address 0x01001
|
||||
+
|
||||
+};
|
||||
+
|
||||
+/* SRDS #3 - not in use */
|
||||
+
|
||||
+
|
||||
+/* SRDS #4 - mPCIe */
|
||||
+&cp1_pcie1 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* SRDS #5 - mPCIe */
|
||||
+&cp1_pcie2 {
|
||||
+ num-lanes = <1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/*************** definitions of addresses for cp0 eth ports ************/
|
||||
+
|
||||
+&cp0_eth0 {
|
||||
+ status = "okay";
|
||||
+ phy = <&cp0_sfi_phy8>; //address 0x01000
|
||||
+};
|
||||
+
|
||||
+&cp0_eth1 {
|
||||
+ status = "okay";
|
||||
+ phy = <&cp0_vsc_phy18>; //address 0x0011000
|
||||
+};
|
||||
+
|
||||
+&cp0_eth2 {
|
||||
+ status = "okay";
|
||||
+ phy = <&cp0_vsc_phy19>; //address 0x0011001
|
||||
+};
|
||||
+
|
||||
|
|
@ -0,0 +1 @@
|
|||
CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome"
|
||||
DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \
|
||||
ARM, MIPS and several other processors, which can be installed in a boot \
|
||||
ROM and used to initialize and test the hardware or to download and run \
|
||||
application code."
|
||||
SECTION = "bootloaders"
|
||||
DEPENDS += "flex-native bison-native"
|
||||
|
||||
COMPATIBLE_MACHINE = "cn913x"
|
||||
|
||||
LICENSE = "GPLv2+"
|
||||
LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e"
|
||||
PE = "1"
|
||||
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/files_2019.10-solidrun:"
|
||||
|
||||
# We use the revision in order to avoid having to fetch it from the
|
||||
# repo during parse
|
||||
SRCREV = "61ba1244b548463dbfb3c5285b6b22e7c772c5bd"
|
||||
|
||||
# Patch from https://github.com/SolidRun/cn913x_build
|
||||
# Git SHA: f33e2aeb01c7ee061be7b053035ae87ce30fce4a
|
||||
SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
|
||||
file://solidrun/0001-cmd-add-tlv_eeprom-command.patch \
|
||||
file://solidrun/0002-cmd-tlv_eeprom.patch \
|
||||
file://solidrun/0003-cmd-tlv_eeprom-remove-use-of-global-variable-current.patch \
|
||||
file://solidrun/0004-cmd-tlv_eeprom-remove-use-of-global-variable-has_bee.patch \
|
||||
file://solidrun/0005-cmd-tlv_eeprom-do_tlv_eeprom-stop-using-non-api-read.patch \
|
||||
file://solidrun/0006-cmd-tlv_eeprom-convert-functions-used-by-command-to-.patch \
|
||||
file://solidrun/0007-cmd-tlv_eeprom-remove-empty-function-implementations.patch \
|
||||
file://solidrun/0008-cmd-tlv_eeprom-split-off-tlv-library-from-command.patch \
|
||||
file://solidrun/0009-lib-tlv_eeprom-add-function-for-reading-one-entry-in.patch \
|
||||
file://solidrun/0010-uboot-marvell-patches.patch \
|
||||
file://solidrun/0011-uboot-support-cn913x-solidrun-paltfroms.patch \
|
||||
file://solidrun/0012-add-SoM-and-Carrier-eeproms.patch \
|
||||
file://solidrun/0013-find-fdtfile-from-tlv-eeprom.patch \
|
||||
file://solidrun/0014-octeontx2_cn913x-support-distro-boot.patch \
|
||||
file://solidrun/0015-octeontx2_cn913x-remove-console-variable.patch \
|
||||
file://solidrun/0016-octeontx2_cn913x-enable-mmc-partconf-command.patch \
|
||||
file://solidrun/0017-uboot-add-support-cn9131-cf-solidwan.patch \
|
||||
file://solidrun/0018-uboot-add-support-bldn-mbv.patch \
|
||||
file://0001-Remove-redundant-YYLOC-global-declaration.patch \
|
||||
file://0001-sr_cn913x_cex7-enable-more-image-formats.patch \
|
||||
file://0021-octeontx2_cn913x-increase-CONFIG_SYS_BOOTM_LEN-to-32.patch \
|
||||
file://0001-sr_cn913x_cex7-enable-VERSION_VARIABLE.patch \
|
||||
file://cn913x.cfg \
|
||||
file://0001-cn9130-fix-compatible-node-inside-dts.patch \
|
||||
file://0001-cn9130-fix-compatible-node-inside-dts-pt-2.patch \
|
||||
"
|
||||
|
||||
S = "${WORKDIR}/git"
|
||||
|
||||
require recipes-bsp/u-boot/u-boot.inc
|
||||
require recipes-bsp/u-boot/u-boot-coreos.inc
|
||||
|
||||
# Solidrun patches require to build out-of-the-tree
|
||||
B = "${WORKDIR}/build"
|
||||
|
||||
DEPENDS += "bc-native dtc-native u-boot-mkimage-native"
|
||||
|
||||
do_compile:prepend() {
|
||||
export DEVICE_TREE="${UBOOT_BUILDENV_DEVICE_TREE}"
|
||||
}
|
||||
|
||||
SYSROOT_DIRS += " /boot "
|
||||
|
|
@ -12,6 +12,8 @@ LICENSE = "GPL-2.0-or-later"
|
|||
LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1"
|
||||
PE = "1"
|
||||
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/files_2023.04-marvell:"
|
||||
|
||||
# We use the revision in order to avoid having to fetch it from the
|
||||
# repo during parse
|
||||
SRCREV = "6add83991b2887619d0b25e4068b4c0082a4596a"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
label: gpt
|
||||
device: /dev/mmcblk0
|
||||
unit: sectors
|
||||
first-lba: 34
|
||||
last-lba: 15269854
|
||||
sector-size: 512
|
||||
|
||||
# Partition should be aligned at 2048S for best performance
|
||||
|
||||
# EBBR 2.1.0 section 4.1.1 mandate the use of an unused type UUID and to set
|
||||
# the RequiredPartition label for part of the firmware stored in the main disk
|
||||
# https://arm-software.github.io/ebbr/#section-gpt-parts
|
||||
# UUID type of fw0 and fw1 was generated
|
||||
# The bootloader can be at 5 different position: 1S, 34S, 4096S, 8192S, 12288S
|
||||
# GPT disk use sector 0-33S, so first free slot is 34S
|
||||
# Current bootloader is about 1.8MB, so if we put it at 4096S and 12288S we
|
||||
# have 4MiB between the first bootloader and the second copy of it
|
||||
/dev/mmcblk0p1 : start= 4096, size= 8192, type=71B02716-C000-4F0D-AE03-2F5DC0A114CD, name="fw0", attrs="RequiredPartition"
|
||||
/dev/mmcblk0p2 : start= 12288, size= 8192, type=71B02716-C000-4F0D-AE03-2F5DC0A114CD, name="fw1", attrs="RequiredPartition"
|
||||
|
||||
/dev/mmcblk0p3 : start= 20480, size= 131072, ${SFDISK_PART_EFI}
|
||||
/dev/mmcblk0p4 : start= 151552, size= 262144, ${SFDISK_PART_EFIBOOTGUARD_A}
|
||||
/dev/mmcblk0p5 : start= 413696, size= 262144, ${SFDISK_PART_EFIBOOTGUARD_B}
|
||||
/dev/mmcblk0p6 : start= 675840, size= 7294976, ${SFDISK_PART_ROOT_A}
|
||||
/dev/mmcblk0p7 : start= 7970816, size= 7294976, ${SFDISK_PART_ROOT_B}
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
FILESEXTRAPATHS:prepend := "${THISDIR}/coreos-installer-config:"
|
||||
|
||||
SRC_URI:append:cn913x = " file://cn9130-cf-pro_1.0.sfdisk"
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
From fe9fd6b88869cecf0965087d67ce64b1aac95233 Mon Sep 17 00:00:00 2001
|
||||
From: Dimitry Shapovalov <dimitry.shapovalov@belden.com>
|
||||
Date: Tue, 30 May 2023 13:09:47 +0200
|
||||
Subject: [PATCH] fix phy support for falcon board
|
||||
|
||||
adjust the devicetree to get the phys up and running
|
||||
---
|
||||
.../boot/dts/marvell/cn9130-bldn-mbv.dts | 17 +++++-----
|
||||
.../boot/dts/marvell/cn9131-bldn-mbv.dts | 31 +++++--------------
|
||||
2 files changed, 17 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts b/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
|
||||
index 8be9c2cc1330..da6289571083 100644
|
||||
--- a/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
|
||||
@@ -98,7 +98,7 @@ cp0_sfp_eth0: sfp-eth@0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c_sfp0>;
|
||||
mod-def0-gpio = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; //MPP27
|
||||
- //maximum-power-milliwatt = <2000>;
|
||||
+ maximum-power-milliwatt = <2000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sfp_cp0_eth0_present_pins>;
|
||||
};
|
||||
@@ -175,7 +175,7 @@ rtc: rtc@68 {
|
||||
/*connected to rtc DS1339U-33+*/
|
||||
};
|
||||
i2c-switch@73 {
|
||||
- compatible = "nxp,pca9544";
|
||||
+ compatible = "nxp,pca9543";
|
||||
reg = <0x73>;
|
||||
#address-cells = <1>;
|
||||
#size-cell = <0>;
|
||||
@@ -248,11 +248,7 @@ &cp0_eth0 {
|
||||
managed = "in-band-status";
|
||||
|
||||
/* for SFP direct connectivity */
|
||||
-// sfp = <&cp0_sfp_eth0>;
|
||||
-
|
||||
- /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
|
||||
-// phy = <&cp0_sfi_phy8>; //address 0x01000
|
||||
-
|
||||
+ sfp = <&cp0_sfp_eth0>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - SGMII 1GE on carrier board */
|
||||
@@ -305,6 +301,13 @@ spi-flash@0 {
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
+ spi-cpld@1 {
|
||||
+ compatible = "rohm,dh2228fv";
|
||||
+ reg = <0x1>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ spi-max-frequency = <10000000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
diff --git a/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts b/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
|
||||
index 43ef7e6cb92f..0bfd2c8cb0b4 100644
|
||||
--- a/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
|
||||
+++ b/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
|
||||
@@ -42,7 +42,7 @@ cp1_usb3_0_phy1: cp1_usb3_phy@1 {
|
||||
};
|
||||
cp1_sfp_eth0: sfp_eth0{
|
||||
compatible = "sff,sfp";
|
||||
- // i2c-bus = <&i2c_sfp1>;
|
||||
+ i2c-bus = <&i2c_sfp1>;
|
||||
mod-def0-gpio = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>; //MPP50
|
||||
maximum-power-milliwatt = <2000>;
|
||||
pinctrl-0 = <&sfp_cp1_present_pins>;
|
||||
@@ -104,10 +104,7 @@ &cp1_eth0 {
|
||||
managed = "in-band-status";
|
||||
|
||||
/* for SFP direct connectivity */
|
||||
-// sfp = <&cp1_sfp_eth0>;
|
||||
-
|
||||
- /* MBV-A BCM PHY | MBV-B VSC Microchip PHY */
|
||||
- phy = <&cp1_sfi_phy9>; //address 0x01001
|
||||
+ sfp = <&cp1_sfp_eth0>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - NC */
|
||||
@@ -142,25 +139,14 @@ &cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
-&cp1_xmdio {
|
||||
- status = "okay";
|
||||
- pinctrl-0 = <&cp1_xmdio_pins>;
|
||||
- cp0_sfi_phy8: ethernet-phy@8 {
|
||||
- reg = <8>;
|
||||
- };
|
||||
- cp1_sfi_phy9: ethernet-phy@9 {
|
||||
- reg = <9>;
|
||||
- };
|
||||
-};
|
||||
-
|
||||
&cp1_mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&cp1_mdio_pins>;
|
||||
cp0_vsc_phy18: ethernet-phy@18 {
|
||||
- reg = <18>;
|
||||
+ reg = <0x18>;
|
||||
};
|
||||
cp0_vsc_phy19: ethernet-phy@19 {
|
||||
- reg = <19>;
|
||||
+ reg = <0x19>;
|
||||
};
|
||||
|
||||
};
|
||||
@@ -237,18 +223,15 @@ cp1_uart1_pins: cp1-uart1-pins-1 {
|
||||
|
||||
/*************** definitions of addresses for cp0 eth ports ************/
|
||||
|
||||
-&cp0_eth0 {
|
||||
- status = "okay";
|
||||
- phy = <&cp0_sfi_phy8>; //address 0x01000
|
||||
-};
|
||||
-
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&cp0_vsc_phy18>; //address 0x0011000
|
||||
+ managed = "auto";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
status = "okay";
|
||||
phy = <&cp0_vsc_phy19>; //address 0x0011001
|
||||
+ managed = "auto";
|
||||
};
|
||||
-
|
||||
+
|
||||
\ No newline at end of file
|
||||
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Reference in New Issue