diff --git a/external-layers/meta-ti b/external-layers/meta-ti index 0f9035a..2e3ffb7 160000 --- a/external-layers/meta-ti +++ b/external-layers/meta-ti @@ -1 +1 @@ -Subproject commit 0f9035a628c10ec0e0656387989e99b1365f184f +Subproject commit 2e3ffb73630f4ff78227822bdb4c23e75a720223 diff --git a/layers/meta-netmodule-coreos-bsp/classes/coreos-image-swupdate-am64xx.bbclass b/layers/meta-netmodule-coreos-bsp/classes/coreos-image-swupdate-am64xx.bbclass index cb7ae92..3d881b3 100644 --- a/layers/meta-netmodule-coreos-bsp/classes/coreos-image-swupdate-am64xx.bbclass +++ b/layers/meta-netmodule-coreos-bsp/classes/coreos-image-swupdate-am64xx.bbclass @@ -1,8 +1,8 @@ -SWUPDATE_IMAGES += "tiboot3" +SWUPDATE_IMAGES += "tiboot3-am64x-gemini-b" SWUPDATE_IMAGES += "tispl" SWUPDATE_IMAGES += "u-boot-${MACHINE}" -SWUPDATE_IMAGES_FSTYPES[tiboot3] = ".bin" +SWUPDATE_IMAGES_FSTYPES[tiboot3-am64x-gemini-b] = ".bin" SWUPDATE_IMAGES_FSTYPES[tispl] = ".bin" python () { @@ -20,12 +20,12 @@ def coreos_swupdate_extends_images_for_am64xx(d,s): return [ { - "filename" : "tiboot3.bin", + "filename" : "tiboot3-am64x-gemini-b.bin", "installed-directly" : "true", "device" : "/dev/mmcblk0boot0", "offset": str(OFFSET[0]), "type" : "raw", - "sha256" : swupdate_get_sha256(d, s, "tiboot3.bin"), + "sha256" : swupdate_get_sha256(d, s, "tiboot3-am64x-gemini-b.bin"), }, { "filename" : "tispl.bin", diff --git a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-common.inc b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-common.inc index 4f9aebe..bd89ec5 100644 --- a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-common.inc +++ b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-common.inc @@ -1,8 +1,6 @@ # This file contains the part of the configuration that is common to all # board based on the Gemini platform and that are the same for both # the Cortex-A53 and Cortex-R5 core (Gemini use a multi-arch SOC) -TI_LINUX_FW_SRCREV = "0f4905088d24e474063f33777559149e11538be5" -K3_IMAGE_GEN_SRCREV ?= "2308bfb01e7bd3e03514cb33f06180dd9bb79121" PREFERRED_PROVIDER_virtual/bootloader = "u-boot-ti-coreos" PREFERRED_PROVIDER_u-boot = "u-boot-ti-coreos" diff --git a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3.inc b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3.inc index 91c527b..70b9a40 100644 --- a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3.inc +++ b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3.inc @@ -6,7 +6,7 @@ WKS_FILE ?= "" require conf/machine/include/k3.inc -require conf/machine/include/netmodule-am64xx-common.inc +require netmodule-am64xx-common.inc # Workarround to remove wic related settings added to IMAGE_FSTYPE in k3.inc # without too much risk of breaking a distro or local config (as remove) diff --git a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3r5.inc b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3r5.inc index 53cb775..d8da30d 100644 --- a/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3r5.inc +++ b/layers/meta-netmodule-coreos-bsp/conf/machine/include/netmodule-am64xx-k3r5.inc @@ -2,11 +2,12 @@ # board based on the Gemini platform and that are the Cortex-R5 core. require conf/machine/include/k3r5.inc -require conf/machine/include/netmodule-am64xx-common.inc +require netmodule-am64xx-common.inc -SYSFW_SOC = "am64x" -SYSFW_CONFIG = "evm" -SYSFW_SUFFIX = "gp" +# A variant +#SPL_BINARY = "tiboot3-am64x-gemini.${SPL_SUFFIX}" +# B variant +SPL_BINARY = "tiboot3-am64x-gemini-b.${SPL_SUFFIX}" # Sanity checks don't apply for real time cores INHERIT:remove = "coreos-sanity" diff --git a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0001-ram-k3-ddrss-Fix-a-ddr4-controller-stall.patch b/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0001-ram-k3-ddrss-Fix-a-ddr4-controller-stall.patch deleted file mode 100644 index 1b13919..0000000 --- a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0001-ram-k3-ddrss-Fix-a-ddr4-controller-stall.patch +++ /dev/null @@ -1,43 +0,0 @@ -From cf50887c0d4053d5a454971633b1f71d477ebc6b Mon Sep 17 00:00:00 2001 -From: Stefan Eichenberger -Date: Tue, 7 Feb 2023 09:20:15 +0100 -Subject: [PATCH] ram: k3-ddrss: Fix a ddr4 controller stall - -The DDR4 controller might stall indefinitely if we access the same -register twice withing a short time interval. This commit makes sure we -reuse the previously read value so that we don't have to access twice. -See this article for more information: -https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057242/am6442-access-to-ddr4-controller-register-stalls-indefinitely-while-in-lpddr4-frequency-update ---- - drivers/ram/k3-ddrss/k3-ddrss.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c -index e8b7aec9e0..b4acb3aea6 100644 ---- a/drivers/ram/k3-ddrss/k3-ddrss.c -+++ b/drivers/ram/k3-ddrss/k3-ddrss.c -@@ -241,15 +241,13 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss) - } - } - -+static u32 dram_class = DENALI_CTL_0_DRAM_CLASS_LPDDR4; - static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) - { -- u32 dram_class; - struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance; - - debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n"); - -- dram_class = k3_lpddr4_read_ddr_type(pd); -- - switch (dram_class) { - case DENALI_CTL_0_DRAM_CLASS_DDR4: - break; -@@ -263,7 +261,6 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd) - - static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss) - { -- u32 dram_class; - int ret; - lpddr4_privatedata *pd = &ddrss->pd; - diff --git a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0002-gemini-board-add-board-and-device-tree.patch b/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0002-gemini-board-add-board-and-device-tree.patch deleted file mode 100644 index 02b88c2..0000000 --- a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos/0002-gemini-board-add-board-and-device-tree.patch +++ /dev/null @@ -1,1845 +0,0 @@ -From 985be59763483746f159e17dd62a6a90083edebf Mon Sep 17 00:00:00 2001 -From: Stefan Eichenberger -Date: Tue, 7 Feb 2023 09:24:16 +0100 -Subject: [PATCH] gemini: board: add board and device tree - -Add gemini as new am64x board including, board configuration, devicetree -and configuration. - ---- - arch/arm/dts/Makefile | 4 +- - arch/arm/dts/k3-am642-gemini-binman.dtsi | 159 +++++++ - arch/arm/dts/k3-am642-gemini-u-boot.dtsi | 135 ++++++ - arch/arm/dts/k3-am642-netmodule-hw34.dts | 476 ++++++++++++++++++++ - arch/arm/dts/k3-am642-r5-netmodule-hw34.dts | 226 ++++++++++ - arch/arm/mach-k3/Kconfig | 2 + - arch/arm/mach-k3/common.c | 5 + - board/nm/am64x/Kconfig | 60 +++ - board/nm/am64x/Makefile | 9 + - board/nm/am64x/gemini.c | 166 +++++++ - board/nm/am64x/sysreset.c | 60 +++ - configs/am64x_netmodule_hw34_a53_defconfig | 179 ++++++++ - configs/am64x_netmodule_hw34_r5_defconfig | 170 +++++++ - include/configs/am64x_gemini.h | 61 +++ - 14 files changed, 1711 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/k3-am642-gemini-binman.dtsi - create mode 100644 arch/arm/dts/k3-am642-gemini-u-boot.dtsi - create mode 100644 arch/arm/dts/k3-am642-netmodule-hw34.dts - create mode 100644 arch/arm/dts/k3-am642-r5-netmodule-hw34.dts - create mode 100644 board/nm/am64x/Kconfig - create mode 100644 board/nm/am64x/Makefile - create mode 100644 board/nm/am64x/gemini.c - create mode 100644 board/nm/am64x/sysreset.c - create mode 100644 configs/am64x_netmodule_hw34_a53_defconfig - create mode 100644 configs/am64x_netmodule_hw34_r5_defconfig - create mode 100644 include/configs/am64x_gemini.h - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 43951a7731..2f6f09a4f4 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -1254,7 +1254,9 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\ - dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ - k3-am642-r5-evm.dtb \ - k3-am642-sk.dtb \ -- k3-am642-r5-sk.dtb -+ k3-am642-r5-sk.dtb \ -+ k3-am642-netmodule-hw34.dtb \ -+ k3-am642-r5-netmodule-hw34.dtb - - dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ - k3-am625-r5-sk.dtb -diff --git a/arch/arm/dts/k3-am642-gemini-binman.dtsi b/arch/arm/dts/k3-am642-gemini-binman.dtsi -new file mode 100644 -index 0000000000..a06dc706b3 ---- /dev/null -+++ b/arch/arm/dts/k3-am642-gemini-binman.dtsi -@@ -0,0 +1,159 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ -+ */ -+ -+/ { -+ binman: binman { -+ multiple-images; -+ }; -+}; -+ -+#define TISPL "tispl.bin" -+#define UBOOT_IMG "u-boot.img" -+ -+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin" -+#define SPL_AM642_GEMINI_DTB "spl/dts/k3-am642-netmodule-hw34.dtb" -+ -+#define UBOOT_NODTB "u-boot-nodtb.bin" -+#define AM642_GEMINI_DTB "arch/arm/dts/k3-am642-netmodule-hw34.dtb" -+ -+&binman { -+ ti-spl { -+ filename = TISPL; -+ pad-byte = <0xff>; -+ -+ fit { -+ description = "Configuration to load ATF and SPL"; -+ #address-cells = <1>; -+ -+ images { -+ -+ atf { -+ description = "ARM Trusted Firmware"; -+ type = "firmware"; -+ arch = "arm64"; -+ compression = "none"; -+ os = "arm-trusted-firmware"; -+ load = ; -+ entry = ; -+ atf-bl31 { -+ filename = "bl31.bin"; -+ }; -+ }; -+ -+ tee { -+ description = "OPTEE"; -+ type = "tee"; -+ arch = "arm64"; -+ compression = "none"; -+ os = "tee"; -+ load = <0x9e800000>; -+ entry = <0x9e800000>; -+ tee-os { -+ filename = "tee-pager_v2.bin"; -+ }; -+ }; -+ -+ dm { -+ description = "DM binary"; -+ type = "firmware"; -+ arch = "arm32"; -+ compression = "none"; -+ os = "DM"; -+ load = <0x89000000>; -+ entry = <0x89000000>; -+ blob-ext { -+ filename = "/dev/null"; -+ }; -+ }; -+ -+ spl { -+ description = "SPL (64-bit)"; -+ type = "standalone"; -+ os = "U-Boot"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <0x80080000>; -+ entry = <0x80080000>; -+ blob { -+ filename = SPL_NODTB; -+ }; -+ }; -+ -+ fdt-1 { -+ description = "k3-am642-gemini"; -+ type = "flat_dt"; -+ arch = "arm"; -+ compression = "none"; -+ blob { -+ filename = SPL_AM642_GEMINI_DTB; -+ }; -+ }; -+ }; -+ -+ configurations { -+ default = "conf-1"; -+ -+ conf-1 { -+ description = "k3-am642-gemini"; -+ firmware = "atf"; -+ loadables = "tee", "dm", "spl"; -+ fdt = "fdt-1"; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&binman { -+ u-boot { -+ filename = UBOOT_IMG; -+ pad-byte = <0xff>; -+ -+ fit { -+ description = "FIT image with multiple configurations"; -+ -+ images { -+ uboot { -+ description = "U-Boot for am64x board"; -+ type = "firmware"; -+ os = "u-boot"; -+ arch = "arm"; -+ compression = "none"; -+ load = ; -+ blob { -+ filename = UBOOT_NODTB; -+ }; -+ hash { -+ algo = "crc32"; -+ }; -+ }; -+ -+ fdt-1 { -+ description = "k3-am642-gemini"; -+ type = "flat_dt"; -+ arch = "arm"; -+ compression = "none"; -+ blob { -+ filename = AM642_GEMINI_DTB; -+ }; -+ hash { -+ algo = "crc32"; -+ }; -+ }; -+ }; -+ -+ configurations { -+ default = "conf-1"; -+ -+ conf-1 { -+ description = "k3-am642-gemini"; -+ firmware = "uboot"; -+ loadables = "uboot"; -+ fdt = "fdt-1"; -+ }; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm/dts/k3-am642-gemini-u-boot.dtsi b/arch/arm/dts/k3-am642-gemini-u-boot.dtsi -new file mode 100644 -index 0000000000..e061ebb06d ---- /dev/null -+++ b/arch/arm/dts/k3-am642-gemini-u-boot.dtsi -@@ -0,0 +1,135 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -+ */ -+#include -+ -+#include "k3-am642-gemini-binman.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ tick-timer = &timer1; -+ }; -+ -+ memory@80000000 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&cbass_main{ -+ u-boot,dm-spl; -+ timer1: timer@2400000 { -+ compatible = "ti,omap5430-timer"; -+ reg = <0x0 0x2400000 0x0 0x80>; -+ ti,timer-alwon; -+ clock-frequency = <200000000>; -+ u-boot,dm-spl; -+ }; -+}; -+ -+&main_conf { -+ u-boot,dm-spl; -+ chipid@14 { -+ u-boot,dm-spl; -+ }; -+}; -+ -+&main_pmx0 { -+ u-boot,dm-spl; -+}; -+ -+&main_uart0 { -+ u-boot,dm-spl; -+}; -+ -+&usb0 { -+ dr_mode="peripheral"; -+ u-boot,dm-spl; -+}; -+ -+&usbss0 { -+ u-boot,dm-spl; -+}; -+ -+&main_mmc1_pins_default { -+ u-boot,dm-spl; -+}; -+ -+&main_usb0_pins_default { -+ u-boot,dm-spl; -+}; -+ -+&dmss { -+ u-boot,dm-spl; -+}; -+ -+&secure_proxy_main { -+ u-boot,dm-spl; -+}; -+ -+&dmsc { -+ u-boot,dm-spl; -+ k3_sysreset: sysreset-controller { -+ compatible = "ti,sci-sysreset"; -+ u-boot,dm-spl; -+ status = "disabled"; -+ }; -+}; -+ -+&k3_pds { -+ u-boot,dm-spl; -+}; -+ -+&k3_clks { -+ u-boot,dm-spl; -+}; -+ -+&k3_reset { -+ u-boot,dm-spl; -+}; -+ -+&sdhci0 { -+ u-boot,dm-spl; -+}; -+ -+&sdhci1 { -+ no-1-8-v; -+ u-boot,dm-spl; -+}; -+ -+&cpsw3g { -+ reg = <0x0 0x8000000 0x0 0x200000>, -+ <0x0 0x43000200 0x0 0x8>; -+ reg-names = "cpsw_nuss", "mac_efuse"; -+ /delete-property/ ranges; -+ -+ cpsw-phy-sel@04044 { -+ compatible = "ti,am64-phy-gmii-sel"; -+ reg = <0x0 0x43004044 0x0 0x8>; -+ }; -+}; -+ -+&cpsw_port2 { -+ status = "disabled"; -+}; -+ -+&main_bcdma { -+ u-boot,dm-spl; -+}; -+ -+&main_pktdma { -+ u-boot,dm-spl; -+}; -+ -+&fss { -+ u-boot,dm-spl; -+}; -+ -+&main_gpio0 { -+ u-boot,dm-spl; -+}; -+ -+&main_gpio1 { -+ u-boot,dm-spl; -+}; -diff --git a/arch/arm/dts/k3-am642-netmodule-hw34.dts b/arch/arm/dts/k3-am642-netmodule-hw34.dts -new file mode 100644 -index 0000000000..be33f6ab87 ---- /dev/null -+++ b/arch/arm/dts/k3-am642-netmodule-hw34.dts -@@ -0,0 +1,476 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include -+#include "k3-am642.dtsi" -+ -+/ { -+ compatible = "netmodule,hw34", "ti,am642"; -+ model = "NetModule AM642 based Gemini"; -+ -+ aliases { -+ i2c0 = &main_i2c0; -+ i2c1 = &main_i2c1; -+ i2c2 = &main_i2c2; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ /* 1G RAM */ -+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; -+ -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ secure_ddr: optee@9e800000 { -+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ -+ alignment = <0x1000>; -+ no-map; -+ }; -+ }; -+ -+ config { -+ u-boot,mmc-env-offset = <0x3e0000>; /* 4MB partition, we put it into the last 128 kB */ -+ }; -+ -+ gemini-sysreset { -+ compatible = "gemini-sysreset"; -+ }; -+}; -+ -+&main_pmx0 { -+ main_mmc1_pins_default: main-mmc1-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ -+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ -+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ -+ AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ -+ AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ -+ AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ -+ AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ -+ AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ -+ >; -+ }; -+ -+ main_uart0_pins_default: main-uart0-pins-default { -+ u-boot,dm-spl; -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ -+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ -+ >; -+ }; -+ -+ gpio0_pins: gpio0-pins { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPIO0_35 */ -+ AM64X_IOPAD(0x008C, PIN_INPUT, 7) /* (T21) GPIO0_34 */ -+ AM64X_IOPAD(0x00A0, PIN_OUTPUT, 7) /* (N16) GPIO0_39 */ -+ AM64X_IOPAD(0x0098, PIN_INPUT, 7) /* (W19) GPIO0_37 */ -+ AM64X_IOPAD(0x009C, PIN_INPUT, 7) /* (Y18) GPIO0_38 */ -+ AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (Y19) GPIO0_36 */ -+ AM64X_IOPAD(0x00A8, PIN_INPUT, 7) /* (R19) GPIO0_41 */ -+ AM64X_IOPAD(0x00AC, PIN_INPUT, 7) /* (R20) GPIO0_42 */ -+ AM64X_IOPAD(0x00A4, PIN_INPUT, 7) /* (N17) GPIO0_40 */ -+ -+ AM64X_IOPAD(0x011c, PIN_INPUT, 7) /* (AA13) GPIO0_70 */ -+ AM64X_IOPAD(0x0128, PIN_OUTPUT, 7) /* (U12) GPIO0_73 */ -+ AM64X_IOPAD(0x0150, PIN_INPUT, 7) /* (Y13) GPIO0_20 */ -+ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) GPIO0_84 */ -+ AM64X_IOPAD(0x00d8, PIN_INPUT, 7) /* (W13) GPIO0_53 */ -+ AM64X_IOPAD(0x00cc, PIN_INPUT, 7) /* (V13) GPIO0_50 */ -+ -+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 7) /* (V15) GPIO0_72 */ -+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 7) /* (V14) GPIO0_74 */ -+ AM64X_IOPAD(0x0130, PIN_INPUT, 7) /* (W14) GPIO0_75 */ -+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 7) /* (AA14) GPIO0_19 */ -+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 7) /* (U14) GPIO0_55 */ -+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (U15) GPIO0_54 */ -+ -+ AM64X_IOPAD(0x0114, PIN_INPUT, 7) /* (Y12) GPIO0_68 */ -+ AM64X_IOPAD(0x0118, PIN_OUTPUT, 7) /* (W12) GPIO0_69 */ -+ -+ -+ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ -+ AM64X_IOPAD(0x00c0, PIN_OUTPUT, 7) /* (W8) GPIO0_47 */ -+ AM64X_IOPAD(0x00c4, PIN_OUTPUT, 7) /* (W8) GPIO0_48 */ -+ AM64X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (W8) GPIO0_49 */ -+ AM64X_IOPAD(0x00fc, PIN_INPUT, 7) /* (U7) GPIO0_62 */ -+ -+ AM64X_IOPAD(0x002c, PIN_OUTPUT, 7) /* (L19) GPIO0_11 */ -+ AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) GPIO0_12 */ -+ AM64X_IOPAD(0x0034, PIN_OUTPUT, 7) /* (K17) GPIO0_13 */ -+ AM64X_IOPAD(0x0038, PIN_OUTPUT, 7) /* (L17) GPIO0_14 */ -+ -+ AM64X_IOPAD(0x0014, PIN_OUTPUT, 7) /* (M20) GPIO0_5 */ -+ AM64X_IOPAD(0x0018, PIN_OUTPUT, 7) /* (M21) GPIO0_6 */ -+ AM64X_IOPAD(0x001c, PIN_OUTPUT, 7) /* (P21) GPIO0_7 */ -+ AM64X_IOPAD(0x0020, PIN_OUTPUT, 7) /* (P20) GPIO0_8 */ -+ AM64X_IOPAD(0x0024, PIN_OUTPUT, 7) /* (N18) GPIO0_9 */ -+ AM64X_IOPAD(0x0028, PIN_OUTPUT, 7) /* (M17) GPIO0_10 */ -+ -+ >; -+ }; -+ -+ gpio1_pins: gpio1-pins { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ -+ AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ -+ >; -+ }; -+ -+ main_i2c2_pins_default: main-i2c2-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x00B0, PIN_INPUT, 1) /* (P19) I2C2_SCL */ -+ AM64X_IOPAD(0x00B4, PIN_INPUT, 1) /* (R21) I2C2_SDA */ -+ >; -+ }; -+ -+ rmii1_pins_default: rmii1-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x01cc, PIN_INPUT, 5) /* (W5) PRG0_PRU1_GPO7.RMII1_RD0 */ -+ AM64X_IOPAD(0x01d4, PIN_INPUT, 5) /* (Y5) PRG0_PRU1_GPO9.RMII1_RD1 */ -+ AM64X_IOPAD(0x01d8, PIN_OUTPUT, 5) /* (V6) PRG0_PRU1_GPO10.RMII1_TD0 */ -+ AM64X_IOPAD(0x01f4, PIN_OUTPUT, 5) /* (V5) PRG0_PRU1_GPO17.RMII1_TD1 */ -+ AM64X_IOPAD(0x01fc, PIN_INPUT, 5) /* (R2) PRG0_PRU1_GPO17.RMII1_CRS_DV*/ -+ AM64X_IOPAD(0x01f8, PIN_INPUT, 5) /* (P5) PRG0_PRU1_GPO17.RMII1_TX_EN */ -+ AM64X_IOPAD(0x0188, PIN_INPUT, 5) /* (AA5) PRG0_PRU0_GPO10.RMII1_REF_CLK*/ -+ AM64X_IOPAD(0x00d4, PIN_OUTPUT, 5) /* (U13) CLKOUT0 */ -+ >; -+ }; -+ -+ mdio0_pins_default: mdio0-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x015c, PIN_OUTPUT_PULLUP, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */ -+ AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */ -+ -+ AM64X_IOPAD(0x01ac, PIN_OUTPUT_PULLUP, 7) /* (W1) GPIO1_19 */ -+ >; -+ }; -+ -+ main_usb0_pins_default: main-usb0-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ -+ >; -+ }; -+ -+ main_i2c1_pins_default: main-i2c1-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ -+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ -+ >; -+ }; -+ -+ -+ main_i2c0_pins_default: main-i2c0-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (P19) I2C2_SCL */ -+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (R21) I2C2_SDA */ -+ >; -+ }; -+}; -+ -+&usbss0 { -+ ti,vbus-divider; -+ ti,usb2-only; -+}; -+ -+&usb0 { -+ dr_mode = "otg"; -+ maximum-speed = "high-speed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_usb0_pins_default>; -+}; -+ -+&main_i2c0 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_i2c0_pins_default>; -+ clock-frequency = <100000>; -+ -+ da9063: pmic@58 { -+ compatible = "dlg,da9063"; -+ reg = <0x58>; -+ -+ regulators { -+ vddcore_reg: bcore1 { -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-ramp-delay = <2>; -+ regulator-name = "DA9063_CORE"; -+ regulator-always-on; -+ }; -+ -+ vddar_reg: bcore2 { -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-ramp-delay = <2>; -+ regulator-name = "DA9063_AR"; -+ regulator-always-on; -+ }; -+ -+ vdd_1v8_reg: bperi { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <2>; -+ regulator-always-on; -+ }; -+ -+ vdd_3v3_1_reg: bio { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vdd_3v3_2_reg: bmem { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vdd_1v1_reg: bpro { -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-always-on; -+ }; -+ -+ vdd_gnss_reg: ldo3 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vdd_sensors_reg: ldo5 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ vdd_stby_reg: ldo6 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vdd_vdda: ldo10 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vdd_5v_can_reg: ldo11 { -+ /* It is actually 5V but the driver does not support it */ -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+/* SYS_I2C */ -+&main_i2c1 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_i2c1_pins_default>; -+ clock-frequency = <400000>; -+ -+ /* There is no driver available */ -+ onewire: ds2484@18 { -+ status = "disabled"; -+ reg = <0x18>; -+ }; -+ -+ eeprom: eeprom@50 { -+ reg = <0x50>; -+ compatible = "onsemi,24c64"; -+ }; -+ -+ temp: temp@48 { -+ reg = <0x48>; -+ compatible = "national,lm75"; -+ /* vs-supply = <&vs>; */ /* Not available, maybe required then use fixed-regulator */ -+ }; -+}; -+ -+/* USER_I2C */ -+&main_i2c2 { -+ status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_i2c2_pins_default>; -+ clock-frequency = <400000>; -+ -+ exp1: gpio@71 { -+ status = "okay"; -+ compatible = "nxp,pca9538"; -+ reg = <0x71>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "GPI_CTRL_PU_EN0", "GPI_CTRL_PU_EN1", -+ "GPI_CTRL_PU_EN2", "GPI_CTRL_PU_EN3", -+ "GPI_CTRL_PU_EN4", "GPI_CTRL_PU_EN5", -+ "", ""; -+ }; -+ -+ exp2: gpio@72 { -+ status = "okay"; -+ compatible = "nxp,pca9538"; -+ reg = <0x73>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "GPIO0", "GPIO1", -+ "GPIO2", "GPIO3", -+ "GPO0", "GPO1", -+ "GPO2", "GPO3"; -+ }; -+}; -+ -+&sdhci0 { -+ /* emmc */ -+ bus-width = <8>; -+ non-removable; -+ ti,driver-strength-ohm = <50>; -+ disable-wp; -+ /delete-property/ ti,otap-del-sel-hs200; -+ /delete-property/ ti,otap-del-sel-hs400; -+}; -+ -+&sdhci1 { -+ status = "disabled"; -+ pinctrl-names = "default"; -+ bus-width = <4>; -+ pinctrl-0 = <&main_mmc1_pins_default>; -+ ti,driver-strength-ohm = <50>; -+ disable-wp; -+ broken-cd; -+ /delete-property/ ti,otap-del-sel-hs200; -+ /delete-property/ ti,otap-del-sel-hs400; -+}; -+ -+&cpsw3g { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mdio0_pins_default -+ &rmii1_pins_default>; -+}; -+ -+&cpsw_port1 { -+ phy-mode = "rmii"; -+ phy-handle = <&cpsw3g_phy0>; -+}; -+ -+&cpsw3g_mdio { -+ bus_freq = <100000>; -+ cpsw3g_phy0: ethernet-phy@b1 { -+ reg = <0x01>; -+ ti,rx-internal-delay = ; -+ ti,fifo-depth = ; -+ }; -+}; -+ -+&main_gpio0 { -+ status = "okay"; -+ ti,ngpio = <87>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpio0_pins>; -+ -+ wlan_en { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "WLAN_EN"; -+ }; -+ -+ canfd0_en { -+ gpio-hog; -+ gpios = <74 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "CANFD0_CTRL_EN"; -+ }; -+ -+ canfd1_en { -+ gpio-hog; -+ gpios = <72 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "CANFD1_CTRL_EN"; -+ }; -+ -+ canfd0_stb { -+ gpio-hog; -+ gpios = <55 GPIO_ACTIVE_HIGH>; -+ output-low; -+ /* In V1 this is high active even though it is STB~ */ -+ line-name = "CANFD0_CTRL_STB"; -+ }; -+ -+ canfd1_stb { -+ gpio-hog; -+ gpios = <54 GPIO_ACTIVE_HIGH>; -+ output-low; -+ /* In V1 this is high active even though it is STB~ */ -+ line-name = "CANFD1_CTRL_STB"; -+ }; -+ -+ xpdr_rst { -+ gpio-hog; -+ gpios = <34 GPIO_ACTIVE_LOW>; -+ output-low; -+ line-name = "XPDR_RST"; -+ }; -+ -+ hub_rst { -+ gpio-hog; -+ gpios = <19 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "HUB_RST"; -+ }; -+ -+ gnss_rst { -+ gpio-hog; -+ gpios = <39 GPIO_ACTIVE_HIGH>; -+ output-low; -+ line-name = "GNSS_RST"; -+ }; -+}; -+ -+&main_gpio1 { -+ status = "okay"; -+ ti,ngpio = <88>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpio1_pins>; -+ -+ brdr_rst { -+ gpio-hog; -+ gpios = <18 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "BRDR_RST"; -+ }; -+ -+ eth_rst { -+ gpio-hog; -+ gpios = <19 GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "ETH_RST"; -+ }; -+}; -+ -+#include "k3-am642-gemini-u-boot.dtsi" -diff --git a/arch/arm/dts/k3-am642-r5-netmodule-hw34.dts b/arch/arm/dts/k3-am642-r5-netmodule-hw34.dts -new file mode 100644 -index 0000000000..a199dd8069 ---- /dev/null -+++ b/arch/arm/dts/k3-am642-r5-netmodule-hw34.dts -@@ -0,0 +1,226 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -+ */ -+ -+/dts-v1/; -+ -+#include "k3-am642.dtsi" -+#include "k3-am64-sk-lp4-1600MTs.dtsi" -+#include "k3-am64-ddr.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ tick-timer = &timer1; -+ }; -+ -+ aliases { -+ remoteproc0 = &sysctrler; -+ remoteproc1 = &a53_0; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ /* 1G RAM */ -+ reg = <0x00000000 0x80000000 0x00000000 0x40000000>; -+ -+ u-boot,dm-spl; -+ }; -+ -+ a53_0: a53@0 { -+ compatible = "ti,am654-rproc"; -+ reg = <0x00 0x00a90000 0x00 0x10>; -+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, -+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; -+ resets = <&k3_reset 135 0>; -+ clocks = <&k3_clks 61 0>; -+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; -+ assigned-clock-parents = <&k3_clks 61 2>; -+ assigned-clock-rates = <200000000>, <1000000000>; -+ ti,sci = <&dmsc>; -+ ti,sci-proc-id = <32>; -+ ti,sci-host-id = <10>; -+ u-boot,dm-spl; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ secure_ddr: optee@9e800000 { -+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ -+ alignment = <0x1000>; -+ no-map; -+ }; -+ }; -+ -+ clk_200mhz: dummy-clock-200mhz { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ u-boot,dm-spl; -+ }; -+}; -+ -+&cbass_main { -+ sysctrler: sysctrler { -+ compatible = "ti,am654-system-controller"; -+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; -+ mbox-names = "tx", "rx"; -+ u-boot,dm-spl; -+ }; -+}; -+ -+&cbass_main { -+ main_esm: esm@420000 { -+ compatible = "ti,j721e-esm"; -+ reg = <0x0 0x420000 0x0 0x1000>; -+ ti,esm-pins = <160>, <161>; -+ u-boot,dm-spl; -+ }; -+}; -+ -+&cbass_mcu { -+ u-boot,dm-spl; -+ mcu_esm: esm@4100000 { -+ compatible = "ti,j721e-esm"; -+ reg = <0x0 0x4100000 0x0 0x1000>; -+ ti,esm-pins = <0>, <1>; -+ u-boot,dm-spl; -+ }; -+}; -+ -+&main_pmx0 { -+ u-boot,dm-spl; -+ main_uart0_pins_default: main-uart0-pins-default { -+ u-boot,dm-spl; -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ -+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ -+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ -+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ -+ >; -+ }; -+ -+ main_mmc0_pins_default: main-mmc0-pins-default { -+ u-boot,dm-spl; -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ -+ AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ -+ AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ -+ AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ -+ AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ -+ AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ -+ AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ -+ AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ -+ AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ -+ AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ -+ AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ -+ >; -+ }; -+ -+ main_mmc1_pins_default: main-mmc1-pins-default { -+ u-boot,dm-spl; -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ -+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ -+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ -+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ -+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ -+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ -+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ -+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ -+ >; -+ }; -+ -+ -+ main_usb0_pins_default: main-usb0-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ -+ >; -+ }; -+ -+ ospi0_pins_default: ospi0-pins-default { -+ pinctrl-single,pins = < -+ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ -+ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ -+ AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ -+ AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ -+ AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ -+ AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ -+ AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ -+ AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ -+ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ -+ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ -+ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ -+ >; -+ }; -+}; -+ -+&dmsc { -+ mboxes= <&secure_proxy_main 0>, -+ <&secure_proxy_main 1>, -+ <&secure_proxy_main 0>; -+ mbox-names = "rx", "tx", "notify"; -+ ti,host-id = <35>; -+ ti,secure-host; -+}; -+ -+&main_uart0 { -+ /delete-property/ power-domains; -+ /delete-property/ clocks; -+ /delete-property/ clock-names; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_uart0_pins_default>; -+ status = "okay"; -+}; -+ -+&sdhci0 { -+ /delete-property/ power-domains; -+ clocks = <&clk_200mhz>; -+ clock-names = "clk_xin"; -+ ti,driver-strength-ohm = <50>; -+ disable-wp; -+ pinctrl-0 = <&main_mmc0_pins_default>; -+ /delete-property/ ti,otap-del-sel-hs200; -+ /delete-property/ ti,otap-del-sel-hs400; -+}; -+ -+&sdhci1 { -+ /delete-property/ power-domains; -+ clocks = <&clk_200mhz>; -+ clock-names = "clk_xin"; -+ ti,driver-strength-ohm = <50>; -+ disable-wp; -+ pinctrl-0 = <&main_mmc1_pins_default>; -+}; -+ -+&main_gpio0 { -+ u-boot,dm-spl; -+ /delete-property/ power-domains; -+}; -+ -+&usbss0 { -+ ti,vbus-divider; -+ ti,usb2-only; -+}; -+ -+&usb0 { -+ dr_mode = "otg"; -+ maximum-speed = "high-speed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&main_usb0_pins_default>; -+}; -+ -+/* EEPROM might be read before SYSFW is available */ -+&main_i2c0 { -+ /delete-property/ power-domains; -+}; -+ -+&memorycontroller { -+// ti,ddr-freq0 = <200000000>; -+}; -+ -+#include "k3-am642-gemini-u-boot.dtsi" -diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig -index 171a7f2f25..694cf5da41 100644 ---- a/arch/arm/mach-k3/Kconfig -+++ b/arch/arm/mach-k3/Kconfig -@@ -188,4 +188,6 @@ source "board/ti/am62x/Kconfig" - source "board/ti/j721e/Kconfig" - source "board/siemens/iot2050/Kconfig" - source "board/ti/j721s2/Kconfig" -+ -+source "board/nm/am64x/Kconfig" - endif -diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c -index 227706e8dc..8530416cec 100644 ---- a/arch/arm/mach-k3/common.c -+++ b/arch/arm/mach-k3/common.c -@@ -138,6 +138,11 @@ void init_env(void) - env_init(); - env_relocate(); - switch (spl_boot_device()) { -+ case BOOT_DEVICE_MMC1: -+ part = env_get("bootpart"); -+ env_set("storage_interface", "mmc"); -+ env_set("fw_dev_part", part); -+ break; - case BOOT_DEVICE_MMC2: - part = env_get("bootpart"); - env_set("storage_interface", "mmc"); -diff --git a/board/nm/am64x/Kconfig b/board/nm/am64x/Kconfig -new file mode 100644 -index 0000000000..bee565988a ---- /dev/null -+++ b/board/nm/am64x/Kconfig -@@ -0,0 +1,60 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -+ -+choice -+ prompt "NetModule boards" -+ optional -+ -+config TARGET_AM642_A53_GEMINI -+ bool "TI K3 based AM642 Gemini Board from NetModule for A53" -+ select ARM64 -+ select SOC_K3_AM642 -+ select BINMAN -+ imply BOARD -+ imply SPL_BOARD -+ -+config TARGET_AM642_R5_GEMINI -+ bool "TI K3 based AM642 Gemini Board from NetModule for R5" -+ select CPU_V7R -+ select SYS_THUMB_BUILD -+ select K3_LOAD_SYSFW -+ select SOC_K3_AM642 -+ select RAM -+ select SPL_RAM -+ select K3_DDRSS -+ imply SYS_K3_SPL_ATF -+endchoice -+ -+if TARGET_AM642_A53_GEMINI -+ -+config SYS_BOARD -+ default "am64x" -+ -+config SYS_VENDOR -+ default "nm" -+ -+config SYS_CONFIG_NAME -+ default "am64x_gemini" -+ -+source "board/ti/common/Kconfig" -+ -+endif -+ -+if TARGET_AM642_R5_GEMINI -+ -+config SYS_BOARD -+ default "am64x" -+ -+config SYS_VENDOR -+ default "nm" -+ -+config SYS_CONFIG_NAME -+ default "am64x_gemini" -+ -+config SPL_LDSCRIPT -+ default "arch/arm/mach-omap2/u-boot-spl.lds" -+ -+source "board/ti/common/Kconfig" -+ -+endif -diff --git a/board/nm/am64x/Makefile b/board/nm/am64x/Makefile -new file mode 100644 -index 0000000000..8a8a4158a2 ---- /dev/null -+++ b/board/nm/am64x/Makefile -@@ -0,0 +1,9 @@ -+# -+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -+# Keerthy -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += gemini.o -+obj-$(CONFIG_TARGET_AM642_A53_GEMINI) += sysreset.o -diff --git a/board/nm/am64x/gemini.c b/board/nm/am64x/gemini.c -new file mode 100644 -index 0000000000..f076b9fb0e ---- /dev/null -+++ b/board/nm/am64x/gemini.c -@@ -0,0 +1,166 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Board specific initialization for AM642 EVM -+ * -+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ -+ * Keerthy -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int board_init(void) -+{ -+ return 0; -+} -+ -+int dram_init(void) -+{ -+ s32 ret; -+ -+ ret = fdtdec_setup_mem_size_base(); -+ if (ret) -+ printf("Error setting up mem size and base. %d\n", ret); -+ -+ return ret; -+} -+ -+int dram_init_banksize(void) -+{ -+ s32 ret; -+ -+ ret = fdtdec_setup_memory_banksize(); -+ if (ret) -+ printf("Error setting up memory banksize. %d\n", ret); -+ -+ return ret; -+} -+#ifdef CONFIG_SPL_LOAD_FIT -+int board_fit_config_name_match(const char *name) -+{ -+ return 0; -+} -+#endif -+ -+#if defined(CONFIG_SPL_BUILD) -+#if CONFIG_IS_ENABLED(USB_STORAGE) -+static int fixup_usb_boot(const void *fdt_blob) -+{ -+ int ret = 0; -+ -+ switch (spl_boot_device()) { -+ case BOOT_DEVICE_USB: -+ /* -+ * If the boot mode is host, fixup the dr_mode to host -+ * before cdns3 bind takes place -+ */ -+ ret = fdt_find_and_setprop((void *)fdt_blob, -+ "/bus@f4000/cdns-usb@f900000/usb@f400000", -+ "dr_mode", "host", 5, 0); -+ if (ret) -+ printf("%s: fdt_find_and_setprop() failed:%d\n", -+ __func__, ret); -+ fallthrough; -+ default: -+ break; -+ } -+ -+ return ret; -+} -+#endif -+ -+#if defined(CONFIG_K3_AM64_DDRSS) -+static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) -+{ -+ struct udevice *dev; -+ int ret; -+ -+ dram_init_banksize(); -+ -+ ret = uclass_get_device(UCLASS_RAM, 0, &dev); -+ if (ret) -+ panic("Cannot get RAM device for ddr size fixup: %d\n", ret); -+ -+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); -+ if (ret) -+ printf("Error fixing up ddr node for ECC use! %d\n", ret); -+} -+#else -+static void fixup_memory_node(struct spl_image_info *spl_image) -+{ -+ u64 start[CONFIG_NR_DRAM_BANKS]; -+ u64 size[CONFIG_NR_DRAM_BANKS]; -+ int bank; -+ int ret; -+ -+ dram_init(); -+ dram_init_banksize(); -+ -+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { -+ start[bank] = gd->bd->bi_dram[bank].start; -+ size[bank] = gd->bd->bi_dram[bank].size; -+ } -+ -+ /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ -+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); -+ if (ret) -+ printf("Error fixing up memory node! %d\n", ret); -+} -+#endif -+ -+void spl_perform_fixups(struct spl_image_info *spl_image) -+{ -+#if defined(CONFIG_K3_AM64_DDRSS) -+ fixup_ddr_driver_for_ecc(spl_image); -+#else -+ fixup_memory_node(spl_image); -+#endif -+ -+#if CONFIG_IS_ENABLED(USB_STORAGE) -+ fixup_usb_boot(spl_image->fdt_addr); -+#endif -+} -+#endif -+ -+int checkboard(void) -+{ -+ printf("Board: GEMINI rev 1\n"); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_BOARD_LATE_INIT -+int board_late_init(void) -+{ -+ return 0; -+} -+#endif -+ -+#define CTRLMMR_USB0_PHY_CTRL 0x43004008 -+#define CORE_VOLTAGE 0x80000000 -+ -+#ifdef CONFIG_SPL_BOARD_INIT -+void spl_board_init(void) -+{ -+ u32 val; -+ /* Set USB PHY core voltage to 0.85V */ -+ val = readl(CTRLMMR_USB0_PHY_CTRL); -+ val &= ~(CORE_VOLTAGE); -+ writel(val, CTRLMMR_USB0_PHY_CTRL); -+ -+ /* Init DRAM size for R5/A53 SPL */ -+ dram_init_banksize(); -+} -+#endif -diff --git a/board/nm/am64x/sysreset.c b/board/nm/am64x/sysreset.c -new file mode 100644 -index 0000000000..7e0b859ab3 ---- /dev/null -+++ b/board/nm/am64x/sysreset.c -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct gemini_sysreset_data { -+ struct udevice *pmic; -+}; -+ -+static int gemini_sysreset_probe(struct udevice *dev) -+{ -+ struct gemini_sysreset_data *data = dev_get_priv(dev); -+ int ret; -+ -+ debug("%s(dev=%p)\n", __func__, dev); -+ -+ if (!data) -+ return -ENOMEM; -+ -+ ret = pmic_get("pmic@58", &data->pmic); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int gemini_sysreset_request(struct udevice *dev, enum sysreset_t type) -+{ -+ struct gemini_sysreset_data *data = dev_get_priv(dev); -+ -+ debug("Reset PMIC DA9063 %p\n", data->pmic); -+ -+ pmic_reg_write(data->pmic, 0x13, 0x7); -+ -+ return 0; -+} -+ -+static struct sysreset_ops gemini_sysreset_ops = { -+ .request = gemini_sysreset_request, -+}; -+ -+static const struct udevice_id gemini_sysreset_of_match[] = { -+ { .compatible = "gemini-sysreset", }, -+ { /* sentinel */ }, -+}; -+ -+ -+U_BOOT_DRIVER(gemini_sysreset) = { -+ .name = "gemini-sysreset", -+ .id = UCLASS_SYSRESET, -+ .of_match = gemini_sysreset_of_match, -+ .probe = gemini_sysreset_probe, -+ .priv_auto = sizeof(struct gemini_sysreset_data), -+ .ops = &gemini_sysreset_ops, -+}; -diff --git a/configs/am64x_netmodule_hw34_a53_defconfig b/configs/am64x_netmodule_hw34_a53_defconfig -new file mode 100644 -index 0000000000..acf5a340dc ---- /dev/null -+++ b/configs/am64x_netmodule_hw34_a53_defconfig -@@ -0,0 +1,179 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_K3=y -+CONFIG_SYS_MALLOC_LEN=0x2000000 -+CONFIG_SYS_MALLOC_F_LEN=0x8000 -+CONFIG_SPL_GPIO=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_SOC_K3_AM642=y -+CONFIG_K3_ATF_LOAD_ADDR=0x701c0000 -+CONFIG_TARGET_AM642_A53_GEMINI=y -+CONFIG_ENV_SIZE=0x20000 -+CONFIG_ENV_OFFSET=0x3e0000 -+CONFIG_DM_GPIO=y -+CONFIG_SPL_DM_SPI=y -+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-netmodule-hw34" -+CONFIG_SPL_TEXT_BASE=0x80080000 -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_DRIVERS_MISC=y -+CONFIG_SPL_STACK_R_ADDR=0x82000000 -+CONFIG_SPL_FS_FAT=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI=y -+CONFIG_DISTRO_DEFAULTS=y -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 -+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 -+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y -+CONFIG_BOOTCOMMAND="run distro_bootcmd" -+CONFIG_BOARD_LATE_INIT=y -+CONFIG_SPL_MAX_SIZE=0x180000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x80a00000 -+CONFIG_SPL_BSS_MAX_SIZE=0x80000 -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x180000 -+CONFIG_SYS_SPL_MALLOC=y -+CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1600 -+CONFIG_SPL_DMA=y -+CONFIG_SPL_ENV_SUPPORT=y -+CONFIG_SPL_ETH=y -+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -+CONFIG_SPL_I2C=y -+CONFIG_SPL_DM_MAILBOX=y -+CONFIG_SPL_DM_SPI_FLASH=y -+CONFIG_SPL_NET=y -+CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" -+CONFIG_SPL_POWER_DOMAIN=y -+CONFIG_SPL_RAM_SUPPORT=y -+CONFIG_SPL_RAM_DEVICE=y -+CONFIG_SPL_SPI_LOAD=y -+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -+CONFIG_SPL_USB_HOST=y -+CONFIG_SPL_USB_STORAGE=y -+CONFIG_SPL_USB_GADGET=y -+CONFIG_SPL_DFU=y -+CONFIG_SPL_YMODEM_SUPPORT=y -+CONFIG_SYS_MAXARGS=64 -+CONFIG_SYS_BOOTM_LEN=0x800000 -+CONFIG_CMD_ASKENV=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_DFU=y -+CONFIG_CMD_DM=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_TIME=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+CONFIG_OF_CONTROL=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_MULTI_DTB_FIT=y -+CONFIG_SPL_MULTI_DTB_FIT=y -+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_MMC_ENV_PART=1 -+CONFIG_SPL_ENV_IS_NOWHERE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM=y -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_OF_TRANSLATE=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_SPL_CLK_CCF=y -+CONFIG_CLK_CCF=y -+CONFIG_CLK_TI_SCI=y -+CONFIG_DFU_MMC=y -+CONFIG_DFU_RAM=y -+CONFIG_DFU_SF=y -+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 -+CONFIG_DMA_CHANNELS=y -+CONFIG_TI_K3_NAVSS_UDMA=y -+CONFIG_TI_SCI_PROTOCOL=y -+CONFIG_GPIO_HOG=y -+CONFIG_DA8XX_GPIO=y -+CONFIG_DM_PCA953X=y -+CONFIG_DM_I2C=y -+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y -+CONFIG_DM_I2C_GPIO=y -+CONFIG_SYS_I2C_OMAP24XX=y -+CONFIG_DM_MAILBOX=y -+CONFIG_K3_SEC_PROXY=y -+CONFIG_SUPPORT_EMMC_BOOT=y -+CONFIG_MMC_HS400_SUPPORT=y -+CONFIG_SPL_MMC_HS400_SUPPORT=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ADMA=y -+CONFIG_SPL_MMC_SDHCI_ADMA=y -+CONFIG_MMC_SDHCI_AM654=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_MULTIPLEXER=y -+CONFIG_MUX_MMIO=y -+CONFIG_PHY_TI_DP83867=y -+CONFIG_PHY_FIXED=y -+CONFIG_TI_AM65_CPSW_NUSS=y -+CONFIG_PHY=y -+CONFIG_SPL_PHY=y -+CONFIG_PHY_CADENCE_SIERRA=y -+CONFIG_PHY_CADENCE_TORRENT=y -+CONFIG_PHY_J721E_WIZ=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_TI_SCI_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_DM_PMIC_DA9063=y -+CONFIG_DM_REGULATOR=y -+CONFIG_K3_SYSTEM_CONTROLLER=y -+CONFIG_REMOTEPROC_TI_K3_ARM64=y -+CONFIG_DM_RESET=y -+CONFIG_RESET_TI_SCI=y -+CONFIG_DM_SERIAL=y -+CONFIG_SOC_DEVICE=y -+CONFIG_SOC_DEVICE_TI_K3=y -+CONFIG_SOC_TI=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_CADENCE_QSPI=y -+CONFIG_SYSRESET=y -+CONFIG_SPL_SYSRESET=y -+CONFIG_SYSRESET_TI_SCI=y -+CONFIG_DM_THERMAL=y -+CONFIG_USB=y -+CONFIG_DM_USB_GADGET=y -+CONFIG_SPL_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_SPL_USB_CDNS3_GADGET=y -+CONFIG_SPL_USB_CDNS3_HOST=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -+CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_FUNCTION_MASS_STORAGE=y -+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -+CONFIG_LZO=y -+CONFIG_HEXDUMP=y -diff --git a/configs/am64x_netmodule_hw34_r5_defconfig b/configs/am64x_netmodule_hw34_r5_defconfig -new file mode 100644 -index 0000000000..c7e66a18e8 ---- /dev/null -+++ b/configs/am64x_netmodule_hw34_r5_defconfig -@@ -0,0 +1,170 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_K3=y -+CONFIG_SYS_MALLOC_LEN=0x2000000 -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_GPIO=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_SOC_K3_AM642=y -+CONFIG_TARGET_AM642_R5_GEMINI=y -+CONFIG_DM_GPIO=y -+CONFIG_SPL_DM_SPI=y -+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-netmodule-hw34" -+CONFIG_SPL_TEXT_BASE=0x70000000 -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_DRIVERS_MISC=y -+CONFIG_SPL_STACK_R_ADDR=0x82000000 -+CONFIG_SPL_SIZE_LIMIT=0x190000 -+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 -+CONFIG_SPL_FS_FAT=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI=y -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800 -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 -+CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y -+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y -+CONFIG_SPL_MAX_SIZE=0x180000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x7019b800 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_SPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_SPL_MALLOC=y -+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 -+CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 -+CONFIG_SPL_EARLY_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x600 -+CONFIG_SPL_DMA=y -+CONFIG_SPL_I2C=y -+CONFIG_SPL_DM_MAILBOX=y -+CONFIG_SPL_DM_SPI_FLASH=y -+CONFIG_SPL_NET=y -+CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_POWER_DOMAIN=y -+CONFIG_SPL_RAM_SUPPORT=y -+CONFIG_SPL_RAM_DEVICE=y -+CONFIG_SPL_REMOTEPROC=y -+CONFIG_SPL_SPI_LOAD=y -+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -+CONFIG_SPL_USB_HOST=y -+CONFIG_SPL_USB_STORAGE=y -+CONFIG_SPL_THERMAL=y -+CONFIG_SPL_USB_GADGET=y -+CONFIG_SPL_DFU=y -+CONFIG_SPL_YMODEM_SUPPORT=y -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_MAXARGS=64 -+CONFIG_CMD_DFU=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_REMOTEPROC=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_DHCP=y -+CONFIG_CMD_TIME=y -+CONFIG_CMD_FAT=y -+CONFIG_OF_CONTROL=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_MULTI_DTB_FIT=y -+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -+CONFIG_SPL_ENV_SUPPORT=y -+CONFIG_ENV_IS_NOWHERE=y -+CONFIG_SPL_DM=y -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_OF_TRANSLATE=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_SPL_CLK_CCF=y -+CONFIG_CLK_CCF=y -+CONFIG_CLK_TI_SCI=y -+CONFIG_DFU_MMC=y -+CONFIG_DFU_RAM=y -+CONFIG_DFU_SF=y -+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 -+CONFIG_DMA_CHANNELS=y -+CONFIG_TI_K3_NAVSS_UDMA=y -+CONFIG_TI_SCI_PROTOCOL=y -+CONFIG_DA8XX_GPIO=y -+CONFIG_DM_I2C=y -+CONFIG_SYS_I2C_OMAP24XX=y -+CONFIG_DM_MAILBOX=y -+CONFIG_K3_SEC_PROXY=y -+CONFIG_ESM_K3=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ADMA=y -+CONFIG_SPL_MMC_SDHCI_ADMA=y -+CONFIG_MMC_SDHCI_AM654=y -+CONFIG_DM_SPI_FLASH=y -+CONFIG_SPI_FLASH_SPANSION=y -+CONFIG_SPI_FLASH_STMICRO=y -+CONFIG_PHY_TI_DP83867=y -+CONFIG_TI_AM65_CPSW_NUSS=y -+CONFIG_PHY=y -+CONFIG_SPL_PHY=y -+CONFIG_PHY_CADENCE_SIERRA=y -+CONFIG_PHY_CADENCE_TORRENT=y -+CONFIG_PHY_J721E_WIZ=y -+CONFIG_PINCTRL=y -+# CONFIG_PINCTRL_GENERIC is not set -+CONFIG_SPL_PINCTRL=y -+# CONFIG_SPL_PINCTRL_GENERIC is not set -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_TI_SCI_POWER_DOMAIN=y -+CONFIG_DM_REGULATOR=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_SPL_DM_REGULATOR_GPIO=y -+CONFIG_K3_SYSTEM_CONTROLLER=y -+CONFIG_REMOTEPROC_TI_K3_ARM64=y -+CONFIG_DM_RESET=y -+CONFIG_RESET_TI_SCI=y -+CONFIG_SPECIFY_CONSOLE_INDEX=y -+CONFIG_DM_SERIAL=y -+CONFIG_SOC_DEVICE=y -+CONFIG_SOC_DEVICE_TI_K3=y -+CONFIG_SOC_TI=y -+CONFIG_SPI=y -+CONFIG_DM_SPI=y -+CONFIG_CADENCE_QSPI=y -+CONFIG_DM_THERMAL=y -+CONFIG_TIMER=y -+CONFIG_SPL_TIMER=y -+CONFIG_OMAP_TIMER=y -+CONFIG_USB=y -+CONFIG_DM_USB=y -+CONFIG_DM_USB_GADGET=y -+CONFIG_SPL_DM_USB_GADGET=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_CDNS3=y -+CONFIG_USB_CDNS3_GADGET=y -+CONFIG_USB_CDNS3_HOST=y -+CONFIG_SPL_USB_CDNS3_GADGET=y -+CONFIG_SPL_USB_CDNS3_HOST=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -+CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 -diff --git a/include/configs/am64x_gemini.h b/include/configs/am64x_gemini.h -new file mode 100644 -index 0000000000..09723e6a29 ---- /dev/null -+++ b/include/configs/am64x_gemini.h -@@ -0,0 +1,61 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Configuration header file for K3 AM642 SoC family -+ * -+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -+ * Keerthy -+ */ -+ -+#ifndef __CONFIG_AM642_EVM_H -+#define __CONFIG_AM642_EVM_H -+ -+#include -+#include -+#include -+#include -+ -+/* Add support for distro boot */ -+#if defined(CONFIG_DISTRO_DEFAULTS) -+#define BOOT_TARGET_DEVICES(func) \ -+ func(MMC, mmc, CONFIG_SYS_MMC_ENV_DEV) -+ -+#include -+#else -+#define BOOTENV "" -+#endif -+ -+/* DDR Configuration */ -+#define CONFIG_SYS_SDRAM_BASE1 0x880000000 -+ -+#ifdef CONFIG_SYS_K3_SPL_ATF -+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -+#endif -+ -+/* Configure R5 SPL post-relocation malloc pool in DDR */ -+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -+#endif -+ -+/* Allow a simple U-Boot update */ -+#define UPDATE_UBOOT_CMD \ -+ "update_uboot=setenv ipaddr 192.168.1.1 && setenv serverip 192.168.1.254 && mmc dev 0 1 && " \ -+ "tftp $loadaddr gemini/tiboot3.bin && mmc write $loadaddr 0 0x600 && " \ -+ "tftp $loadaddr gemini/tispl.bin && mmc write ${loadaddr} 0x600 0x800 && " \ -+ "tftp $loadaddr gemini/u-boot.img && mmc write ${loadaddr} 0x1600 0x800;\0" -+ -+#define EXTRA_ENV_DFUARGS \ -+ DFU_ALT_INFO_MMC \ -+ DFU_ALT_INFO_EMMC \ -+ DFU_ALT_INFO_RAM -+ -+/* Incorporate settings into the U-Boot environment */ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ BOOTENV \ -+ UPDATE_UBOOT_CMD \ -+ DEFAULT_LINUX_BOOT_ENV \ -+ DEFAULT_FIT_TI_ARGS \ -+ DEFAULT_MMC_TI_ARGS \ -+ EXTRA_ENV_DFUARGS -+ -+/* Now for the remaining common defines */ -+#include -+ diff --git a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.01.bb b/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.04.bb similarity index 51% rename from layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.01.bb rename to layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.04.bb index a3df4e9..9180248 100644 --- a/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.01.bb +++ b/layers/meta-netmodule-coreos-bsp/recipes-bsp/u-boot/u-boot-ti-coreos_2023.04.bb @@ -5,22 +5,14 @@ SPL_UART_BINARY:netmodule-hw34-k3r5 = "u-boot-spl.bin" LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1" -PV = "2023.01" +PV = "2023.04" -SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master \ - file://0001-ram-k3-ddrss-Fix-a-ddr4-controller-stall.patch \ - file://0002-gemini-board-add-board-and-device-tree.patch \ +SRC_URI = "git://bitbucket.gad.local:7999/nm-nsp/netmodule-u-boot.git;protocol=ssh;user=git;branch=gemini/ti/ti-u-boot-2023.04 \ " - -SRCREV = "62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9" +SRCREV = "34cf1e583eb263dd6644d0ebf3468b3846fc0925" PACKAGECONFIG[atf] = "BL31=${STAGING_DIR_HOST}/firmware/bl31.bin,,trusted-firmware-a" -do_deploy:append:netmodule-hw34-k3r5 () { - mv ${DEPLOYDIR}/tiboot3.bin ${DEPLOYDIR}/tiboot3-r5spl.bin || true - mv ${DEPLOYDIR}/u-boot-spl.bin ${DEPLOYDIR}/u-boot-spl-r5spl.bin || true -} - # Only require coreos include file for the aarch64 build of u-boot UBOOT_REQUIRE ?= "" UBOOT_REQUIRE:netmodule-hw34 = "recipes-bsp/u-boot/u-boot-coreos.inc"