fix(meta-belden-marvell-bsp): add cn913x additions config from solidrun repo. ath11 config enabled in this config by default, so we remove separate ath11 config fragment

* CP was not set correctly
* board config was wrong and changed cn9130 -> cn 9131

This commit needs rework. it is just a hotfix, to get stuff working.

layers/meta-belden-marvell-bsp/conf/machine/cn9130-bldn-mbv.conf

@@ -1,6 +0,0 @@
-#@TYPE: Machine
-#@NAME: cn9130-bldn-mbv
-#@DESCRIPTION: CN9130 SOM based on Bldn MBV-A/B
-#
-
-require conf/machine/include/cn913x.inc

layers/meta-belden-marvell-bsp/conf/machine/cn9130-cex7.conf

@@ -0,0 +1,8 @@
+#@TYPE: Machine
+#@NAME: cn9130
+#@DESCRIPTION: Machine support for Marvell Opteon TX2 CN9130.
+#
+
+require conf/machine/include/cn913x.inc
+
+UBOOT_BUILDENV_DEVICE_TREE ?= "cn9130-cex7-A"

layers/meta-belden-marvell-bsp/conf/machine/cn9131-bldn-mbv.conf

@@ -0,0 +1,6 @@
+#@TYPE: Machine
+#@NAME: cn9131-bldn-mbv
+#@DESCRIPTION: CN9131 SOM based on Bldn MBV-A/B
+#
+
+require conf/machine/include/cn913x.inc

layers/meta-belden-marvell-bsp/conf/machine/include/cn913x.inc

@@ -11,7 +11,7 @@ require conf/machine/include/soc-family.inc
 # *****************************************************************************
 
 PREFERRED_PROVIDER_virtual/bootloader = "u-boot"
-PREFERRED_VERSION_u-boot ?= "2023.04-marvell"
+PREFERRED_VERSION_u-boot ?= "2019.10-solidrun"
 
 # All cn913x use the same defconfig for u-boot, but another devicetree by
 # settings UBOOT_BUILDENV_DEVICE_TREE in the machine configuration file

layers/meta-belden-marvell-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.3-solidrun.bb

@@ -15,8 +15,8 @@ COMPATIBLE_MACHINE = "cn913x"
 
 DEPENDS += "mv-ddr-marvell coreutils-native"
 
-CP_NUM:cn9132 = "3"
-CP_NUM:cn9130 = "1"
+CP_NUM:cn9131-bldn-mbv = "2"
+CP_NUM:cn9130-cf-pro = "1"
 
 TFA_PLATFORM       = "t9130"
 TFA_BUILD_TARGET   = "all mrvl_flash"
@@ -27,4 +27,4 @@ TFA_UBOOT          = "1"
 TFA_UEFI           = "0"
 
 
-EXTRA_OEMAKE += "MV_DDR_PATH=${PKG_CONFIG_SYSROOT_DIR}/usr/src/mv-ddr-marvell CP_NUM=${CP_NUM} SCP_BL2=${WORKDIR}/mrvl_scp_bl2.img"
+EXTRA_OEMAKE += "USE_COHERENT_MEM=0 LOG_LEVEL=20 MV_DDR_PATH=${PKG_CONFIG_SYSROOT_DIR}/usr/src/mv-ddr-marvell CP_NUM=${CP_NUM} SCP_BL2=${WORKDIR}/mrvl_scp_bl2.img"

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch

@@ -0,0 +1,24 @@
+From 0e0801291261a2c1267a42905d647cc0d1140791 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Thu, 30 Jan 2020 09:37:15 +0000
+Subject: [PATCH] Remove redundant YYLOC global declaration
+
+Same as the upstream fix for building dtc with gcc 10.
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+---
+ scripts/dtc/dtc-lexer.l | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
+index fd825ebba6..24af549977 100644
+--- a/scripts/dtc/dtc-lexer.l
++++ b/scripts/dtc/dtc-lexer.l
+@@ -38,7 +38,6 @@ LINECOMMENT	"//".*\n
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+ 
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+ 
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-cn9130-fix-compatible-node-inside-dts-pt-2.patch

@@ -0,0 +1,26 @@
+From 841657cef0b50f6e3af4d3d3c829e438fbac7cc3 Mon Sep 17 00:00:00 2001
+From: Patrick Vogelaar <patrick.vogelaar@belden.com>
+Date: Wed, 19 Apr 2023 09:07:10 +0200
+Subject: [PATCH] fix u-boot device tree compatible
+
+---
+ arch/arm/dts/cn9131-bldn-mbv.dts | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
+index d10c7f032e..74322805db 100644
+--- a/arch/arm/dts/cn9131-bldn-mbv.dts
++++ b/arch/arm/dts/cn9131-bldn-mbv.dts
+@@ -11,8 +11,10 @@
+ 
+ / {
+ 	model = "Belden CN9131 based Platform";
+-	compatible =	"marvell,cn9131-db", "marvell,armada-ap806-quad",
+-			"marvell,armada-ap806";
++	compatible =  "solidrun,cn9131-bldn-mbv", "marvell,cn9130-db",
++		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
++		"marvell,armada-ap806-quad", "marvell,armada-ap806",
++		"marvell,armada70x0";
+ };
+ 
+ &cp1_comphy {

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-cn9130-fix-compatible-node-inside-dts.patch

@@ -0,0 +1,65 @@
+From 0017797ce718f4512271deddde75120c57623049 Mon Sep 17 00:00:00 2001
+From: Samuel Dolt <samuel.dolt@netmodule.com>
+Date: Tue, 24 Jan 2023 15:22:58 +0100
+Subject: [PATCH] cn9130: fix compatible node inside dts
+
+---
+ arch/arm/dts/cn9130-bldn-mbv.dts | 7 ++++---
+ arch/arm/dts/cn9130-cex7-A.dts   | 7 ++++---
+ arch/arm/dts/cn9130-cf-pro.dts   | 7 ++++---
+ 3 files changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
+index 9e10eab008..a91c490218 100644
+--- a/arch/arm/dts/cn9130-bldn-mbv.dts
++++ b/arch/arm/dts/cn9130-bldn-mbv.dts
+@@ -10,9 +10,10 @@
+ 
+ / {
+ 	model = "Belden CN9130 based SOM and Carrier MBV-A/B";
+-	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+-		     "marvell,cn9030", "marvell,armada-ap806-quad",
+-		     "marvell,armada-ap806", "marvell,armada70x0";
++	compatible =  "solidrun,cn9130-bldn-mbv", "marvell,cn9130-db",
++		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
++		"marvell,armada-ap806-quad", "marvell,armada-ap806",
++		"marvell,armada70x0";
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+diff --git a/arch/arm/dts/cn9130-cex7-A.dts b/arch/arm/dts/cn9130-cex7-A.dts
+index 209e485822..9995a586f6 100644
+--- a/arch/arm/dts/cn9130-cex7-A.dts
++++ b/arch/arm/dts/cn9130-cex7-A.dts
+@@ -10,9 +10,10 @@
+ 
+ / {
+ 	model = "SolidRun CN9130 based COM express type 7";
+-	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+-		     "marvell,cn9030", "marvell,armada-ap806-quad",
+-		     "marvell,armada-ap806", "marvell,armada70x0";
++	compatible =  "solidrun,cn9130-cex7", "marvell,cn9130-db",
++		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
++		"marvell,armada-ap806-quad", "marvell,armada-ap806",
++		"marvell,armada70x0";
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
+index 6931818cf6..dae7a75076 100644
+--- a/arch/arm/dts/cn9130-cf-pro.dts
++++ b/arch/arm/dts/cn9130-cf-pro.dts
+@@ -10,9 +10,10 @@
+ 
+ / {
+ 	model = "SolidRun CN9130 based SOM ClearFog Pro";
+-	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+-		     "marvell,cn9030", "marvell,armada-ap806-quad",
+-		     "marvell,armada-ap806", "marvell,armada70x0";
++	compatible = "solidrun,cn9130-cf-pro", "marvell,cn9130-db",
++		"marvell,cn91xx", "marvell,cn9030-vd", "marvell,cn9030",
++		"marvell,armada-ap806-quad", "marvell,armada-ap806",
++		"marvell,armada70x0";
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-sr_cn913x_cex7-enable-VERSION_VARIABLE.patch

@@ -0,0 +1,18 @@
+From 8b62e225c541fdfcc764582ee80bf0d8a0b6bc65 Mon Sep 17 00:00:00 2001
+From: Samuel Dolt <samuel.dolt@netmodule.com>
+Date: Mon, 25 Jul 2022 15:02:00 +0200
+Subject: [PATCH] sr_cn913x_cex7: enable VERSION_VARIABLE
+
+---
+ configs/sr_cn913x_cex7_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index 3e01b31371..a7c6c9f93e 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -115,3 +115,4 @@ CONFIG_ZSTD=y
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_OF_LIBFDT=y
++CONFIG_VERSION_VARIABLE=y

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0001-sr_cn913x_cex7-enable-more-image-formats.patch

@@ -0,0 +1,27 @@
+From ca34fc483e68e332c5aa6c3cc98e04604216d846 Mon Sep 17 00:00:00 2001
+From: Samuel Dolt <samuel.dolt@netmodule.com>
+Date: Fri, 15 Jul 2022 15:36:12 +0200
+Subject: [PATCH] sr_cn913x_cex7: enable more image formats
+
+---
+ configs/sr_cn913x_cex7_defconfig | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index d7445e9476..3e01b31371 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -105,3 +105,13 @@ CONFIG_I2C_EEPROM=y
+ CONFIG_CMD_TLV_EEPROM=y
+ CONFIG_SUPPORT_EMMC_BOOT=y
+ CONFIG_NET_RANDOM_ETHADDR=y
++# Custom
++CONFIG_BZIP2=y
++CONFIG_GZIP=y
++CONFIG_LZ4=y
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_OF_LIBFDT=y

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/0021-octeontx2_cn913x-increase-CONFIG_SYS_BOOTM_LEN-to-32.patch

@@ -0,0 +1,22 @@
+From 7e4c3c48c4ed9dcecf5228c6b4480a7c01fc6dca Mon Sep 17 00:00:00 2001
+From: Samuel Dolt <samuel.dolt@netmodule.com>
+Date: Tue, 19 Jul 2022 11:21:37 +0200
+Subject: [PATCH] octeontx2_cn913x: increase CONFIG_SYS_BOOTM_LEN to 32MB
+
+---
+ include/configs/octeontx2_cn913x.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
+index d01644fcb5..9edf57c6c2 100644
+--- a/include/configs/octeontx2_cn913x.h
++++ b/include/configs/octeontx2_cn913x.h
+@@ -22,6 +22,8 @@
+ #define CONFIG_SYS_NAND_ONFI_DETECTION
+ #define CONFIG_SYS_NAND_USE_FLASH_BBT
+ 
++#define CONFIG_SYS_BOOTM_LEN 0x3200000 /* 32MB */
++
+ #define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+ 
+ #define BOOT_TARGET_DEVICES(func) \

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0002-cmd-tlv_eeprom.patch

@@ -0,0 +1,27 @@
+From 0dce367ced42c77d4de5c17b52605c6c003a4b20 Mon Sep 17 00:00:00 2001
+From: Sven Auhagen <Sven.Auhagen@voleatech.de>
+Date: Sun, 12 Sep 2021 09:25:44 +0200
+Subject: [PATCH] cmd: tlv_eeprom
+
+The function show_eeprom is missing int i if debug is enabled.
+
+Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
+Reviewed-by: Stefan Roese <sr@denx.de>
+---
+ cmd/tlv_eeprom.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 211ab2680f..96d40f4f4d 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -166,6 +166,9 @@ static void show_eeprom(u8 *eeprom)
+ {
+ 	int tlv_end;
+ 	int curr_tlv;
++#ifdef DEBUG
++	int i;
++#endif
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	struct tlvinfo_tlv    *eeprom_tlv;
+ 

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0003-cmd-tlv_eeprom-remove-use-of-global-variable-current.patch

@@ -0,0 +1,227 @@
+From 3a807537ace144e802e3421b29f3eea0e48d2f1f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Thu, 17 Mar 2022 11:52:34 +0200
+Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable current_dev
+
+Make tlv_eeprom command device selection an explicit parameter of all
+function calls.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ cmd/tlv_eeprom.c     | 50 ++++++++++++++++++++++----------------------
+ include/tlv_eeprom.h |  3 ++-
+ 2 files changed, 27 insertions(+), 26 deletions(-)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 96d40f4f4d..05d28c26c8 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -26,18 +26,18 @@ DECLARE_GLOBAL_DATA_PTR;
+ 
+ /* File scope function prototypes */
+ static bool is_checksum_valid(u8 *eeprom);
+-static int read_eeprom(u8 *eeprom);
+-static void show_eeprom(u8 *eeprom);
++static int read_eeprom(int devnum, u8 *eeprom);
++static void show_eeprom(int devnum, u8 *eeprom);
+ static void decode_tlv(struct tlvinfo_tlv *tlv);
+ static void update_crc(u8 *eeprom);
+-static int prog_eeprom(u8 *eeprom);
++static int prog_eeprom(int devnum, u8 *eeprom);
+ static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
+ static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
+ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
+ static int set_mac(char *buf, const char *string);
+ static int set_date(char *buf, const char *string);
+ static int set_bytes(char *buf, const char *string, int *converted_accum);
+-static void show_tlv_devices(void);
++static void show_tlv_devices(int current_dev);
+ 
+ /* Set to 1 if we've read EEPROM into memory */
+ static int has_been_read;
+@@ -45,7 +45,6 @@ static int has_been_read;
+ static u8 eeprom[TLV_INFO_MAX_LEN];
+ 
+ static struct udevice *tlv_devices[MAX_TLV_DEVICES];
+-static unsigned int current_dev;
+ 
+ #define to_header(p) ((struct tlvinfo_header *)p)
+ #define to_entry(p) ((struct tlvinfo_tlv *)p)
+@@ -122,7 +121,7 @@ static bool is_checksum_valid(u8 *eeprom)
+  *
+  *  Read the EEPROM into memory, if it hasn't already been read.
+  */
+-static int read_eeprom(u8 *eeprom)
++static int read_eeprom(int devnum, u8 *eeprom)
+ {
+ 	int ret;
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+@@ -132,12 +131,11 @@ static int read_eeprom(u8 *eeprom)
+ 		return 0;
+ 
+ 	/* Read the header */
+-	ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, current_dev);
++	ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
+ 	/* If the header was successfully read, read the TLVs */
+ 	if (ret == 0 && is_valid_tlvinfo_header(eeprom_hdr))
+ 		ret = read_tlv_eeprom((void *)eeprom_tlv, HDR_SIZE,
+-				      be16_to_cpu(eeprom_hdr->totallen),
+-				      current_dev);
++				      be16_to_cpu(eeprom_hdr->totallen), devnum);
+ 
+ 	// If the contents are invalid, start over with default contents
+ 	if (!is_valid_tlvinfo_header(eeprom_hdr) ||
+@@ -162,7 +160,7 @@ static int read_eeprom(u8 *eeprom)
+  *
+  *  Display the contents of the EEPROM
+  */
+-static void show_eeprom(u8 *eeprom)
++static void show_eeprom(int devnum, u8 *eeprom)
+ {
+ 	int tlv_end;
+ 	int curr_tlv;
+@@ -177,7 +175,7 @@ static void show_eeprom(u8 *eeprom)
+ 		return;
+ 	}
+ 
+-	printf("TLV: %u\n", current_dev);
++	printf("TLV: %u\n", devnum);
+ 	printf("TlvInfo Header:\n");
+ 	printf("   Id String:    %s\n", eeprom_hdr->signature);
+ 	printf("   Version:      %d\n", eeprom_hdr->version);
+@@ -386,7 +384,7 @@ static void update_crc(u8 *eeprom)
+  *
+  *  Write the EEPROM data from CPU memory to the hardware.
+  */
+-static int prog_eeprom(u8 *eeprom)
++static int prog_eeprom(int devnum, u8 *eeprom)
+ {
+ 	int ret = 0;
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+@@ -395,7 +393,7 @@ static int prog_eeprom(u8 *eeprom)
+ 	update_crc(eeprom);
+ 
+ 	eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
+-	ret = write_tlv_eeprom(eeprom, eeprom_len);
++	ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
+ 	if (ret) {
+ 		printf("Programming failed.\n");
+ 		return -1;
+@@ -430,11 +428,12 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ {
+ 	char cmd;
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
++	static unsigned int current_dev = 0;
+ 
+ 	// If no arguments, read the EERPOM and display its contents
+ 	if (argc == 1) {
+-		read_eeprom(eeprom);
+-		show_eeprom(eeprom);
++		read_eeprom(current_dev, eeprom);
++		show_eeprom(current_dev, eeprom);
+ 		return 0;
+ 	}
+ 
+@@ -445,7 +444,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	// Read the EEPROM contents
+ 	if (cmd == 'r') {
+ 		has_been_read = 0;
+-		if (!read_eeprom(eeprom))
++		if (!read_eeprom(current_dev, eeprom))
+ 			printf("EEPROM data loaded from device to memory.\n");
+ 		return 0;
+ 	}
+@@ -460,7 +459,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	if (argc == 2) {
+ 		switch (cmd) {
+ 		case 'w':   /* write */
+-			prog_eeprom(eeprom);
++			prog_eeprom(current_dev, eeprom);
+ 			break;
+ 		case 'e':   /* erase */
+ 			strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
+@@ -473,7 +472,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 			show_tlv_code_list();
+ 			break;
+ 		case 'd':   /* dev */
+-			show_tlv_devices();
++			show_tlv_devices(current_dev);
+ 			break;
+ 		default:
+ 			cmd_usage(cmdtp);
+@@ -883,7 +882,7 @@ static int set_bytes(char *buf, const char *string, int *converted_accum)
+ 	return 0;
+ }
+ 
+-static void show_tlv_devices(void)
++static void show_tlv_devices(int current_dev)
+ {
+ 	unsigned int dev;
+ 
+@@ -953,14 +952,14 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev_num)
+ /**
+  * write_tlv_eeprom - write the hwinfo to i2c EEPROM
+  */
+-int write_tlv_eeprom(void *eeprom, int len)
++int write_tlv_eeprom(void *eeprom, int len, int dev)
+ {
+ 	if (!(gd->flags & GD_FLG_RELOC))
+ 		return -ENODEV;
+-	if (!tlv_devices[current_dev])
++	if (!tlv_devices[dev])
+ 		return -ENODEV;
+ 
+-	return i2c_eeprom_write(tlv_devices[current_dev], 0, eeprom, len);
++	return i2c_eeprom_write(tlv_devices[dev], 0, eeprom, len);
+ }
+ 
+ int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
+@@ -1015,10 +1014,11 @@ int mac_read_from_eeprom(void)
+ 	int maccount;
+ 	u8 macbase[6];
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
++	int devnum = 0; // TODO: support multiple EEPROMs
+ 
+ 	puts("EEPROM: ");
+ 
+-	if (read_eeprom(eeprom)) {
++	if (read_eeprom(devnum, eeprom)) {
+ 		printf("Read failed.\n");
+ 		return -1;
+ 	}
+@@ -1083,7 +1083,7 @@ int mac_read_from_eeprom(void)
+  *
+  *  This function must be called after relocation.
+  */
+-int populate_serial_number(void)
++int populate_serial_number(int devnum)
+ {
+ 	char serialstr[257];
+ 	int eeprom_index;
+@@ -1092,7 +1092,7 @@ int populate_serial_number(void)
+ 	if (env_get("serial#"))
+ 		return 0;
+ 
+-	if (read_eeprom(eeprom)) {
++	if (read_eeprom(devnum, eeprom)) {
+ 		printf("Read failed.\n");
+ 		return -1;
+ 	}
+diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
+index 1de2fe2337..aa96c9e8d4 100644
+--- a/include/tlv_eeprom.h
++++ b/include/tlv_eeprom.h
+@@ -84,11 +84,12 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev);
+  * write_tlv_eeprom - Write the entire EEPROM binary data to the hardware
+  * @eeprom: Pointer to buffer to hold the binary data
+  * @len   : Maximum size of buffer
++ * @dev   : EEPROM device to write
+  *
+  * Note: this routine does not validate the EEPROM data.
+  *
+  */
+-int write_tlv_eeprom(void *eeprom, int len);
++int write_tlv_eeprom(void *eeprom, int len, int dev);
+ 
+ /**
+  * read_tlvinfo_tlv_eeprom - Read the TLV from EEPROM, and validate

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0004-cmd-tlv_eeprom-remove-use-of-global-variable-has_bee.patch

@@ -0,0 +1,94 @@
+From 28da9685c7e65f70065319921ccaf2d2aea7b185 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Thu, 17 Mar 2022 12:49:46 +0200
+Subject: [PATCH] cmd: tlv_eeprom: remove use of global variable has_been_read
+
+has_been_read is only used as an optimization for do_tlv_eeprom.
+Explicitly use and set inside this function, thus making read_eeprom
+stateless.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ cmd/tlv_eeprom.c | 25 ++++++++++++-------------
+ 1 file changed, 12 insertions(+), 13 deletions(-)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 05d28c26c8..70c1a2e7df 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -39,8 +39,6 @@ static int set_date(char *buf, const char *string);
+ static int set_bytes(char *buf, const char *string, int *converted_accum);
+ static void show_tlv_devices(int current_dev);
+ 
+-/* Set to 1 if we've read EEPROM into memory */
+-static int has_been_read;
+ /* The EERPOM contents after being read into memory */
+ static u8 eeprom[TLV_INFO_MAX_LEN];
+ 
+@@ -127,9 +125,6 @@ static int read_eeprom(int devnum, u8 *eeprom)
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	struct tlvinfo_tlv *eeprom_tlv = to_entry(&eeprom[HDR_SIZE]);
+ 
+-	if (has_been_read)
+-		return 0;
+-
+ 	/* Read the header */
+ 	ret = read_tlv_eeprom((void *)eeprom_hdr, 0, HDR_SIZE, devnum);
+ 	/* If the header was successfully read, read the TLVs */
+@@ -146,10 +141,8 @@ static int read_eeprom(int devnum, u8 *eeprom)
+ 		update_crc(eeprom);
+ 	}
+ 
+-	has_been_read = 1;
+-
+ #ifdef DEBUG
+-	show_eeprom(eeprom);
++	show_eeprom(devnum, eeprom);
+ #endif
+ 
+ 	return ret;
+@@ -429,10 +422,15 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	char cmd;
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	static unsigned int current_dev = 0;
++	/* Set to devnum if we've read EEPROM into memory */
++	static int has_been_read = -1;
+ 
+ 	// If no arguments, read the EERPOM and display its contents
+ 	if (argc == 1) {
+-		read_eeprom(current_dev, eeprom);
++		if(has_been_read != current_dev) {
++			read_eeprom(current_dev, eeprom);
++			has_been_read = current_dev;
++		}
+ 		show_eeprom(current_dev, eeprom);
+ 		return 0;
+ 	}
+@@ -443,14 +441,16 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 
+ 	// Read the EEPROM contents
+ 	if (cmd == 'r') {
+-		has_been_read = 0;
+-		if (!read_eeprom(current_dev, eeprom))
++		has_been_read = -1;
++		if (!read_eeprom(current_dev, eeprom)) {
+ 			printf("EEPROM data loaded from device to memory.\n");
++			has_been_read = current_dev;
++		}
+ 		return 0;
+ 	}
+ 
+ 	// Subsequent commands require that the EEPROM has already been read.
+-	if (!has_been_read) {
++	if (has_been_read != current_dev) {
+ 		printf("Please read the EEPROM data first, using the 'tlv_eeprom read' command.\n");
+ 		return 0;
+ 	}
+@@ -506,7 +506,6 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 			return 0;
+ 		}
+ 		current_dev = devnum;
+-		has_been_read = 0;
+ 	} else {
+ 		cmd_usage(cmdtp);
+ 	}

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0005-cmd-tlv_eeprom-do_tlv_eeprom-stop-using-non-api-read.patch

@@ -0,0 +1,37 @@
+From 6578def0ace0d030a02b8c45031d41c5d2ef517e Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Thu, 17 Mar 2022 14:23:22 +0200
+Subject: [PATCH] cmd: tlv_eeprom: do_tlv_eeprom: stop using non-api
+ read_eeprom function
+
+IN the scope of do_tlv_eeprom, the error-checking provided by the
+read_eeprom function is not required.
+Instead use the API function read_tlv_eeprom.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ cmd/tlv_eeprom.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 70c1a2e7df..8a926ba224 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -428,7 +428,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	// If no arguments, read the EERPOM and display its contents
+ 	if (argc == 1) {
+ 		if(has_been_read != current_dev) {
+-			read_eeprom(current_dev, eeprom);
++			read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev);
+ 			has_been_read = current_dev;
+ 		}
+ 		show_eeprom(current_dev, eeprom);
+@@ -442,7 +442,7 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	// Read the EEPROM contents
+ 	if (cmd == 'r') {
+ 		has_been_read = -1;
+-		if (!read_eeprom(current_dev, eeprom)) {
++		if (read_tlv_eeprom(eeprom, 0, TLV_INFO_MAX_LEN, current_dev) == 0) {
+ 			printf("EEPROM data loaded from device to memory.\n");
+ 			has_been_read = current_dev;
+ 		}

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0006-cmd-tlv_eeprom-convert-functions-used-by-command-to-.patch

@@ -0,0 +1,278 @@
+From 62114ab82feaf919138d2d4377344072c95571de Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Thu, 17 Mar 2022 16:09:02 +0200
+Subject: [PATCH] cmd: tlv_eeprom: convert functions used by command to api
+ functions
+
+- prog_eeprom: write_tlvinfo_tlv_eeprom
+- update_crc: tlvinfo_update_crc
+- is_valid_tlv: is_valid_tlvinfo_entry
+- is_checksum_valid: tlvinfo_check_crc
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ cmd/tlv_eeprom.c     | 56 +++++++++++++++----------------------------
+ include/tlv_eeprom.h | 57 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 76 insertions(+), 37 deletions(-)
+
+diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c
+index 8a926ba224..271fefc0c6 100644
+--- a/cmd/tlv_eeprom.c
++++ b/cmd/tlv_eeprom.c
+@@ -25,13 +25,9 @@ DECLARE_GLOBAL_DATA_PTR;
+ #define MAX_TLV_DEVICES	2
+ 
+ /* File scope function prototypes */
+-static bool is_checksum_valid(u8 *eeprom);
+ static int read_eeprom(int devnum, u8 *eeprom);
+ static void show_eeprom(int devnum, u8 *eeprom);
+ static void decode_tlv(struct tlvinfo_tlv *tlv);
+-static void update_crc(u8 *eeprom);
+-static int prog_eeprom(int devnum, u8 *eeprom);
+-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
+ static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
+ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval);
+ static int set_mac(char *buf, const char *string);
+@@ -55,18 +51,6 @@ static inline bool is_digit(char c)
+ 	return (c >= '0' && c <= '9');
+ }
+ 
+-/**
+- *  is_valid_tlv
+- *
+- *  Perform basic sanity checks on a TLV field. The TLV is pointed to
+- *  by the parameter provided.
+- *      1. The type code is not reserved (0x00 or 0xFF)
+- */
+-static inline bool is_valid_tlv(struct tlvinfo_tlv *tlv)
+-{
+-	return((tlv->type != 0x00) && (tlv->type != 0xFF));
+-}
+-
+ /**
+  *  is_hex
+  *
+@@ -80,14 +64,12 @@ static inline u8 is_hex(char p)
+ }
+ 
+ /**
+- *  is_checksum_valid
+- *
+  *  Validate the checksum in the provided TlvInfo EEPROM data. First,
+  *  verify that the TlvInfo header is valid, then make sure the last
+  *  TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
+  *  and compare it to the value stored in the EEPROM CRC-32 TLV.
+  */
+-static bool is_checksum_valid(u8 *eeprom)
++bool tlvinfo_check_crc(u8 *eeprom)
+ {
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	struct tlvinfo_tlv    *eeprom_crc;
+@@ -134,11 +116,11 @@ static int read_eeprom(int devnum, u8 *eeprom)
+ 
+ 	// If the contents are invalid, start over with default contents
+ 	if (!is_valid_tlvinfo_header(eeprom_hdr) ||
+-	    !is_checksum_valid(eeprom)) {
++	    !tlvinfo_check_crc(eeprom)) {
+ 		strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
+ 		eeprom_hdr->version = TLV_INFO_VERSION;
+ 		eeprom_hdr->totallen = cpu_to_be16(0);
+-		update_crc(eeprom);
++		tlvinfo_update_crc(eeprom);
+ 	}
+ 
+ #ifdef DEBUG
+@@ -180,7 +162,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
+ 	tlv_end  = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
+ 	while (curr_tlv < tlv_end) {
+ 		eeprom_tlv = to_entry(&eeprom[curr_tlv]);
+-		if (!is_valid_tlv(eeprom_tlv)) {
++		if (!is_valid_tlvinfo_entry(eeprom_tlv)) {
+ 			printf("Invalid TLV field starting at EEPROM offset %d\n",
+ 			       curr_tlv);
+ 			return;
+@@ -190,7 +172,7 @@ static void show_eeprom(int devnum, u8 *eeprom)
+ 	}
+ 
+ 	printf("Checksum is %s.\n",
+-	       is_checksum_valid(eeprom) ? "valid" : "invalid");
++	       tlvinfo_check_crc(eeprom) ? "valid" : "invalid");
+ 
+ #ifdef DEBUG
+ 	printf("EEPROM dump: (0x%x bytes)", TLV_INFO_MAX_LEN);
+@@ -337,13 +319,13 @@ static void decode_tlv(struct tlvinfo_tlv *tlv)
+ }
+ 
+ /**
+- *  update_crc
++ *  tlvinfo_update_crc
+  *
+  *  This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
+  *  one is added. This function should be called after each update to the
+  *  EEPROM structure, to make sure the CRC is always correct.
+  */
+-static void update_crc(u8 *eeprom)
++void tlvinfo_update_crc(u8 *eeprom)
+ {
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	struct tlvinfo_tlv    *eeprom_crc;
+@@ -373,20 +355,20 @@ static void update_crc(u8 *eeprom)
+ }
+ 
+ /**
+- *  prog_eeprom
++ *  write_tlvinfo_tlv_eeprom
+  *
+- *  Write the EEPROM data from CPU memory to the hardware.
++ *  Write the TLV data from CPU memory to the hardware.
+  */
+-static int prog_eeprom(int devnum, u8 *eeprom)
++int write_tlvinfo_tlv_eeprom(void *eeprom, int dev)
+ {
+ 	int ret = 0;
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	int eeprom_len;
+ 
+-	update_crc(eeprom);
++	tlvinfo_update_crc(eeprom);
+ 
+ 	eeprom_len = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
+-	ret = write_tlv_eeprom(eeprom, eeprom_len, devnum);
++	ret = write_tlv_eeprom(eeprom, eeprom_len, dev);
+ 	if (ret) {
+ 		printf("Programming failed.\n");
+ 		return -1;
+@@ -459,13 +441,13 @@ int do_tlv_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+ 	if (argc == 2) {
+ 		switch (cmd) {
+ 		case 'w':   /* write */
+-			prog_eeprom(current_dev, eeprom);
++			write_tlvinfo_tlv_eeprom(eeprom, current_dev);
+ 			break;
+ 		case 'e':   /* erase */
+ 			strcpy(eeprom_hdr->signature, TLV_INFO_ID_STRING);
+ 			eeprom_hdr->version = TLV_INFO_VERSION;
+ 			eeprom_hdr->totallen = cpu_to_be16(0);
+-			update_crc(eeprom);
++			tlvinfo_update_crc(eeprom);
+ 			printf("EEPROM data in memory reset.\n");
+ 			break;
+ 		case 'l':   /* list */
+@@ -546,7 +528,7 @@ U_BOOT_CMD(tlv_eeprom, 4, 1,  do_tlv_eeprom,
+  *  An offset from the beginning of the EEPROM is returned in the
+  *  eeprom_index parameter if the TLV is found.
+  */
+-static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
++bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
+ {
+ 	struct tlvinfo_header *eeprom_hdr = to_header(eeprom);
+ 	struct tlvinfo_tlv    *eeprom_tlv;
+@@ -558,7 +540,7 @@ static bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index)
+ 	eeprom_end = HDR_SIZE + be16_to_cpu(eeprom_hdr->totallen);
+ 	while (*eeprom_index < eeprom_end) {
+ 		eeprom_tlv = to_entry(&eeprom[*eeprom_index]);
+-		if (!is_valid_tlv(eeprom_tlv))
++		if (!is_valid_tlvinfo_entry(eeprom_tlv))
+ 			return false;
+ 		if (eeprom_tlv->type == tcode)
+ 			return true;
+@@ -591,7 +573,7 @@ static bool tlvinfo_delete_tlv(u8 *eeprom, u8 code)
+ 		eeprom_hdr->totallen =
+ 			cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) -
+ 				    tlength);
+-		update_crc(eeprom);
++		tlvinfo_update_crc(eeprom);
+ 		return true;
+ 	}
+ 	return false;
+@@ -692,7 +674,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval)
+ 	// Update the total length and calculate (add) a new CRC-32 TLV
+ 	eeprom_hdr->totallen = cpu_to_be16(be16_to_cpu(eeprom_hdr->totallen) +
+ 			ENT_SIZE + new_tlv_len);
+-	update_crc(eeprom);
++	tlvinfo_update_crc(eeprom);
+ 
+ 	return true;
+ }
+@@ -983,7 +965,7 @@ int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
+ 			      be16_to_cpu(tlv_hdr->totallen), dev_num);
+ 	if (ret < 0)
+ 		return ret;
+-	if (!is_checksum_valid(eeprom))
++	if (!tlvinfo_check_crc(eeprom))
+ 		return -EINVAL;
+ 
+ 	*hdr = tlv_hdr;
+diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
+index aa96c9e8d4..eeb8af57f1 100644
+--- a/include/tlv_eeprom.h
++++ b/include/tlv_eeprom.h
+@@ -111,6 +111,51 @@ int write_tlv_eeprom(void *eeprom, int len, int dev);
+ int read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
+ 			    struct tlvinfo_tlv **first_entry, int dev);
+ 
++/**
++ * Write TLV data to the EEPROM.
++ * 
++ * - Only writes length of actual tlv data
++ * - updates checksum
++ * 
++ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
++ *          of size at least TLV_INFO_MAX_LEN.
++ * @dev   : EEPROM device to write
++ * 
++ */
++int write_tlvinfo_tlv_eeprom(void *eeprom, int dev);
++
++/**
++ *  tlvinfo_find_tlv
++ *
++ *  This function finds the TLV with the supplied code in the EERPOM.
++ *  An offset from the beginning of the EEPROM is returned in the
++ *  eeprom_index parameter if the TLV is found.
++ */
++bool tlvinfo_find_tlv(u8 *eeprom, u8 tcode, int *eeprom_index);
++
++/**
++ *  tlvinfo_update_crc
++ *
++ *  This function updates the CRC-32 TLV. If there is no CRC-32 TLV, then
++ *  one is added. This function should be called after each update to the
++ *  EEPROM structure, to make sure the CRC is always correct.
++ * 
++ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
++ *          of size at least TLV_INFO_MAX_LEN.
++ */
++void tlvinfo_update_crc(u8 *eeprom);
++
++/**
++ *  Validate the checksum in the provided TlvInfo EEPROM data. First,
++ *  verify that the TlvInfo header is valid, then make sure the last
++ *  TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data
++ *  and compare it to the value stored in the EEPROM CRC-32 TLV.
++ * 
++ * @eeprom: Pointer to buffer to hold the binary data. Must point to a buffer
++ *          of size at least TLV_INFO_MAX_LEN.
++ */
++bool tlvinfo_check_crc(u8 *eeprom);
++
+ #else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
+ 
+ static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
+@@ -150,4 +195,16 @@ static inline bool is_valid_tlvinfo_header(struct tlvinfo_header *hdr)
+ 		(be16_to_cpu(hdr->totallen) <= TLV_TOTAL_LEN_MAX));
+ }
+ 
++/**
++ *  is_valid_tlv
++ *
++ *  Perform basic sanity checks on a TLV field. The TLV is pointed to
++ *  by the parameter provided.
++ *      1. The type code is not reserved (0x00 or 0xFF)
++ */
++static inline bool is_valid_tlvinfo_entry(struct tlvinfo_tlv *tlv)
++{
++	return((tlv->type != 0x00) && (tlv->type != 0xFF));
++}
++
+ #endif /* __TLV_EEPROM_H_ */

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0007-cmd-tlv_eeprom-remove-empty-function-implementations.patch

@@ -0,0 +1,56 @@
+From 04ce313a110bae4262684666c245443182d6f0bc Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 20 Mar 2022 11:11:25 +0200
+Subject: [PATCH] cmd: tlv_eeprom: remove empty function implementations from
+ header
+
+tlv_eeprom exposed functions are independent from platforms, hence no
+stubs are required.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ include/tlv_eeprom.h | 24 ++----------------------
+ 1 file changed, 2 insertions(+), 22 deletions(-)
+
+diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
+index eeb8af57f1..201a2b44af 100644
+--- a/include/tlv_eeprom.h
++++ b/include/tlv_eeprom.h
+@@ -65,7 +65,8 @@ struct __attribute__ ((__packed__)) tlvinfo_tlv {
+ #define TLV_CODE_VENDOR_EXT     0xFD
+ #define TLV_CODE_CRC_32         0xFE
+ 
+-#if CONFIG_IS_ENABLED(CMD_TLV_EEPROM)
++/* how many EEPROMs can be used */
++#define TLV_MAX_DEVICES			2
+ 
+ /**
+  * read_tlv_eeprom - Read the EEPROM binary data from the hardware
+@@ -156,27 +157,6 @@ void tlvinfo_update_crc(u8 *eeprom);
+  */
+ bool tlvinfo_check_crc(u8 *eeprom);
+ 
+-#else /* !CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
+-
+-static inline int read_tlv_eeprom(void *eeprom, int offset, int len, int dev)
+-{
+-	return -ENOTSUPP;
+-}
+-
+-static inline int write_tlv_eeprom(void *eeprom, int len)
+-{
+-	return -ENOTSUPP;
+-}
+-
+-static inline int
+-read_tlvinfo_tlv_eeprom(void *eeprom, struct tlvinfo_header **hdr,
+-			struct tlvinfo_tlv **first_entry, int dev)
+-{
+-	return -ENOTSUPP;
+-}
+-
+-#endif /* CONFIG_IS_ENABLED(CMD_TLV_EEPROM) */
+-
+ /**
+  *  is_valid_tlvinfo_header
+  *

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0009-lib-tlv_eeprom-add-function-for-reading-one-entry-in.patch

@@ -0,0 +1,69 @@
+From 40355952340169930bfbd03a6ea4de3041c39754 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 20 Mar 2022 12:07:38 +0200
+Subject: [PATCH] lib: tlv_eeprom: add function for reading one entry into a C
+ string
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ include/tlv_eeprom.h | 12 ++++++++++++
+ lib/tlv/tlv_eeprom.c | 23 +++++++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
+index ee9f035c8c..c91618e480 100644
+--- a/include/tlv_eeprom.h
++++ b/include/tlv_eeprom.h
+@@ -167,6 +167,18 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval);
+  */
+ bool tlvinfo_delete_tlv(u8 *eeprom, u8 code);
+ 
++/**
++ * Read the TLV entry with specified code to a buffer as terminated C string.
++ * @eeprom: Pointer to buffer holding the TLV EEPROM binary data.
++ * @code:   The TLV Code of the entry to read.
++ * @buffer: Pointer to buffer where the value will be stored. Must have capacity
++ *          for the string representation of the data including null terminator.
++ * @length: size of the buffer where the value will be stored.
++ * 
++ * Return length of string on success, -1 on error.
++ */
++ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length);
++
+ /**
+  *  tlvinfo_update_crc
+  *
+diff --git a/lib/tlv/tlv_eeprom.c b/lib/tlv/tlv_eeprom.c
+index fe164cabe6..e2c7a0d664 100644
+--- a/lib/tlv/tlv_eeprom.c
++++ b/lib/tlv/tlv_eeprom.c
+@@ -349,6 +349,29 @@ bool tlvinfo_add_tlv(u8 *eeprom, int code, char *strval)
+ 	return true;
+ }
+ 
++/**
++ * Read the TLV entry with specified code to a buffer as terminated C string.
++ */
++ssize_t tlvinfo_read_tlv(u8 *eeprom, u8 code, u8 *buffer, size_t length) {
++	int index;
++	struct tlvinfo_tlv *tlv;
++
++	// read sku from part-number field
++	if(tlvinfo_find_tlv(eeprom, code, &index)) {
++		tlv = (struct tlvinfo_tlv *) &eeprom[index];
++		if(tlv->length > length) {
++			pr_err("%s: tlv value (%d) larger than buffer (%zu)!\n", __func__, tlv->length+1, length);
++			return -1;
++		}
++		memcpy(buffer, tlv->value, tlv->length);
++		buffer[tlv->length] = 0;
++
++		return tlv->length;
++	}
++
++	return -1;
++}
++
+ /**
+  *  set_mac
+  *

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0012-add-SoM-and-Carrier-eeproms.patch

@@ -0,0 +1,111 @@
+From 79df8e99fb5cc4c0e2716b1051302f72df28ee04 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 13 Mar 2022 10:54:15 +0200
+Subject: [PATCH] add SoM and Carrier eeproms
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ arch/arm/dts/cn9130-cex7-A.dts  | 11 ++++++-----
+ arch/arm/dts/cn9130-cf-base.dts | 20 +++++++++++++++-----
+ arch/arm/dts/cn9130-cf-pro.dts  | 20 +++++++++++++++-----
+ 3 files changed, 36 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm/dts/cn9130-cex7-A.dts b/arch/arm/dts/cn9130-cex7-A.dts
+index 2db0fc802e..209e485822 100644
+--- a/arch/arm/dts/cn9130-cex7-A.dts
++++ b/arch/arm/dts/cn9130-cex7-A.dts
+@@ -147,12 +147,13 @@
+ 	pinctrl-0 = <&cp0_i2c0_pins>;
+ 	status = "okay";
+ 	clock-frequency = <100000>;
+-	eeprom0: eeprom@50 {
+-                compatible = "atmel,24c64";
+-                reg = <0x50>;
+-                pagesize = <0x20>;
+-        };
+ 
++	/* M24C0x-MWN */
++	com_eeprom@50 {
++		compatible = "atmel,24c02";
++		reg = <0x50>;
++		pagesize = <0x10>;
++	};
+ };
+ 
+ &cp0_i2c1 {
+diff --git a/arch/arm/dts/cn9130-cf-base.dts b/arch/arm/dts/cn9130-cf-base.dts
+index a9d4a4491f..355c9d8ed0 100644
+--- a/arch/arm/dts/cn9130-cf-base.dts
++++ b/arch/arm/dts/cn9130-cf-base.dts
+@@ -145,11 +145,7 @@
+ 	pinctrl-0 = <&cp0_i2c0_pins>;
+ 	status = "okay";
+ 	clock-frequency = <100000>;
+-	eeprom0: eeprom@50 {
+-                compatible = "atmel,24c64";
+-                reg = <0x53>;
+-                pagesize = <0x20>;
+-        };
++
+ 	/*
+ 	 * PCA9655 GPIO expander, up to 1MHz clock.
+ 	 *  0-CON3 CLKREQ#
+@@ -225,6 +221,20 @@
+ 			line-name = "m.2 devslp";
+ 		};
+ 	};
++
++	/* 24AA025UID */
++	carrier_eeprom@52 {
++		compatible = "atmel,24c02";
++		reg = <0x52>;
++		pagesize = <8>;
++	};
++
++	/* M24C02-WMN6TP */
++	som_eeprom@53 {
++		compatible = "atmel,24c02";
++		reg = <0x53>;
++		pagesize = <16>;
++	};
+ };
+ 
+ &cp0_i2c1 {
+diff --git a/arch/arm/dts/cn9130-cf-pro.dts b/arch/arm/dts/cn9130-cf-pro.dts
+index fb37dd833d..6931818cf6 100644
+--- a/arch/arm/dts/cn9130-cf-pro.dts
++++ b/arch/arm/dts/cn9130-cf-pro.dts
+@@ -145,11 +145,7 @@
+ 	pinctrl-0 = <&cp0_i2c0_pins>;
+ 	status = "okay";
+ 	clock-frequency = <100000>;
+-	eeprom0: eeprom@50 {
+-                compatible = "atmel,24c64";
+-                reg = <0x53>;
+-                pagesize = <0x20>;
+-        };
++
+ 	/*
+ 	 * PCA9655 GPIO expander, up to 1MHz clock.
+ 	 *  0-CON3 CLKREQ#
+@@ -231,6 +227,20 @@
+ 			line-name = "m.2 devslp";
+ 		};
+ 	};
++
++	/* 24AA025UID */
++	carrier_eeprom@52 {
++		compatible = "atmel,24c02";
++		reg = <0x52>;
++		pagesize = <8>;
++	};
++
++	/* M24C02-WMN6TP */
++	som_eeprom@53 {
++		compatible = "atmel,24c02";
++		reg = <0x53>;
++		pagesize = <16>;
++	};
+ };
+ 
+ &cp0_i2c1 {

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0013-find-fdtfile-from-tlv-eeprom.patch

@@ -0,0 +1,143 @@
+From a4fce9816a992f26044cef488b2617d7006535c2 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 13 Mar 2022 12:42:28 +0200
+Subject: [PATCH] find fdtfile from tlv eeprom
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ board/Marvell/octeontx2_cn913x/board.c | 97 ++++++++++++++++++++++++++
+ configs/sr_cn913x_cex7_defconfig       |  2 +
+ 2 files changed, 99 insertions(+)
+
+diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
+index 27db37e86e..1e900d2aab 100644
+--- a/board/Marvell/octeontx2_cn913x/board.c
++++ b/board/Marvell/octeontx2_cn913x/board.c
+@@ -8,11 +8,13 @@
+ #include <common.h>
+ #include <console.h>
+ #include <dm.h>
++#include <env.h>
+ #include <i2c.h>
+ #include <asm/io.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/soc.h>
+ #include <power/regulator.h>
++#include <tlv_eeprom.h>
+ #ifdef CONFIG_BOARD_CONFIG_EEPROM
+ #include <mvebu/cfg_eeprom.h>
+ #endif
+@@ -121,8 +123,103 @@ static int init_bootcmd_console(void)
+ }
+ #endif
+ 
++/*
++ * Read TLV formatted data from eeprom.
++ * Only read as much data as indicated by the TLV header.
++ */
++// TODO: this should be a library function?!
++static bool get_tlvinfo_from_eeprom(int index, u8 *buffer, size_t length) {
++	struct tlvinfo_header *eeprom_hdr = (struct tlvinfo_header *) buffer;
++	struct tlvinfo_tlv *eeprom_tlv = (struct tlvinfo_tlv *) &buffer[sizeof(struct tlvinfo_header)];
++
++	if(length < TLV_INFO_HEADER_SIZE) {
++		pr_err("%s: buffer too small for tlv header!\n", __func__);
++		return false;
++	}
++	if(read_tlv_eeprom((void *)eeprom_hdr, 0, TLV_INFO_HEADER_SIZE, index) != 0) {
++		pr_err("%s: failed to read from eeprom!\n", __func__);
++		return false;
++	}
++	if(!is_valid_tlvinfo_header(eeprom_hdr)) {
++		pr_warn("%s: invalid tlv header!\n", __func__);
++		return false;
++	}
++	if(length - TLV_INFO_HEADER_SIZE < be16_to_cpu(eeprom_hdr->totallen)) {
++		pr_err("%s: buffer too small for tlv data!\n", __func__);
++		return false;
++	}
++	if(read_tlv_eeprom((void *)eeprom_tlv, sizeof(struct tlvinfo_header), be16_to_cpu(eeprom_hdr->totallen), index) != 0) {
++		pr_err("%s: failed to read from eeprom!\n", __func__);
++		return false;
++	}
++
++	return true;
++}
++
++static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
++	char cpu[5] = {0};
++	char carrier[8] = {0};
++	static u8 eeprom[TLV_INFO_MAX_LEN];
++	char sku[257];
++
++	for(int i = 0; i < 2;i++) {
++		// read eeprom
++		if(!get_tlvinfo_from_eeprom(i, eeprom, sizeof(eeprom))) {
++			pr_info("%s: failed to read eeprom %d\n", __func__, i);
++			continue;
++		}
++
++		// read sku
++		if(!tlvinfo_read_tlv(eeprom, TLV_CODE_PART_NUMBER, sku, sizeof(sku))) {
++			pr_warn("%s: could not find sku in eeprom\n", __func__);
++			continue;
++		}
++		pr_debug("%s: read sku %s\n", __func__, sku);
++
++		// parse sku - processor or carrier indicated at index 2-6
++		if(memcmp(&sku[2], "CFCB", 4) == 0) {
++			// Clearfog Base
++			strcpy(carrier, "cf-base");
++		} else if(memcmp(&sku[2], "CFCP", 4) == 0) {
++			// Clearfog Pro
++			strcpy(carrier, "cf-pro");
++		} else if(memcmp(&sku[2], "C", 1) == 0) {
++			// COM-Express 7 - C9130 / C9131 / C9132 ...
++			memcpy(cpu, &sku[3], 4);
++			strcpy(carrier, "cex7");
++		} else if(memcmp(&sku[2], "S9130", 4) == 0) {
++			// SoM - S9130 / S9131 / S9132 ...
++			memcpy(cpu, &sku[3], 4);
++		} else {
++			pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
++		}
++	}
++
++	if(!cpu[0]) {
++		pr_err("%s: could not identify SoC, defaulting to %s!\n", __func__, "CN9130");
++		strcpy(cpu, "9130");
++	}
++
++	if(!carrier[0]) {
++		pr_err("%s: could not identify carrier, defaulting to %s!\n", __func__, "Clearfog Pro");
++		strcpy(carrier, "cf-pro");
++	}
++
++	// assemble fdtfile
++	if(snprintf(buffer, length, "marvell/cn%s-%s.dtb", cpu, carrier) >= length) {
++		pr_err("%s: fdtfile buffer too small, result truncated!\n", __func__);
++	}
++}
++
+ int board_late_init(void)
+ {
++	char fdtfile[32] = {0};
++
++	// identify device
++	get_fdtfile_from_tlv_eeprom(fdtfile, sizeof(fdtfile));
++	if (!env_get("fdtfile"))
++		env_set("fdtfile", fdtfile);
++
+ #if CONFIG_IS_ENABLED(OCTEONTX_SERIAL_BOOTCMD)
+ 	if (init_bootcmd_console())
+ 		printf("Failed to init bootcmd input\n");
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index 307cefef65..f971d9d4d0 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -102,3 +102,5 @@ CONFIG_USB_ETHER_SMSC95XX=y
+ CONFIG_SMBIOS_MANUFACTURER=""
+ CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
++CONFIG_I2C_EEPROM=y
++CONFIG_CMD_TLV_EEPROM=y

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0014-octeontx2_cn913x-support-distro-boot.patch

@@ -0,0 +1,46 @@
+From 6516e51970deea70b79ebff44ad704b2be08e3fb Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Sun, 20 Mar 2022 15:02:03 +0200
+Subject: [PATCH] octeontx2_cn913x: support distro-boot
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ configs/sr_cn913x_cex7_defconfig   |  1 -
+ include/configs/octeontx2_cn913x.h | 12 ++++++++++++
+ 2 files changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index f971d9d4d0..30e51c0026 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -11,7 +11,6 @@ CONFIG_DEBUG_UART=y
+ CONFIG_AHCI=y
+ CONFIG_DISTRO_DEFAULTS=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+-CONFIG_BOOTCOMMAND="run get_images; run set_bootargs; booti $kernel_addr $ramfs_addr $fdt_addr"
+ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+ CONFIG_SYS_CONSOLE_INFO_QUIET=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
+index 2ae70e5efe..aa966bd292 100644
+--- a/include/configs/octeontx2_cn913x.h
++++ b/include/configs/octeontx2_cn913x.h
+@@ -35,6 +35,18 @@
+ 	func(PXE, pxe, na) \
+ 	func(DHCP, dhcp, na)
+ 
++#include <config_distro_bootcmd.h>
++
++#undef CONFIG_EXTRA_ENV_SETTINGS
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	"console=" CONFIG_DEFAULT_CONSOLE "\0"\
++	"kernel_addr_r=0x7000000\0" \
++	"fdt_addr_r=0x6f00000\0" \
++	"ramdisk_addr_r=0x9000000\0" \
++	"scriptaddr=0x6e00000\0" \
++	"pxefile_addr_r=0x6000000\0" \
++	BOOTENV
++
+ /* RTC configuration */
+ #ifdef CONFIG_MARVELL_RTC
+ #define ERRATA_FE_3124064

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0015-octeontx2_cn913x-remove-console-variable.patch

@@ -0,0 +1,35 @@
+From 03297ee2679e39da71dd39fb3076b305621c45d5 Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Tue, 22 Mar 2022 11:09:06 +0200
+Subject: [PATCH] octeontx2_cn913x: remove console variable
+
+console is now properly selected by chosen nodei n device-tree rather
+than through bootargs.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ include/configs/octeontx2_cn913x.h | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/include/configs/octeontx2_cn913x.h b/include/configs/octeontx2_cn913x.h
+index aa966bd292..d01644fcb5 100644
+--- a/include/configs/octeontx2_cn913x.h
++++ b/include/configs/octeontx2_cn913x.h
+@@ -8,9 +8,6 @@
+ #ifndef _CONFIG_OCTEONTX2_CN913X_H
+ #define _CONFIG_OCTEONTX2_CN913X_H
+ 
+-#define CONFIG_DEFAULT_CONSOLE		"console=ttyS0,115200 "\
+-					"earlycon=uart8250,mmio32,0xf0512000"
+-
+ #include <configs/mvebu_armada-common.h>
+ 
+ /*
+@@ -39,7 +36,6 @@
+ 
+ #undef CONFIG_EXTRA_ENV_SETTINGS
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+-	"console=" CONFIG_DEFAULT_CONSOLE "\0"\
+ 	"kernel_addr_r=0x7000000\0" \
+ 	"fdt_addr_r=0x6f00000\0" \
+ 	"ramdisk_addr_r=0x9000000\0" \

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0016-octeontx2_cn913x-enable-mmc-partconf-command.patch

@@ -0,0 +1,19 @@
+From 11a0fbc3e0ab35fbb5620e59fa65b201df26eabd Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Tue, 22 Mar 2022 11:12:12 +0200
+Subject: [PATCH] octeontx2_cn913x: enable mmc partconf command
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ configs/sr_cn913x_cex7_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index 30e51c0026..24219ef45d 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -103,3 +103,4 @@ CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_CMD_TLV_EEPROM=y
++CONFIG_SUPPORT_EMMC_BOOT=y

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0017-uboot-add-support-cn9131-cf-solidwan.patch

@@ -0,0 +1,783 @@
+From c6279eb32f1d4f295c8f0335f4586ff92d3e4439 Mon Sep 17 00:00:00 2001
+From: Alon Rotman <alon.rotman@solid-run.com>
+Date: Thu, 7 Jul 2022 21:58:29 +0300
+Subject: [PATCH] uboot: add support cn9131-cf-solidwan
+
+Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
+---
+ arch/arm/dts/Makefile                  |   7 +-
+ arch/arm/dts/armada-cp110.dtsi         |  14 +
+ arch/arm/dts/cn9130-cf-solidwan.dts    | 382 +++++++++++++++++++++++++
+ arch/arm/dts/cn9130-som.dtsi           |   9 +
+ arch/arm/dts/cn9131-cf-solidwan.dts    |  50 ++++
+ arch/arm/dts/cn9131-cf-solidwan.dtsi   | 214 ++++++++++++++
+ board/Marvell/octeontx2_cn913x/board.c |   8 +-
+ configs/sr_cn913x_cex7_defconfig       |   1 +
+ 8 files changed, 683 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm/dts/cn9130-cf-solidwan.dts
+ create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dts
+ create mode 100644 arch/arm/dts/cn9131-cf-solidwan.dtsi
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 246bd4665e..db8f42d94d 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -242,7 +242,12 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
+ 	cn9132-db-C.dtb				\
+ 	cn9132-cex7-A.dtb			\
+ 	cn9130-cf-pro.dtb			\
+-	cn9130-cf-base.dtb
++	cn9130-cf-base.dtb			\
++	cn9130-bldn-mbv.dtb                  	\
++	cn9131-bldn-mbv.dtb                     \
++	cn9130-cf-solidwan.dtb                  \
++        cn9131-cf-solidwan.dtb
++
+ 
+ dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
+ 	uniphier-ld11-global.dtb \
+diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
+index af55c5573d..6abe8f0bea 100644
+--- a/arch/arm/dts/armada-cp110.dtsi
++++ b/arch/arm/dts/armada-cp110.dtsi
+@@ -31,6 +31,11 @@
+ 			compatible = "simple-bus";
+ 			ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
+ 
++			
++/*			CP110_LABEL(ser1): ser@15
++
++*/
++
+ 			CP110_LABEL(mdio): mdio@12a200 {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+@@ -39,6 +44,15 @@
+ 				mdio-name = CP110_STRING_LABEL(mdio);
+ 				status = "disabled";
+ 			};
++			CP110_LABEL(mdio2): mdio@12a400 {
++                                #address-cells = <1>;
++                                #size-cells = <0>;
++                                compatible = "marvell,orion-mdio";
++                                reg = <0x12a200 0x10>;
++                                mdio-name = CP110_STRING_LABEL(mdio);
++                                status = "disabled";
++                        };
++
+ 
+ 			CP110_LABEL(xmdio): mdio@12a600 {
+ 				#address-cells = <1>;
+diff --git a/arch/arm/dts/cn9130-cf-solidwan.dts b/arch/arm/dts/cn9130-cf-solidwan.dts
+new file mode 100644
+index 0000000000..c26bb15af9
+--- /dev/null
++++ b/arch/arm/dts/cn9130-cf-solidwan.dts
+@@ -0,0 +1,382 @@
++/*
++ * Copyright (C) 2020 SolidRun ltd.
++ *
++ * SPDX-License-Identifier:    GPL-2.0
++ * https://spdx.org/licenses
++ */
++
++/* cn9130-cex7-A.dts */
++#include "cn9130-som.dtsi"
++
++/ {
++	model = "SolidRun CN9130 based SOM ClearFog SolidWAN ";
++	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
++		     "marvell,cn9030", "marvell,armada-ap806-quad",
++		     "marvell,armada-ap806", "marvell,armada70x0";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	aliases {
++		i2c0 = &cp0_i2c0;
++		i2c1 = &cp0_i2c1;
++		spi0 = &cp0_spi1;
++		gpio0 = &ap_gpio0;
++		gpio1 = &cp0_gpio0;
++		gpio2 = &cp0_gpio1;
++	};
++
++	memory@00000000 {
++		device_type = "memory";
++		reg = <0x0 0x0 0x0 0x80000000>;
++	};
++
++	cp0 {
++		config-space {
++			sdhci@780000 {
++				vqmmc-supply = <&cp0_reg_sd_vccq>;
++				vmmc-supply = <&cp0_reg_sd_vcc>;
++			};
++			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
++				compatible = "regulator-gpio";
++				regulator-name = "ap_mmc_vccq";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
++				states = <1800000 0x1
++					3300000 0x0>;
++			};
++			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
++				compatible = "regulator-fixed";
++				regulator-name = "cp_sd_vcc";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				status = "okay";
++			};
++			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
++				compatible = "regulator-gpio";
++				regulator-name = "cp0_sd_vccq";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
++				enable-active-high;
++				states = <1800000 0x1
++					3300000 0x0>;
++			};
++			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                regulator-name = "cp0-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
++                        };
++
++                        cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
++                                compatible = "regulator-fixed";
++                                regulator-name = "cp0-xhci1-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
++                        };
++
++		};
++		gpio@440100 {
++			p24 {
++				gpio-hog;
++				gpios = <24 GPIO_ACTIVE_HIGH>;
++				output-high;
++				line-name = "switch_reset";
++			};
++		};
++	};
++};
++
++
++/***** AP related configuration *****/
++&ap_pinctl {
++	/* MPP Bus:
++	 * SDIO  [0-10, 12]
++	 * UART0 [11,19]
++	 */
++		/*   0 1 2 3 4 5 6 7 8 9 */
++	pin-func = < 1 1 1 1 1 1 1 1 1 1
++		     1 3 1 0 0 0 0 0 0 3 >;
++};
++
++
++/* on-board eMMC */
++&ap_sdhci0 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
++        vqmmc-supply = <&ap_reg_mmc_vccq>;
++        bus-width = <8>;
++        status = "okay";
++};
++
++&uart0 {
++        status = "okay";
++};
++/*
++&cp0_uart1 {
++        status = "okay";
++	pinctrl-names = "default";
++        pinctrl-0 = <&cp0_uart1_pins>;	
++	u-boot,dm-pre-reloc;
++};
++*/
++
++/****** CP related configuration  ******/
++
++&cp0_pinctl {
++	/* MPP Bus:
++	*	[0-1] 	SMI MDC/MDIO
++	*	[2-3]	UART1 TX/RX
++	*	[4-5]	UART1 RTS/CTS
++	*	[6-8]	PTP
++	*	[10-11] GPIO - SPD Strap
++	*	[12-16]	SPI1
++	*	[17-26]	GPIO - Boot straps
++	*	[27-34]	GPIO
++	*	[35-36]	I2C1
++	*	[37-38]	I2C1
++	*	[39] 	GPIO
++	*	[40] 	RCVR CLK
++	*	[41]	GPIO VHV_EN
++	*	[43]	SD CARD DT
++	*	[44-55]	RGMII --> GPIOs
++	*	[56-61]	SDIO
++	*/
++		   /*   0   1   2   3   4   5   6   7   8   9 */
++	pin-func = <	10  10  8   8   6   6   0   0   0   0
++			0   0   3   3   3   3   3   0   0   0
++			0   0   0   0   0   0   0   0   0   0
++			0   0   0   0   0   2   2   2   2   0
++			0   0   0   0   0   0   0   0   0   0
++			0   0   0   0   0   0  0xe 0xe 0xe 0xe
++			0xe 0xe 0 >;
++};
++
++&cp0_i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_i2c0_pins>;
++	status = "okay";
++	clock-frequency = <100000>;
++	eeprom0: eeprom@53 {
++                compatible = "atmel,24c64";
++                reg = <0x53>;
++                pagesize = <0x20>;
++        };
++};
++
++&cp0_i2c1 {
++	/* connected to SFP0*/
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_i2c1_pins>;
++	clock-frequency = <100000>;
++};
++
++/* SD CARD */
++&cp0_sdhci0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_sdhci_pins
++		     &cp0_sdhci_cd_pins>;
++	bus-width = <4>;
++	status = "okay";
++	no-1-8-v;
++};
++
++/* SPI NOR  */
++&cp0_spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_spi1_pins
++		     &cp0_spi1_cs1_pins>;
++	reg =	<0x700680 0x50>,	/* control */
++		<0x2000000 0x1000000>,	/* CS0 */
++		<0x2000000 0x1000004>,	/* CS1 */
++		<0 0xffffffff>,		/* CS2 */
++		<0 0xffffffff>;		/* CS3 */
++	status = "okay";
++
++	spi-flash@0 {
++		#address-cells = <0x1>;
++		#size-cells = <0x1>;
++		compatible = "jedec,spi-nor", "spi-flash";
++		reg = <0x0>;
++		/* On-board MUX does not allow higher frequencies */
++		spi-max-frequency = <20000000>;
++	};
++	spi-flash@1 {
++                #address-cells = <0x1>;
++                #size-cells = <0x1>;
++                compatible = "jedec,spi-nor";
++                reg = <0x1>;
++                /* On carrier MUX does not allow higher frequencies */
++                spi-max-frequency = <20000000>;
++        };
++
++
++};
++
++&cp0_comphy {
++	phy0 {
++		phy-type = <COMPHY_TYPE_PEX0>;
++	};
++
++	phy1 {
++		phy-type = <COMPHY_TYPE_SGMII2>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++	};
++
++	phy2 {
++		phy-type = <COMPHY_TYPE_SFI0>;
++		phy-speed = <COMPHY_SPEED_10_3125G>;
++	};
++
++	phy3 {
++		phy-type = <COMPHY_TYPE_SGMII1>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++	};
++
++	phy4 {
++		phy-type = <COMPHY_TYPE_USB3_HOST1>;
++	};
++
++	phy5 {
++		phy-type = <COMPHY_TYPE_PEX2>;
++	};
++};
++
++&cp0_ethernet {
++        status = "okay";
++};
++
++/* SRDS #0 - PCIe X1 Gen3 M.2 Slot */
++&cp0_pcie0 {
++	num-lanes = <1>;
++	status = "okay";
++//	pinctrl-0 = <&cp0_pci0_reset_pins>;
++//	marvell,reset-gpio = <&cp0_gpio0 6 GPIO_ACTIVE_LOW>; //MPP6
++};
++
++/* SRDS #1 - 1GbE SGMII */
++&cp0_eth2 {
++        status = "okay";
++        phy-mode = "sgmii";
++        phy = <&cp0_phy1>;
++     //   phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
++};
++
++
++/* SRDS #2 - 10GE SFP+ */
++&cp0_eth0 {
++	status = "okay";
++	phy-mode = "sfi";
++	compatible = "sff,sfp";
++	i2c-bus = <&cp0_i2c1>;
++	los-gpio = <&cp0_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
++	mod-def0-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>; //MPP32
++	tx-disable-gpio = <&cp0_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
++	tx-fault-gpio = <&cp0_gpio0 31 GPIO_ACTIVE_HIGH>; //MPP31
++	maximum-power-milliwatt = <2000>;
++};
++
++/* SRDS #3 - 1GE PHY over SGMII */
++&cp0_eth1 {
++	status = "okay";
++	phy = <&cp0_phy0>;
++	phy-mode = "sgmii";
++//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //MPP39
++};
++
++/* SRDS #4 - USB 3.0 host on M.2 connector */
++&cp0_usb3_1 {
++	status = "okay";
++	vbus-supply = <&cp0_reg_usb3_vbus1>;
++};
++&cp0_utmi0 {
++        status = "okay";
++};
++&cp0_utmi1 {
++        status = "okay";
++};
++/*
++&cp0_usb3_0 {
++        status = "okay";
++	vbus-supply = <&cp0_reg_usb3_vbus0>;
++};
++*/
++
++/* SRDS #5 - mini PCIE slot */
++&cp0_pcie2 {
++	num-lanes = <1>;
++	status = "okay";
++//      pinctrl-0 = <&cp0_pci2_reset_pins>;
++//      marvell,reset-gpio = <&cp0_gpio0 8 GPIO_ACTIVE_LOW>; //MPP6
++};
++
++/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
++&cp0_mdio {
++	status = "okay";
++	pinctrl-0 = <&cp0_mdio_pins>;
++	cp0_phy0: ethernet-phy@0 {
++		marvell,reg-init = <3 16 0 0x1017>;
++		reg = <0>;
++	};
++	cp0_phy1: ethernet-phy@1 {
++		marvell,reg-init = <3 16 0 0x1017>;
++		reg = <1>;
++	};
++};
++
++&cp0_pinctl {
++	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
++	bank-name ="cp0-110";
++
++	cp0_i2c0_pins: cp0-i2c-pins-0 {
++		marvell,pins = < 37 38 >;
++		marvell,function = <2>;
++	};
++	cp0_i2c1_pins: cp0-i2c-pins-1 {
++		marvell,pins = < 35 36 >;
++		marvell,function = <2>;
++	};
++	cp0_sdhci_pins: cp0-sdhi-pins-0 {
++		marvell,pins = < 56 57 58 59 60 61 >;
++		marvell,function = <14>;
++	};
++	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
++		marvell,pins = < 43 >;
++		marvell,function = <1>;
++	};
++	cp0_spi1_pins: cp0-spi-pins-0 {
++		marvell,pins = < 13 14 15 16 >;
++		marvell,function = <3>;
++	};
++	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
++		marvell,pins = < 12 >;
++		marvell,function = <3>;
++	};
++	cp0_mdio_pins: cp0-mdio-pins {
++                marvell,pins = < 0 1 >;
++                marvell,function = <10>;
++        };
++	cp0_pci0_reset_pins: pci0-reset-pins {
++		marvell,pins = < 6 >;
++                marvell,function = <0>;
++        };
++	cp0_pci2_reset_pins: pci2-reset-pins {
++                marvell,pins = < 8 >;
++                marvell,function = <0>;
++        };
++	cp0_uart1_pins: cp0-uart1-pins {
++                marvell,pins = < 2 3 >;
++                marvell,function = <8>;
++        };
++};
+diff --git a/arch/arm/dts/cn9130-som.dtsi b/arch/arm/dts/cn9130-som.dtsi
+index 683821e0ea..ca69cd3ba0 100644
+--- a/arch/arm/dts/cn9130-som.dtsi
++++ b/arch/arm/dts/cn9130-som.dtsi
+@@ -12,6 +12,15 @@
+ #include "armada-ap807.dtsi"
+ #include "armada-ap80x-quad.dtsi"
+ 
++
++#undef CP110_NAME
++#undef CP110_NUM
++#undef CP110_PCIE_MEM_SIZE
++#undef CP110_PCIEx_CPU_MEM_BASE
++#undef CP110_PCIEx_BUS_MEM_BASE
++
++
++
+ /* This defines used to calculate the base address of each CP */
+ #define CP110_BASE_OFFSET		(0xf2000000)
+ #define CP110_SPACE_SIZE		(0x02000000)
+diff --git a/arch/arm/dts/cn9131-cf-solidwan.dts b/arch/arm/dts/cn9131-cf-solidwan.dts
+new file mode 100644
+index 0000000000..95c3aec3c5
+--- /dev/null
++++ b/arch/arm/dts/cn9131-cf-solidwan.dts
+@@ -0,0 +1,50 @@
++/*
++ * Copyright (C) 2020 SolidRun ltd.
++ *
++ * SPDX-License-Identifier:    GPL-2.0
++ * https://spdx.org/licenses
++ */
++
++/* cn9131-cex7-A */
++
++#include "cn9130-cf-solidwan.dts"
++#include "cn9131-cf-solidwan.dtsi"
++
++/ {
++	model = "Belden CN9131 based Platform";
++	compatible =	"marvell,cn9131-db", "marvell,armada-ap806-quad",
++			"marvell,armada-ap806";
++};
++
++&cp1_comphy {
++	/* Serdes Configuration:
++	*	Lane 0: PCIe
++	*	Lane 1: SATA
++	*	Lane 2: USB3
++	*	Lane 3: SGMII 
++	*	Lane 4: XFI
++	*	Lane 5: SGMII
++	*/
++	phy0 {
++		phy-type = <COMPHY_TYPE_PEX0>;
++	};
++	phy1 {
++		phy-type = <COMPHY_TYPE_SATA0>;
++	};
++	phy2 {
++		phy-type = <COMPHY_TYPE_USB3_HOST1>;
++	};
++	phy3 {	
++		phy-type = <COMPHY_TYPE_SGMII1>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++	};
++	phy4 {
++		phy-type = <COMPHY_TYPE_SFI0>;
++                phy-speed = <COMPHY_SPEED_10_3125G>;
++	};
++	phy5 {
++		phy-type = <COMPHY_TYPE_SGMII2>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++
++	};
++};
+diff --git a/arch/arm/dts/cn9131-cf-solidwan.dtsi b/arch/arm/dts/cn9131-cf-solidwan.dtsi
+new file mode 100644
+index 0000000000..5f2ee49850
+--- /dev/null
++++ b/arch/arm/dts/cn9131-cf-solidwan.dtsi
+@@ -0,0 +1,214 @@
++/*
++* Copyright (C) 2020 SolidRun ltd.
++*
++* SPDX-License-Identifier:    GPL-2.0
++* https://spdx.org/licenses
++*/
++
++/* Device Tree file for the cn1931 based belden mbv carrier board, cp1  */
++
++#undef CP110_NAME
++#undef CP110_NUM
++#undef CP110_PCIE_MEM_SIZE
++#undef CP110_PCIEx_CPU_MEM_BASE
++#undef CP110_PCIEx_BUS_MEM_BASE
++
++/* CP110-1 Settings */
++#define CP110_NAME                     cp1
++#define CP110_NUM                      1
++#define CP110_PCIE_MEM_SIZE(iface)     (0xf00000)
++#define CP110_PCIEx_CPU_MEM_BASE(iface)        (0xe2000000 + (iface) * 0x1000000)
++#define CP110_PCIEx_BUS_MEM_BASE(iface)        (CP110_PCIEx_CPU_MEM_BASE(iface))
++
++#include "armada-cp110.dtsi"
++
++/ {
++       model = "SolidRun CN9131 based SolidWan";
++       compatible = "marvell,cn9131-db";
++
++       aliases {
++               gpio3 = &cp1_gpio0;
++               gpio4 = &cp1_gpio1;
++               fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
++               fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
++       };
++
++	cp1 {
++                config-space {
++                        cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                pinctrl-names = "default";
++//                                pinctrl-0 = <&cp1_xhci0_vbus_pins>;
++                                regulator-name = "cp1-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
++                        };
++			cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                pinctrl-names = "default";
++//                                pinctrl-0 = <&cp1_xhci0_vbus_pins>;
++                                regulator-name = "cp1-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                //gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
++                        };
++
++                        cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
++                                compatible = "regulator-fixed";
++                                regulator-min-microamp = <900000>;
++                                regulator-max-microamp = <900000>;
++                                regulator-force-boot-off;
++//                                gpio = <&cp1_gpio0 5 GPIO_ACTIVE_HIGH>;
++                        };
++                };
++        };
++};
++&cp1_ld_efuse0 {
++       status = "disabled";
++};
++
++&cp1_ld_efuse1 {
++       status = "disabled";
++};
++
++&cp1_i2c1 {
++       pinctrl-names = "default";
++       pinctrl-0 = <&cp1_i2c1_pins>;
++       status = "okay";
++       clock-frequency = <100000>;
++};
++
++
++&cp1_utmi0 {
++        status = "okay";
++};
++&cp1_utmi1 {
++        status = "okay";
++};
++/*
++&cp1_usb3_1 {
++        status = "okay";
++	vbus-supply = <&cp1_reg_usb3_vbus1>;
++};
++*/
++&cp1_pcie0 {
++       pinctrl-names = "default";
++       status = "okay";
++       num-lanes = <1>;
++               /* non-prefetchable memory */
++   	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
++//        pinctrl-names = "default";
++//        marvell,reset-gpio = <&cp1_gpio0 29 GPIO_ACTIVE_LOW>;
++};
++
++&cp1_pinctl {
++       compatible = "marvell,mvebu-pinctrl",
++                    "marvell,cp115-standalone-pinctrl";
++       bank-name ="cp1-110";
++
++       /* MPP Bus:
++	*	[1:0]	UART0
++	*	[29:2]	NC
++	*	[30:29] GPIO - M.2 Power off
++	*	[32:31]	NC
++	*	[34:33] SFP GPIOs
++	*	[36:35] I2C
++	*	[38:37]	SMI
++	*	[41:40]	UART1
++	*	[48:42]	NC
++	*	[50:49] SFP GPIOs
++	*	[62:51]	NC
++	*/
++               /*      0    1    2    3    4    5    6    7    8    9 */
++       pin-func = <    0x8  0x8  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x2  0x2  0x7  0x7  0x0
++                       0x7  0x7  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0 >;
++
++	cp1_uart0_pins: cp1-uart0-pins-1 {
++               marvell,pins = < 0 1 >;
++               marvell,function = <8>;
++        };
++	cp1_uart1_pins: cp1-uart1-pins-1 {
++               marvell,pins = < 40 41 >;
++               marvell,function = <7>;
++        };
++		
++	cp1_i2c1_pins: cp1-i2c-pins-1 {
++               marvell,pins = < 35 36 >;
++               marvell,function = <2>;
++	};
++
++	cp1_mdio_pins: cp1-mdio-pins {
++                marvell,pins = < 37 38 >;
++                marvell,function = <7>;
++        };
++
++
++};
++
++&cp1_mdio2 {
++        status = "okay";
++	pinctrl-0 = <&cp1_mdio_pins>;	
++        cp1_phy0: ethernet-phy@0 {
++        	marvell,reg-init = <3 16 0 0x1017>;
++	        reg = <0>;
++        };
++        cp1_phy1: ethernet-phy@1 {
++		marvell,reg-init = <3 16 0 0x1017>;
++                reg = <1>;
++        };
++};
++
++/* SATA0  */
++&cp1_sata0 {
++       status = "okay";
++};
++
++&cp1_ethernet {
++        status = "okay";
++};
++
++&cp1_eth0 {
++        status = "okay";
++        phy-mode = "sfi";
++	compatible = "sff,sfp";
++        i2c-bus = <&cp1_i2c1>;
++        los-gpio = <&cp1_gpio1 2 GPIO_ACTIVE_HIGH>; //MPP34
++        mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
++        tx-disable-gpio = <&cp1_gpio1 1 GPIO_ACTIVE_HIGH>; //MPP33
++        tx-fault-gpio = <&cp1_gpio1 17 GPIO_ACTIVE_HIGH>; //MPP49
++        maximum-power-milliwatt = <2000>;
++};
++
++/* SERDES 3 SGMII */
++&cp1_eth1 {
++        status = "okay";
++        phy-mode = "sgmii";
++        phy = <&cp1_phy0>;
++//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
++};
++
++/* SERDES 5 SGMII */
++&cp1_eth2 {
++        status = "okay";
++        phy-mode = "sgmii";
++        phy = <&cp1_phy1>;
++//	phy-reset-gpios = <&cp0_gpio1 7 GPIO_ACTIVE_LOW>; //CP0 MPP39
++};
++
++/* M.2 LTE USB */
++&cp1_usb3_0 {
++        status = "okay";
++	vbus-supply = <&cp1_reg_usb3_vbus0>;
++};
++
++
+diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
+index 1e900d2aab..cfd8d5f5fd 100644
+--- a/board/Marvell/octeontx2_cn913x/board.c
++++ b/board/Marvell/octeontx2_cn913x/board.c
+@@ -188,8 +188,14 @@ static void get_fdtfile_from_tlv_eeprom(u8 *buffer, size_t length) {
+ 			memcpy(cpu, &sku[3], 4);
+ 			strcpy(carrier, "cex7");
+ 		} else if(memcmp(&sku[2], "S9130", 4) == 0) {
+-			// SoM - S9130 / S9131 / S9132 ...
++			// SoM - S9130
+ 			memcpy(cpu, &sku[3], 4);
++		} else if(memcmp(&sku[2], "CFSW", 4) == 0) {
++                        // SolidWan SOM S9131
++			strcpy(carrier, "cf-swn");
++		} else if(memcmp(&sku[2], "MBV", 3) == 0) {
++                        //BLDN MBV S9131
++                        strcpy(carrier, "bldn-mbv");
+ 		} else {
+ 			pr_err("%s: did not recognise SKU %s!\n", __func__, sku);
+ 		}
+diff --git a/configs/sr_cn913x_cex7_defconfig b/configs/sr_cn913x_cex7_defconfig
+index 24219ef45d..d7445e9476 100644
+--- a/configs/sr_cn913x_cex7_defconfig
++++ b/configs/sr_cn913x_cex7_defconfig
+@@ -104,3 +104,4 @@ CONFIG_CMD_MVEBU_PHY_FW_DOWNLOAD=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_CMD_TLV_EEPROM=y
+ CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_NET_RANDOM_ETHADDR=y

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/files/solidrun/0018-uboot-add-support-bldn-mbv.patch

@@ -0,0 +1,779 @@
+From 70b50e2ac9671cbda2e9efd7ebef37eec66b8332 Mon Sep 17 00:00:00 2001
+From: Alon Rotman <alon.rotman@solid-run.com>
+Date: Thu, 7 Jul 2022 21:59:29 +0300
+Subject: [PATCH] uboot: add support bldn-mbv
+
+Signed-off-by: Alon Rotman <alon.rotman@solid-run.com>
+---
+ arch/arm/dts/cn9130-bldn-mbv.dts  | 477 ++++++++++++++++++++++++++++++
+ arch/arm/dts/cn9131-bldn-mbv.dts  |  46 +++
+ arch/arm/dts/cn9131-bldn-mbv.dtsi | 223 ++++++++++++++
+ 3 files changed, 746 insertions(+)
+ create mode 100644 arch/arm/dts/cn9130-bldn-mbv.dts
+ create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dts
+ create mode 100644 arch/arm/dts/cn9131-bldn-mbv.dtsi
+
+diff --git a/arch/arm/dts/cn9130-bldn-mbv.dts b/arch/arm/dts/cn9130-bldn-mbv.dts
+new file mode 100644
+index 0000000000..9e10eab008
+--- /dev/null
++++ b/arch/arm/dts/cn9130-bldn-mbv.dts
+@@ -0,0 +1,477 @@
++/*
++ * Copyright (C) 2020 SolidRun ltd.
++ *
++ * SPDX-License-Identifier:    GPL-2.0
++ * https://spdx.org/licenses
++ */
++
++/* cn9130-som.dts */
++#include "cn9130-som.dtsi"
++
++/ {
++	model = "Belden CN9130 based SOM and Carrier MBV-A/B";
++	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
++		     "marvell,cn9030", "marvell,armada-ap806-quad",
++		     "marvell,armada-ap806", "marvell,armada70x0";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	aliases {
++		i2c0 = &cp0_i2c0;
++		i2c1 = &cp0_i2c1;
++		spi0 = &cp0_spi1;
++		gpio0 = &ap_gpio0;
++		gpio1 = &cp0_gpio0;
++		gpio2 = &cp0_gpio1;
++	};
++
++	memory@00000000 {
++		device_type = "memory";
++		reg = <0x0 0x0 0x0 0x80000000>;
++	};
++
++	cp0 {
++		config-space {
++			sdhci@780000 {
++				vqmmc-supply = <&cp0_reg_sd_vccq>;
++				vmmc-supply = <&cp0_reg_sd_vcc>;
++			};
++			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
++				compatible = "regulator-gpio";
++				regulator-name = "ap_mmc_vccq";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				gpios = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
++				states = <1800000 0x1
++					3300000 0x0>;
++			};
++			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
++				compatible = "regulator-fixed";
++				regulator-name = "cp_sd_vcc";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				status = "okay";
++			};
++			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
++				compatible = "regulator-gpio";
++				regulator-name = "cp0_sd_vccq";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				gpios = <&cp0_gpio1 26 GPIO_ACTIVE_HIGH>;
++				enable-active-high;
++				states = <1800000 0x1
++					3300000 0x0>;
++			};
++			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                regulator-name = "cp0-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                gpio = <&cp0_gpio0 26 GPIO_ACTIVE_HIGH>;
++                        };
++
++                        cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
++                                compatible = "regulator-fixed";
++                                regulator-name = "cp0-xhci1-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                                gpio = <&cp0_gpio0 1 GPIO_ACTIVE_HIGH>;
++                        };
++
++		};
++		gpio@440100 {
++			p24 {
++				gpio-hog;
++				gpios = <24 GPIO_ACTIVE_HIGH>;
++				output-high;
++				line-name = "switch_reset";
++			};
++		};
++	};
++};
++
++
++/***** AP related configuration *****/
++&ap_pinctl {
++	/* MPP Bus:
++	 * SDIO  [0-10, 12]
++	 * UART0 [11,19]
++	 */
++		/*   0 1 2 3 4 5 6 7 8 9 */
++	pin-func = < 1 1 1 1 1 1 1 1 1 1
++		     1 3 1 0 0 0 0 0 0 3 >;
++};
++
++
++/* on-board eMMC */
++&ap_sdhci0 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&ap_emmc_pins>; /*defined in armada-ap80x.dtsi */
++        vqmmc-supply = <&ap_reg_mmc_vccq>;
++        bus-width = <8>;
++        status = "okay";
++};
++
++&uart0 {
++        status = "okay";
++};
++/*
++&cp0_uart1 {
++        status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_uart1_pins>;
++	u-boot,dm-pre-reloc;
++};
++*/
++
++/****** CP related configuration  ******/
++
++&cp0_pinctl {
++	/* MPP Bus:
++	*	[0-1] 	SMI MDC/MDIO
++	*	[2-3]	UART1 TX/RX
++	*	[4-5]	UART1 RTS/CTS - NC on carrier board
++	*	[6-8]	PTP
++	*	[10-11] SPD Strap - GPIO
++	*	[12-16]	SPI1
++	*	[17-26]	Boot straps - GPIO
++	*	[35-36]	I2C1
++	*	[37-38]	I2C0
++	*	[40] 	RCVR CLK - NC
++	*	[41]	VHV_EN - GPIO
++	*	[43]	SD CARD DT
++	*	[44-55]	RGMII
++	*	[56-61]	SDIO
++
++	***** GPIOs connected to CPLD******
++	* 	[28]	RESET_VSC8504_PHY
++	*	[31]	CPLD_RESET_VSC8254_PHY
++	*	[32]    INT_RELEASE
++	*	[33]	CPLD_STATUS_INT
++	*	[34]	CPLD_PWR_INT
++	*	[39]    RESET_EMMC
++	*	[42]	CPLD_DONE
++	*	[43]	CPLD_PROG_N
++
++
++	*/
++		   /*   0   1   2   3   4   5   6   7   8   9 */
++	pin-func = <	0xa 0xa 8   8   6   6   9   9   9   0
++			0   0   3   3   3   3   3   0   0   0
++			0   0   0   0   0   0   0   0   0   0
++			0   0   0   0   0   2   2   2   2   0
++			2   0   0   1   1   1   1   1   1   1
++			1   1   1   1   1   1  0xe 0xe 0xe 0xe
++			0xe 0xe 0 >;
++};
++
++
++&cp0_i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_i2c0_pins>;
++	status = "okay";
++	clock-frequency = <100000>;
++	/* on som */
++	eeprom0: eeprom@53 {
++                compatible = "atmel,24c64";
++                reg = <0x53>;
++                pagesize = <0x20>;
++        };
++	/* on carrier */
++	eeprom1: eeprom@50 {
++                compatible = "i2c-eeprom";
++                reg = <0x50>;
++                pagesize = <0x16>;
++        };
++
++};
++
++&cp0_i2c1 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_i2c1_pins>;
++	clock-frequency = <100000>;
++	rtc: rtc@68 {
++                reg = <68>;
++		compatible = "dallas,ds1339";
++                /*connected to rtc DS1339U-33+*/
++	};
++	i2c-switch@e6 {
++                compatible = "nxp,pca9543";
++                reg = <0xe6>;
++                #address-cells = <1>;
++                #size-cells = <0>;
++		i2c_sfp0: i2c@0 {
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++                        reg = <0>;
++                        /*connected to sfp cp0_eth0*/
++		};
++		i2c_sfp1: i2c@1 {
++                        #address-cells = <1>;
++                        #size-cells = <0>;
++                        reg = <1>;
++                        /*connected to sfp cp1_eth1*/
++		};
++	};
++	temp_sns:temp_sense@40 {
++		reg = <40>;
++
++	};
++};
++
++/* SD CARD */
++&cp0_sdhci0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_sdhci_pins
++		     &cp0_sdhci_cd_pins>;
++	bus-width = <4>;
++	status = "okay";
++	no-1-8-v;
++	max-frequency = <25000000>;
++};
++
++/* SPI NOR  */
++&cp0_spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp0_spi1_pins
++		     &cp0_spi1_cs1_pins>;
++	reg =	<0x700680 0x50>,	/* control */
++		<0x2000000 0x1000000>,	/* CS0 */
++		<0x2000000 0x1000004>,	/* CS1 */
++		<0 0xffffffff>,		/* CS2 */
++		<0 0xffffffff>;		/* CS3 */
++	status = "okay";
++
++	spi-flash@0 {
++		#address-cells = <0x1>;
++		#size-cells = <0x1>;
++		compatible = "jedec,spi-nor", "spi-flash";
++		reg = <0>;
++		spi-max-frequency = <20000000>;
++	};
++};
++
++&cp0_comphy {
++	phy0 {
++		phy-type = <COMPHY_TYPE_PEX0>;
++	};
++
++	phy1 {
++		phy-type = <COMPHY_TYPE_SGMII2>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++	};
++
++	phy2 {
++		phy-type = <COMPHY_TYPE_SFI0>;
++		phy-speed = <COMPHY_SPEED_10_3125G>;
++	};
++
++	phy3 {
++		phy-type = <COMPHY_TYPE_SGMII1>;
++                phy-speed = <COMPHY_SPEED_1_25G>;
++	};
++
++	phy4 {
++		phy-type = <COMPHY_TYPE_PEX1>;
++	};
++
++	phy5 {
++		phy-type = <COMPHY_TYPE_PEX2>;
++	};
++};
++
++&cp0_sata0 {
++	status = "disabled";
++};
++
++&cp0_usb3_0 {
++	status = "disabled";
++};
++
++
++&cp0_utmi0 {
++        status = "okay";
++};
++&cp0_utmi1 {
++        status = "okay";
++};
++
++&cp0_ethernet {
++        status = "okay";
++};
++
++
++/* SRDS #0 - PCIe X1 mPCIe #0 */
++&cp0_pcie0 {
++        num-lanes = <1>;
++        status = "okay";
++};
++
++/* SRDS #1 - SGMII connected to VSC8584 1GbE PHY */
++&cp0_eth2 {
++        status = "okay";
++//        phy = <&cp0_vsc_phy19>; //address 0x0011001
++        phy-mode = "sgmii";
++};
++
++/* SRDS #2 - 10GE SFP+ */
++&cp0_eth0 {
++	status = "okay";
++	phy-mode = "sfi";
++	compatible = "sff,sfp";
++
++	/* for SFP direct connectivity */
++//	i2c-bus = <&i2c_sfp0>;
++//	mod-def0-gpio = <&cp0_gpio0 27 GPIO_ACTIVE_LOW>;
++
++	/* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
++//	phy = <&cp0_sfi_phy8>; //address 0x01000
++};
++
++/* SRDS #3 - SGMII connected to VSC8584 1GbE PHY */
++
++&cp0_eth1 {
++	status = "okay";
++//	phy = <&cp0_vsc_phy18>; //address 0x0011000
++	phy-mode = "sgmii";
++//	phy = <&cp0_phy0>; //  only for testing on cf-solidwan - to be removed for final dtb  
++};
++
++/* SRDS #4 - Extenssion conector */
++&cp0_pcie1 {
++	num-lanes = <1>;
++	status = "okay";
++};
++
++/* SRDS #5 - Extenssion connector */
++&cp0_pcie2 {
++	num-lanes = <1>;
++	status = "okay";
++};
++
++/* CP0 MDIO connected to local SOM 1Gbps phy and carrier 88E1512 phy */
++&cp0_mdio {
++	status = "disabled";
++        pinctrl-0 = <&cp0_mdio_pins>;
++
++	/**  only for testing on cf-solidwan - to be removed for final dtb */
++/*	cp0_phy0: ethernet-phy@0 {
++                marvell,reg-init = <3 16 0 0x1017>;
++                reg = <0>;
++        };
++	cp0_phy1: ethernet-phy@0 {
++                marvell,reg-init = <3 16 0 0x1017>;
++                reg = <0>;
++        };
++*/
++
++};
++
++&cp0_gpio0{
++	phy_vsc8504_phy_reset { 
++		gpio-hog;
++		gpios = <28 GPIO_ACTIVE_HIGH>;
++		output-high;
++		line-name = "phy_vsc8504_phy_reset";
++	};
++	phy_vsc8254_phy_reset { 
++                gpio-hog;
++                gpios = <31 GPIO_ACTIVE_HIGH>;
++                output-high;
++                line-name = "phy_vsc8254_phy_reset";
++        };
++};
++
++&cp0_gpio1{
++	cpld_int_release {
++                gpio-hog;
++                gpios = <0 GPIO_ACTIVE_HIGH>; //MPP32
++                output-high;
++                line-name = "cpld_int_release";
++        };
++	cpld_status_int {
++                gpio-hog;
++                gpios = <1 GPIO_ACTIVE_HIGH>; //MPP33
++                output-high;
++                line-name = "cpld_status_int";
++        };
++	cpld_pwr_int {
++                gpio-hog;
++                gpios = <2 GPIO_ACTIVE_HIGH>; //MPP34
++                output-high;
++                line-name = "cpld_pwr_int";
++        };
++	cpld_reset_emmc{
++                gpio-hog;
++                gpios = <7 GPIO_ACTIVE_HIGH>; //MPP39
++                output-high;
++                line-name = "cpld_reset_emmc";
++        };
++	cpld_done {
++                gpio-hog;
++                gpios = <10 GPIO_ACTIVE_HIGH>; //MPP42
++                input;
++                line-name = "cpld_done";
++        };
++	cpld_prog_n {
++                gpio-hog;
++                gpios = <11 GPIO_ACTIVE_HIGH>; //MPP43
++                output-high;
++                line-name = "cpld_prog_n";
++	};
++};
++
++&cp0_pinctl {
++	compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
++	bank-name ="cp0-110";
++
++	cp0_i2c0_pins: cp0-i2c-pins-0 {
++		marvell,pins = < 37 38 >;
++		marvell,function = <2>;
++	};
++	cp0_i2c1_pins: cp0-i2c-pins-1 {
++		marvell,pins = < 35 36 >;
++		marvell,function = <2>;
++	};
++	cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
++                marvell,pins = < 44 45 46 47 48 49 50 51
++                                52 53 54 55 >;
++                marvell,function = <1>;
++	};
++	cp0_sdhci_pins: cp0-sdhi-pins-0 {
++		marvell,pins = < 56 57 58 59 60 61 >;
++		marvell,function = <14>;
++	};
++	cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
++		marvell,pins = < 43 >;
++		marvell,function = <1>;
++	};
++	cp0_spi1_pins: cp0-spi-pins-0 {
++		marvell,pins = < 13 14 15 16 >;
++		marvell,function = <3>;
++	};
++	cp0_spi1_cs1_pins: cp0-spi-cs1-pins-0 {
++		marvell,pins = < 12 >;
++		marvell,function = <3>;
++	};
++	cp0_mdio_pins: cp0-mdio-pins {
++                marvell,pins = < 0 1 >;
++                marvell,function = <10>;
++        };
++	cp0_ptp_pins: cp0-ptp-pins {
++		marvell,pins = < 6 7 8 >;
++		marvell,function = <9>;
++	};
++	cp0_uart1_pins: cp0-uart1-pins {
++                marvell,pins = < 2 3 >;
++                marvell,function = <8>;
++        };
++};
+diff --git a/arch/arm/dts/cn9131-bldn-mbv.dts b/arch/arm/dts/cn9131-bldn-mbv.dts
+new file mode 100644
+index 0000000000..d10c7f032e
+--- /dev/null
++++ b/arch/arm/dts/cn9131-bldn-mbv.dts
+@@ -0,0 +1,46 @@
++/*
++ * Copyright (C) 2020 SolidRun ltd.
++ *
++ * SPDX-License-Identifier:    GPL-2.0
++ * https://spdx.org/licenses
++ */
++
++/* cn9131-bldn mbv-a/b */
++#include "cn9130-bldn-mbv.dts"
++#include "cn9131-bldn-mbv.dtsi"
++
++/ {
++	model = "Belden CN9131 based Platform";
++	compatible =	"marvell,cn9131-db", "marvell,armada-ap806-quad",
++			"marvell,armada-ap806";
++};
++
++&cp1_comphy {
++	/* Serdes Configuration:
++	*	Lane 0: PCIe0 (x1)
++	*	Lane 1: USB3
++	*	Lane 2: ETH PORT 10GE
++	*	Lane 3: NC
++	*	Lane 4: PCIE1 X1
++	*	Lane 5: PCIe2 X1
++	*/
++	phy0 {
++		phy-type = <COMPHY_TYPE_PEX0>;
++	};
++	phy1 {
++		phy-type = <COMPHY_TYPE_USB3_HOST0>;
++	};
++	phy2 {
++		phy-type = <COMPHY_TYPE_SFI0>;
++		phy-speed = <COMPHY_SPEED_10_3125G>;
++	};
++	phy3 {
++		phy-type = <COMPHY_TYPE_SATA1>;
++	};
++	phy4 {
++		phy-type = <COMPHY_TYPE_PEX1>;
++	};
++	phy5 {
++		phy-type = <COMPHY_TYPE_PEX2>;
++	};
++};
+diff --git a/arch/arm/dts/cn9131-bldn-mbv.dtsi b/arch/arm/dts/cn9131-bldn-mbv.dtsi
+new file mode 100644
+index 0000000000..afd63d8ba6
+--- /dev/null
++++ b/arch/arm/dts/cn9131-bldn-mbv.dtsi
+@@ -0,0 +1,223 @@
++/*
++* Copyright (C) 2020 SolidRun ltd.
++*
++* SPDX-License-Identifier:    GPL-2.0
++* https://spdx.org/licenses
++*/
++
++/* Device Tree file for the cn1931 based belden mbv carrier board, cp1  */
++
++#undef CP110_NAME
++#undef CP110_NUM
++#undef CP110_PCIE_MEM_SIZE
++#undef CP110_PCIEx_CPU_MEM_BASE
++#undef CP110_PCIEx_BUS_MEM_BASE
++
++/* CP110-1 Settings */
++#define CP110_NAME                     cp1
++#define CP110_NUM                      1
++#define CP110_PCIE_MEM_SIZE(iface)     (0xf00000)
++#define CP110_PCIEx_CPU_MEM_BASE(iface)        (0xe2000000 + (iface) * 0x1000000)
++#define CP110_PCIEx_BUS_MEM_BASE(iface)        (CP110_PCIEx_CPU_MEM_BASE(iface))
++
++#include "armada-cp110.dtsi"
++/ {
++       model = "Belden CN9131 based MBV-A/B";
++       compatible = "marvell,cn9131-db";
++
++       aliases {
++               gpio3 = &cp1_gpio0;
++               gpio4 = &cp1_gpio1;
++               fuse5 = &cp1_ld_efuse0; /* bank 68 RO */
++               fuse6 = &cp1_ld_efuse1; /* bank 69 RW */
++       };
++	cp1 {
++                config-space {
++                        cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                pinctrl-names = "default";
++                                regulator-name = "cp1-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                        };
++                        cp1_reg_usb3_vbus1: cp1_usb3_vbus@0 {
++                                compatible = "regulator-fixed";
++                                pinctrl-names = "default";
++                                regulator-name = "cp1-xhci0-vbus";
++                                regulator-min-microvolt = <5000000>;
++                                regulator-max-microvolt = <5000000>;
++                                startup-delay-us = <100000>;
++                                regulator-force-boot-off;
++                        };
++
++                        cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
++                                compatible = "regulator-fixed";
++                                regulator-min-microamp = <900000>;
++                                regulator-max-microamp = <900000>;
++                                regulator-force-boot-off;
++                        };
++                };
++        };
++};
++
++&cp1_ld_efuse0 {
++       status = "disabled";
++};
++
++&cp1_ld_efuse1 {
++       status = "disabled";
++};
++
++&cp1_i2c1 {
++       pinctrl-names = "default";
++       pinctrl-0 = <&cp1_i2c1_pins>;
++       status = "okay";
++       clock-frequency = <100000>;
++};
++
++&cp1_utmi0 {
++        status = "okay";
++};
++&cp1_utmi1 {
++        status = "okay";
++};
++
++&cp1_usb3_0 {
++        status = "disabled";
++};
++
++&cp1_xmdio {
++        status = "okay";
++        pinctrl-0 = <&cp1_xmdio_pins>;
++	cp0_sfi_phy8: ethernet-phy@8 {
++                reg = <8>;
++        };
++	cp1_sfi_phy9: ethernet-phy@9 {
++                reg = <9>;
++        };
++};
++
++&cp1_mdio {
++        status = "okay";
++        pinctrl-0 = <&cp1_mdio_pins>;
++        cp0_vsc_phy18: ethernet-phy@18 {
++                reg = <18>;
++        };
++	cp0_vsc_phy19: ethernet-phy@19 {
++                reg = <19>;
++        };
++};
++
++
++&cp1_pinctl {
++       compatible = "marvell,mvebu-pinctrl",
++                    "marvell,cp115-standalone-pinctrl";
++       bank-name ="cp1-110";
++
++       /* MPP Bus:
++	*	[3:2]	xmdio
++	*	[5:4]	mdio
++	*	[36:35]	i2c1
++	*	[43:40]	rs232
++	*/
++               /*      0    1    2    3    4    5    6    7    8    9 */
++       pin-func = <    0x0  0x0  0xa  0xa  0xa  0xa  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0	0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x2  0x2  0x0  0x0  0x0
++                       0x7  0x7  0x7  0x7  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0  0x0
++                       0x0  0x0  0x0 >;
++
++	cp1_i2c1_pins: cp1-i2c-pins-1 {
++		marvell,pins = < 35 36 >;
++		marvell,function = <2>;
++	};
++	cp1_xmdio_pins: cp1-xmdio-pins-0 {
++               marvell,pins = < 2 3 >;
++               marvell,function = <10>;
++	};
++	cp1_mdio_pins: cp1-mdio-pins-0 {
++               marvell,pins = < 4 5 >;
++               marvell,function = <10>;
++        };
++	cp1_uart1_pins: cp1-uart1-pins-0 {
++               marvell,pins = < 40 41 42 43 >;
++               marvell,function = <7>;
++        };
++};
++
++/* SATA0  */
++&cp1_sata0 {
++       status = "disabled";
++};
++
++&cp1_ethernet {
++        status = "okay";
++};
++
++/* SRDS #0 - PCIe Extenssion card */
++&cp1_pcie0 {
++	pinctrl-names = "default";
++        num-lanes = <1>;
++        status = "okay";
++	ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
++};
++
++/* SRDS #1 - USB Extenssion card */
++&cp1_usb3_0 {
++        status = "okay";
++        vbus-supply = <&cp1_reg_usb3_vbus0>;
++};
++
++/* SRDS #2 - 10GE SFP+ */
++&cp1_eth0 {
++        status = "okay";
++        phy-mode = "sfi";
++        compatible = "sff,sfp";
++
++        /* for SFP direct connectivity */
++//      i2c-bus = <i2c_sfp1>;
++//      mod-def0-gpio = <&cp1_gpio1 18 GPIO_ACTIVE_LOW>; //MPP50
++//	compatible = "sff,sfp";
++//	maximum-power-milliwatt = <2000>;
++
++        /* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
++        phy = <&cp1_sfi_phy9>; //address 0x01001
++
++};
++
++/* SRDS #3 - not in use */ 
++
++
++/* SRDS #4 - mPCIe */
++&cp1_pcie1 {
++        num-lanes = <1>;
++        status = "okay";
++};
++
++/* SRDS #5 - mPCIe */
++&cp1_pcie2 {
++        num-lanes = <1>;
++        status = "okay";
++};
++
++/*************** definitions of addresses for cp0 eth ports ************/
++
++&cp0_eth0 {
++        status = "okay";
++	phy = <&cp0_sfi_phy8>; //address 0x01000
++};
++
++&cp0_eth1 {
++        status = "okay";
++        phy = <&cp0_vsc_phy18>; //address 0x0011000
++};
++
++&cp0_eth2 {
++        status = "okay";
++        phy = <&cp0_vsc_phy19>; //address 0x0011001
++};
++

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/u-boot_2019.10-solidrun.bb

@@ -0,0 +1,63 @@
+HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome"
+DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \
+ARM, MIPS and several other processors, which can be installed in a boot \
+ROM and used to initialize and test the hardware or to download and run \
+application code."
+SECTION = "bootloaders"
+DEPENDS += "flex-native bison-native"
+
+COMPATIBLE_MACHINE = "cn913x"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e"
+PE = "1"
+
+# We use the revision in order to avoid having to fetch it from the
+# repo during parse
+SRCREV = "61ba1244b548463dbfb3c5285b6b22e7c772c5bd"
+
+# Patch from https://github.com/SolidRun/cn913x_build
+# Git SHA: f33e2aeb01c7ee061be7b053035ae87ce30fce4a
+SRC_URI = "git://git.denx.de/u-boot.git;branch=master \
+           file://solidrun/0001-cmd-add-tlv_eeprom-command.patch \
+           file://solidrun/0002-cmd-tlv_eeprom.patch \
+           file://solidrun/0003-cmd-tlv_eeprom-remove-use-of-global-variable-current.patch \
+           file://solidrun/0004-cmd-tlv_eeprom-remove-use-of-global-variable-has_bee.patch \
+           file://solidrun/0005-cmd-tlv_eeprom-do_tlv_eeprom-stop-using-non-api-read.patch \
+           file://solidrun/0006-cmd-tlv_eeprom-convert-functions-used-by-command-to-.patch \
+           file://solidrun/0007-cmd-tlv_eeprom-remove-empty-function-implementations.patch \
+           file://solidrun/0008-cmd-tlv_eeprom-split-off-tlv-library-from-command.patch \
+           file://solidrun/0009-lib-tlv_eeprom-add-function-for-reading-one-entry-in.patch \
+           file://solidrun/0010-uboot-marvell-patches.patch \
+           file://solidrun/0011-uboot-support-cn913x-solidrun-paltfroms.patch \
+           file://solidrun/0012-add-SoM-and-Carrier-eeproms.patch \
+           file://solidrun/0013-find-fdtfile-from-tlv-eeprom.patch \
+           file://solidrun/0014-octeontx2_cn913x-support-distro-boot.patch \
+           file://solidrun/0015-octeontx2_cn913x-remove-console-variable.patch \
+           file://solidrun/0016-octeontx2_cn913x-enable-mmc-partconf-command.patch \
+           file://solidrun/0017-uboot-add-support-cn9131-cf-solidwan.patch \
+           file://solidrun/0018-uboot-add-support-bldn-mbv.patch \
+           file://0001-Remove-redundant-YYLOC-global-declaration.patch \
+           file://0001-sr_cn913x_cex7-enable-more-image-formats.patch \
+           file://0021-octeontx2_cn913x-increase-CONFIG_SYS_BOOTM_LEN-to-32.patch \
+           file://0001-sr_cn913x_cex7-enable-VERSION_VARIABLE.patch \
+           file://cn913x.cfg \
+           file://0001-cn9130-fix-compatible-node-inside-dts.patch \
+           file://0001-cn9130-fix-compatible-node-inside-dts-pt-2.patch \
+           "
+
+S = "${WORKDIR}/git"
+
+require recipes-bsp/u-boot/u-boot.inc
+require recipes-bsp/u-boot/u-boot-coreos.inc
+
+# Solidrun patches require to build out-of-the-tree
+B = "${WORKDIR}/build"
+
+DEPENDS += "bc-native dtc-native u-boot-mkimage-native"
+
+do_compile:prepend() {
+    export DEVICE_TREE="${UBOOT_BUILDENV_DEVICE_TREE}"
+}
+
+SYSROOT_DIRS +=  " /boot "

layers/meta-belden-marvell-bsp/recipes-bsp/u-boot/u-boot_2023.04-marvell.bb

@@ -1,42 +0,0 @@
-HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome"
-DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \
-ARM, MIPS and several other processors, which can be installed in a boot \
-ROM and used to initialize and test the hardware or to download and run \
-application code."
-SECTION = "bootloaders"
-DEPENDS += "flex-native bison-native"
-
-COMPATIBLE_MACHINE = "cn913x"
-
-LICENSE = "GPL-2.0-or-later"
-LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1"
-PE = "1"
-
-# We use the revision in order to avoid having to fetch it from the
-# repo during parse
-SRCREV = "6add83991b2887619d0b25e4068b4c0082a4596a"
-
-# Patch from https://github.com/SolidRun/cn913x_build
-# Git SHA: f33e2aeb01c7ee061be7b053035ae87ce30fce4a
-SRC_URI = "git://source.denx.de/u-boot/custodians/u-boot-marvell.git;branch=master;protocol=https \
-           ${@bb.utils.contains("IMAGE_FEATURES", "debug-tweaks", "file://debug-tweaks.cfg", "", d)} \
-           file://uefi.cfg \
-           file://uefi-secureboot.cfg \
-           file://0001-add-support-for-cn9130-cf-pro-and-cn9130-bldn-mbv.patch \
-           "
-
-S = "${WORKDIR}/git"
-
-require recipes-bsp/u-boot/u-boot.inc
-require recipes-bsp/u-boot/u-boot-coreos.inc
-
-# Solidrun patches require to build out-of-the-tree
-B = "${WORKDIR}/build"
-
-DEPENDS += "bc-native dtc-native u-boot-mkimage-native"
-
-do_compile:prepend() {
-    export DEVICE_TREE="${UBOOT_BUILDENV_DEVICE_TREE}"
-}
-
-SYSROOT_DIRS +=  " /boot "

layers/meta-belden-marvell-bsp/recipes-kernel/linux/linux-netmodule/cn9131_linux_copper_and_sfp.patch

@@ -0,0 +1,125 @@
+diff --git a/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts b/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
+index 42faebf55e28..0eb60884810a 100644
+--- a/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
++++ b/arch/arm64/boot/dts/marvell/cn9130-bldn-mbv.dts
+@@ -96,7 +96,7 @@ cp0_sfp_eth0: sfp-eth@0 {
+ 		compatible = "sff,sfp";
+ 		i2c-bus = <&i2c_sfp0>;
+ 		mod-def0-gpio = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>; //MPP27
+-		//maximum-power-milliwatt = <2000>;
++		maximum-power-milliwatt = <2000>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&sfp_cp0_eth0_present_pins>;
+ 	};
+@@ -173,7 +173,7 @@ rtc: rtc@68 {
+                 /*connected to rtc DS1339U-33+*/
+         };
+         i2c-switch@73 {
+-                compatible = "nxp,pca9544";
++                compatible = "nxp,pca9543";
+                 reg = <0x73>;
+                 #address-cells = <1>;
+                 #size-cell = <0>;
+@@ -246,11 +246,7 @@ &cp0_eth0 {
+ 	managed = "in-band-status";
+ 
+ 	/* for SFP direct connectivity */
+-//      sfp = <&cp0_sfp_eth0>;
+-
+-        /* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+-//      phy = <&cp0_sfi_phy8>; //address 0x01000
+-
++        sfp = <&cp0_sfp_eth0>;
+ };
+ 
+ /* SRDS #3 - SGMII 1GE on carrier board */
+@@ -303,6 +299,13 @@ spi-flash@0 {
+ 		reg = <0x0>;
+ 		spi-max-frequency = <10000000>;
+ 	};
++        spi-cpld@1 {
++                compatible = "rohm,dh2228fv";
++                reg = <0x1>;
++                #address-cells = <1>;
++                #size-cells = <0>;
++                spi-max-frequency = <10000000>;
++       };
+ };
+ 
+ &cp0_syscon0 {
+diff --git a/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts b/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
+index b0140000141c..fe93f180e4ac 100644
+--- a/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
++++ b/arch/arm64/boot/dts/marvell/cn9131-bldn-mbv.dts
+@@ -42,7 +42,7 @@ cp1_usb3_0_phy1: cp1_usb3_phy@1 {
+ 	};
+ 	cp1_sfp_eth0: sfp_eth0{
+ 		compatible = "sff,sfp";
+-	//	i2c-bus = <&i2c_sfp1>;
++		i2c-bus = <&i2c_sfp1>;
+                 mod-def0-gpio = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>; //MPP50
+                 maximum-power-milliwatt = <2000>;
+                 pinctrl-0 = <&sfp_cp1_present_pins>; 
+@@ -104,10 +104,7 @@ &cp1_eth0 {
+         managed = "in-band-status";
+ 
+ 	/* for SFP direct connectivity */
+-//	sfp = <&cp1_sfp_eth0>;
+-        
+-	/* MBV-A BCM PHY  | MBV-B VSC Microchip PHY */
+-	phy = <&cp1_sfi_phy9>; //address 0x01001
++	sfp = <&cp1_sfp_eth0>;
+ };
+ 
+ /* SRDS #3 - NC */
+@@ -142,25 +139,14 @@ &cp1_gpio2 {
+ 	status = "okay";
+ };
+ 
+-&cp1_xmdio {
+-        status = "okay";
+- 	pinctrl-0 = <&cp1_xmdio_pins>;
+-        cp0_sfi_phy8: ethernet-phy@8 {
+-                reg = <8>;
+-        };
+-        cp1_sfi_phy9: ethernet-phy@9 {
+-                reg = <9>;
+-        };
+-};
+-
+ &cp1_mdio {
+         status = "okay";
+         pinctrl-0 = <&cp1_mdio_pins>;
+         cp0_vsc_phy18: ethernet-phy@18 {
+-                reg = <18>;
++                reg = <0x18>;
+         };
+         cp0_vsc_phy19: ethernet-phy@19 {
+-                reg = <19>;
++                reg = <0x19>;
+         };
+ 
+ };
+@@ -237,18 +223,15 @@ cp1_uart1_pins: cp1-uart1-pins-1 {
+ 
+ /*************** definitions of addresses for cp0 eth ports ************/
+ 
+-&cp0_eth0 {
+-        status = "okay";
+-        phy = <&cp0_sfi_phy8>; //address 0x01000
+-};
+-
+ &cp0_eth1 {
+         status = "okay";
+         phy = <&cp0_vsc_phy18>; //address 0x0011000
++        managed = "auto";
+ };
+ 
+ &cp0_eth2 {
+         status = "okay";
+         phy = <&cp0_vsc_phy19>; //address 0x0011001
++        managed = "auto";
+ };
+-                                                   
++                                                   
+\ No newline at end of file

layers/meta-belden-marvell-bsp/recipes-kernel/linux/linux-netmodule/cn913x_additions.cfg

@@ -0,0 +1,172 @@
+CONFIG_NET_DSA_MV88E6XXX=m
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_NET_DSA=m
+CONFIG_SENSORS_PWM_FAN=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SFP=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MARVELL_10G_PHY=y
+CONFIG_SENSORS_MCP3021=y
+CONFIG_EEPROM_AT24=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ACPI_CPPC_CPUFREQ=y
+CONFIG_ARM_ARMADA_8K_CPUFREQ=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_QRTR_MHI=m
+CONFIG_MHI_BUS=m
+CONFIG_ATH11K=m
+CONFIG_ATH11K_AHB=m
+CONFIG_ATH11K_PCI=m
+CONFIG_ATH11K_DEBUG=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_R8169=y
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_TASKS_RUDE_RCU=y
+CONFIG_BOOT_CONFIG=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_ACPI_APEI_PCIEAER is not set
+CONFIG_UPROBES=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+# CONFIG_NET_DROP_MONITOR is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_CFG80211_WEXT_EXPORT=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+CONFIG_LIB80211_DEBUG=y
+CONFIG_MAC80211_DEBUGFS=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_MAC80211_DEBUG_MENU=y
+# CONFIG_MAC80211_NOINLINE is not set
+CONFIG_MAC80211_VERBOSE_DEBUG=y
+# CONFIG_MAC80211_MLME_DEBUG is not set
+CONFIG_MAC80211_STA_DEBUG=y
+# CONFIG_MAC80211_HT_DEBUG is not set
+# CONFIG_MAC80211_OCB_DEBUG is not set
+# CONFIG_MAC80211_IBSS_DEBUG is not set
+CONFIG_MAC80211_PS_DEBUG=y
+# CONFIG_MAC80211_TDLS_DEBUG is not set
+# CONFIG_MAC80211_DEBUG_COUNTERS is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIE_ECRC=y
+# CONFIG_PCIE_DPC is not set
+CONFIG_PCI_DEBUG=y
+# CONFIG_ATH10K_TRACING is not set
+# CONFIG_ATH11K_DEBUGFS is not set
+# CONFIG_ATH11K_TRACING is not set
+CONFIG_IPW2100=m
+CONFIG_IPW2100_MONITOR=y
+CONFIG_IPW2100_DEBUG=y
+CONFIG_IPW2200=m
+CONFIG_IPW2200_MONITOR=y
+CONFIG_IPW2200_RADIOTAP=y
+CONFIG_IPW2200_PROMISCUOUS=y
+CONFIG_IPW2200_QOS=y
+CONFIG_IPW2200_DEBUG=y
+CONFIG_LIBIPW=m
+CONFIG_LIBIPW_DEBUG=y
+CONFIG_IWLEGACY=m
+CONFIG_IWL4965=m
+CONFIG_IWL3945=m
+#
+# iwl3945 / iwl4965 Debugging Options
+#
+CONFIG_IWLEGACY_DEBUG=y
+# CONFIG_IWLEGACY_DEBUGFS is not set
+# end of iwl3945 / iwl4965 Debugging Options
+CONFIG_IWLWIFI=m
+CONFIG_IWLWIFI_LEDS=y
+CONFIG_IWLDVM=m
+CONFIG_IWLMVM=m
+CONFIG_IWLWIFI_OPMODE_MODULAR=y
+CONFIG_IWLWIFI_BCAST_FILTERING=y
+#
+# Debugging Options
+#
+CONFIG_IWLWIFI_DEBUG=y
+# CONFIG_IWLWIFI_DEBUGFS is not set
+CONFIG_IWLWIFI_DEVICE_TRACING=y
+# end of Debugging Options
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_PSTORE_FTRACE is not set
+CONFIG_BINARY_PRINTF=y
+# CONFIG_DEBUG_PAGE_REF is not set
+CONFIG_TRACE_IRQFLAGS=y
+CONFIG_STACKTRACE=y
+CONFIG_NOP_TRACER=y
+CONFIG_TRACER_MAX_TRACE=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_PREEMPTIRQ_TRACEPOINTS=y
+CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_FTRACE=y
+CONFIG_BOOTTIME_TRACING=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_FUNCTION_GRAPH_TRACER=y
+CONFIG_DYNAMIC_FTRACE=y
+# CONFIG_FUNCTION_PROFILER is not set
+# CONFIG_STACK_TRACER is not set
+CONFIG_TRACE_PREEMPT_TOGGLE=y
+CONFIG_IRQSOFF_TRACER=y
+CONFIG_PREEMPT_TRACER=y
+CONFIG_SCHED_TRACER=y
+# CONFIG_HWLAT_TRACER is not set
+# CONFIG_OSNOISE_TRACER is not set
+# CONFIG_TIMERLAT_TRACER is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_TRACER_SNAPSHOT=y
+CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_UPROBE_EVENTS=y
+CONFIG_DYNAMIC_EVENTS=y
+CONFIG_PROBE_EVENTS=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y
+# CONFIG_SYNTH_EVENTS is not set
+# CONFIG_HIST_TRIGGERS is not set
+# CONFIG_TRACE_EVENT_INJECT is not set
+# CONFIG_TRACEPOINT_BENCHMARK is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_TRACE_EVAL_MAP_FILE is not set
+# CONFIG_FTRACE_RECORD_RECURSION is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
+# CONFIG_PREEMPTIRQ_DELAY_TEST is not set
+CONFIG_CMA_SIZE_MBYTES=128
+CONFIG_FUNCTION_TRACER
+CONFIG_FUNCTION_GRAPH_TRACER
+CONFIG_STACK_TRACER
+CONFIG_DYNAMIC_FTRACE

layers/meta-belden-marvell-bsp/recipes-kernel/linux/linux-netmodule_git-5.15-solidrun.bb

@@ -7,6 +7,9 @@ SRC_URI = "git://gitlab.com/netmodule/kernel/linux-netmodule.git;protocol=ssh;us
            file://0001-cn913x-fix-compatible-node-inside-dts.patch \
            file://netfilter.cfg \
            file://0001-cn913x-fix-compatible-node-inside-dts-pt-2.patch \
+           file://cn9131_linux_copper_and_sfp.patch \
+           file://0001-refactor-cn913x-defconfig-cleanup.patch \
+           file://cn913x_additions.cfg \
            "
 SRCREV ?= "be2f2f0c96e85ecec9d807397194e46bb8bea4a5"