162 lines
5.0 KiB
Diff
162 lines
5.0 KiB
Diff
From 3f8f24cf82848ef1778f3e1d0a0607d4860dd4f3 Mon Sep 17 00:00:00 2001
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From: Alon Rotman <alon.rotman@solid-run.com>
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Date: Mon, 22 Nov 2021 13:33:25 +0200
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Subject: [PATCH] ddr spd read failover to defualt config
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---
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.../octeontx/otx2/t91/t9130/board/dram_port.c | 100 ++++++++++++++++--
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1 file changed, 93 insertions(+), 7 deletions(-)
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diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
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index 82ce07b09..bb7814e9b 100644
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--- a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
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+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
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@@ -33,7 +33,7 @@ struct mv_ddr_iface dram_iface_ap0 = {
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.id = 0,
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.iface_base_addr = 0,
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.tm = {
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- DEBUG_LEVEL_ERROR,
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+ DEBUG_LEVEL_INFO,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x0, 0, 0},
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@@ -45,8 +45,8 @@ struct mv_ddr_iface dram_iface_ap0 = {
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0} },
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- SPEED_BIN_DDR_2400T, /* speed_bin */
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- MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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+ SPEED_BIN_DDR_2400R, /* speed_bin */
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+ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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@@ -54,7 +54,8 @@ struct mv_ddr_iface dram_iface_ap0 = {
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#if DDR32
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MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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#else
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- MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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+/* MV_DDR_64BIT_ECC_PUP8_BUS_MASK, *//* subphys mask */
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+ MV_DDR_64BIT_BUS_MASK,
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#endif
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MV_DDR_CFG_SPD, /* ddr configuration data src */
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NOT_COMBINED, /* ddr twin-die combined*/
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@@ -98,6 +99,87 @@ struct mv_ddr_iface dram_iface_ap0 = {
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},
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};
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+u8 is_spd_empty_sr(u8 *spd_buffer){
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+/* checks the first 196 bytes to check if SPD is has any DDR */
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+ u32 i=0;
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+ u32 size=MV_DDR_SPD_DATA_BLOCK0_SIZE+MV_DDR_SPD_DATA_BLOCK1M_SIZE;
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+ for (i=0; i<size; i++){
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+ if (spd_buffer[i] != 0xff) {
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+ return 0;
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+ }
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+ }
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+ return 1;
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+}
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+
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+void define_gpio_input_sr (u32 mux_address, u32 direction_address, u8 bit_start_mux, u8 bit_dir_address)
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+{
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+ u32 mask=0;
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+ u32 val;
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+
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+ /* define as gpio */
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+ val = mmio_read_32 (mux_address);
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+ mask |= (0xf << bit_start_mux);
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+ mask = ~mask;
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+ val &= mask;
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+ mmio_write_32(mux_address, val);
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+ /*define as input */
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+
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+ val = mmio_read_32(direction_address);
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+ val |= (1 << bit_dir_address);
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+ mmio_write_32(direction_address, val);
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+
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+ /*all is standard polarity by defualt */
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+}
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+
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+u8 read_gpio_strap_sr (u32 addr, u8 bit_loc)
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+{
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+ u32 val;
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+
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+ val=mmio_read_32 (addr);
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+ val &= (0x1<<bit_loc);
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+ printf("\nDDR Strap %d, value is %d\n", bit_loc, val != 0);
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+
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+ if (!val)
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+ return (u8) 0;
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+
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+ return (u8) 1;
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+
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+}
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+
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+void set_param_based_on_som_strap (){
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+ /* sample GPIOs 10, 11
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+ * MPP10: 1-ECC /0-noECC
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+ * MPP11: 1-4Gb /0-8Gb per component
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+ */
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+
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+ /*defining MPP[11:10] as gpio inputs*/
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+ define_gpio_input_sr (0xf2440004, 0xf2440100, 8, 10);
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+ define_gpio_input_sr (0xf2440004, 0xf2440100, 12,11);
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+
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+ /*after SPD read failed, defining as DEFAULT configuration*/
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+ dram_iface_ap0.tm.cfg_src = MV_DDR_CFG_DEFAULT;
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+
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+ /* read gpio value to check if ECC exist or not */
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+ if (read_gpio_strap_sr ((u32) 0xf2440110, (u8) 10)){
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+ printf("ecc strap value=1\n\n");
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+ dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_ECC_PUP8_BUS_MASK;
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+ }
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+ else {
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+ dram_iface_ap0.tm.bus_act_mask=MV_DDR_64BIT_BUS_MASK;
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+ printf("ecc strap value=0\n\n");
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+ }
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+ /* read gpio value to check 4GB or 8GB configuration */
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+ if (!read_gpio_strap_sr ((u32) 0xf2440110, (u8) 11)){
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+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_8GBIT;
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+ printf("die capacity strap value=1\n\n");
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+ }
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+ else{
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+ dram_iface_ap0.tm.interface_params[0].memory_size=MV_DDR_DIE_CAP_4GBIT;
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+ printf("die capacity strap value=1\n\n");
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+ }
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+}
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+
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+
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/* Pointer to the first DRAM interface in the system */
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struct mv_ddr_iface *ptr_iface = &dram_iface_ap0;
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@@ -109,7 +191,7 @@ struct mv_ddr_iface *mv_ddr_iface_get(void)
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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- /* Return the board topology as defined in the board code */
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+/* Return the board topology as defined in the board code */
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return &ptr_iface->tm;
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}
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@@ -135,6 +217,8 @@ static void mpp_config(void)
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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+
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+
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void plat_marvell_dram_update_topology(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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@@ -152,7 +236,9 @@ void plat_marvell_dram_update_topology(void)
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i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
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/* read data from spd */
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- i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
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- sizeof(tm->spd_data.all_bytes));
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+ i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,sizeof(tm->spd_data.all_bytes));
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+ /* if SPD is empty, then copy default configuration as SPD */
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+ if (is_spd_empty_sr(tm->spd_data.all_bytes))
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+ set_param_based_on_som_strap();
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}
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}
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