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MLK-16034-02: enable GPMI NAND driver for i.MX8 

enable the GPMI NAND driver for i.MX8, the major changes

- register defination for i.mx8
- Makefile change for misc.c
- DMA structure must be 32bit address

Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 474c4270108551647c7064a23abdc2e11d7f37ab)
This commit is contained in:
Han Xu 2017-07-19 11:43:08 -05:00 committed by Ye Li
parent d297f33f47
commit 029cce25cc
6 changed files with 30 additions and 23 deletions
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15
arch/arm/include/asm/mach-imx/dma.h
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@ -6,6 +6,7 @@
* *
* Based on code from LTIB: * Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2017 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -54,7 +55,7 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS, MXS_MAX_DMA_CHANNELS,
}; };
#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
enum { enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1, MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
@ -96,13 +97,13 @@ enum {
#define MXS_DMA_DESC_BYTES_OFFSET 16 #define MXS_DMA_DESC_BYTES_OFFSET 16
struct mxs_dma_cmd { struct mxs_dma_cmd {
unsigned long next; uint32_t next;
unsigned long data; uint32_t data;
union { union {
dma_addr_t address; uint32_t address;
unsigned long alternate; uint32_t alternate;
}; };
unsigned long pio_words[DMA_PIO_WORDS]; uint32_t pio_words[DMA_PIO_WORDS];
}; };
/* /*
@ -118,7 +119,7 @@ struct mxs_dma_cmd {
struct mxs_dma_desc { struct mxs_dma_desc {
struct mxs_dma_cmd cmd; struct mxs_dma_cmd cmd;
unsigned int flags; unsigned int flags;
dma_addr_t address; uint32_t address;
void *buffer; void *buffer;
struct list_head node; struct list_head node;
} __aligned(MXS_DMA_ALIGNMENT); } __aligned(MXS_DMA_ALIGNMENT);

7
arch/arm/include/asm/mach-imx/regs-apbh.h
View File

@ -6,6 +6,7 @@
* *
* Based on code from LTIB: * Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2017 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -96,7 +97,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version) mxs_reg_32(hw_apbh_version)
}; };
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
struct mxs_apbh_regs { struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1) mxs_reg_32(hw_apbh_ctrl1)
@ -275,7 +276,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
@ -391,7 +392,7 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif #endif
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif #endif

5
arch/arm/include/asm/mach-imx/regs-bch.h
View File

@ -6,6 +6,7 @@
* *
* Based on code from LTIB: * Based on code from LTIB:
* Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2017 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -127,7 +128,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else #else
@ -158,7 +159,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else #else

1
arch/arm/mach-imx/Makefile
View File

@ -58,6 +58,7 @@ ifeq ($(SOC),$(filter $(SOC),imx8))
obj-$(CONFIG_HAVE_SC_FIRMWARE) += sci/ obj-$(CONFIG_HAVE_SC_FIRMWARE) += sci/
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
obj-y += misc.o
endif endif
ifneq ($(CONFIG_SPL_BUILD),y) ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o

9
drivers/dma/apbh_dma.c
View File

@ -6,6 +6,7 @@
* *
* Based on code from LTIB: * Based on code from LTIB:
* Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2017 NXP
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -88,7 +89,7 @@ void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
uint32_t addr; uint32_t addr;
uint32_t size; uint32_t size;
addr = (uint32_t)desc; addr = (uintptr_t)desc;
size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
flush_dcache_range(addr, addr + size); flush_dcache_range(addr, addr + size);
@ -215,8 +216,8 @@ static int mxs_dma_reset(int channel)
#if defined(CONFIG_MX23) #if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); uint32_t setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif #endif
@ -224,7 +225,7 @@ static int mxs_dma_reset(int channel)
if (ret) if (ret)
return ret; return ret;
writel(1 << (channel + offset), setreg); writel(1 << (channel + offset), (uintptr_t)setreg);
return 0; return 0;
} }

16
drivers/mtd/nand/mxs_nand.c
View File

@ -31,7 +31,7 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else #else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
@ -88,21 +88,21 @@ static int galois_field = 13;
#ifndef CONFIG_SYS_DCACHE_OFF #ifndef CONFIG_SYS_DCACHE_OFF
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{ {
uint32_t addr = (uint32_t)info->data_buf; uint32_t addr = (uintptr_t)info->data_buf;
flush_dcache_range(addr, addr + info->data_buf_size); flush_dcache_range(addr, addr + info->data_buf_size);
} }
static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
{ {
uint32_t addr = (uint32_t)info->data_buf; uint32_t addr = (uintptr_t)info->data_buf;
invalidate_dcache_range(addr, addr + info->data_buf_size); invalidate_dcache_range(addr, addr + info->data_buf_size);
} }
static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
{ {
uint32_t addr = (uint32_t)info->cmd_buf; uint32_t addr = (uintptr_t)info->cmd_buf;
flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
} }
@ -204,7 +204,7 @@ static int mxs_nand_get_ecc_strength(struct mtd_info *mtd)
int max_ecc_strength_supported; int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
if (is_mx6sx() || is_mx7() || is_imx8m()) if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
max_ecc_strength_supported = 62; max_ecc_strength_supported = 62;
else else
max_ecc_strength_supported = 40; max_ecc_strength_supported = 40;
@ -805,7 +805,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
if (status[i] == 0xff) { if (status[i] == 0xff) {
if (is_mx6dqp() || is_mx7() || if (is_mx6dqp() || is_mx7() ||
is_mx6ul() || is_imx8m()) is_mx6ul() || is_imx8() || is_imx8m())
if (readl(&bch_regs->hw_bch_debug1)) if (readl(&bch_regs->hw_bch_debug1))
flag = 1; flag = 1;
continue; continue;
@ -1135,6 +1135,8 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
uint32_t tmp; uint32_t tmp;
/* calculate ecc_strength, bbm_chunk, eec_for meta, if necessary */ /* calculate ecc_strength, bbm_chunk, eec_for meta, if necessary */
mxs_nand_get_ecc_strength(mtd); mxs_nand_get_ecc_strength(mtd);
@ -1168,7 +1170,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
/* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */ /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
if (is_mx6dqp() || is_mx7() || if (is_mx6dqp() || is_mx7() ||
is_mx6ul() || is_imx8m()) is_mx6ul() || is_imx8() || is_imx8m())
writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength), writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength),
&bch_regs->hw_bch_mode); &bch_regs->hw_bch_mode);