From 02b99a8ce3ed8f7ab1798b946c10b614ae386924 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 3 Jul 2017 03:54:49 -0500 Subject: [PATCH] MLK-15324-2 video: imxdpuv1: Add DPU driver for i.MX8 Adding new IMXDPUV1 (aka Seeris, Iris-lite) display control driver. Signed-off-by: Oliver Brown Signed-off-by: Ye Li (cherry picked from commit 43541cba14f851c6eebaa84becd42967f94a9cfd) --- drivers/video/Kconfig | 7 + drivers/video/Makefile | 1 + drivers/video/imxdpuv1.c | 6219 ++++++++ drivers/video/imxdpuv1_be.h | 116 + drivers/video/imxdpuv1_private.h | 470 + include/imxdpuv1.h | 998 ++ include/imxdpuv1_events.h | 353 + include/imxdpuv1_registers.h | 22682 +++++++++++++++++++++++++++++ 8 files changed, 30846 insertions(+) create mode 100644 drivers/video/imxdpuv1.c create mode 100644 drivers/video/imxdpuv1_be.h create mode 100644 drivers/video/imxdpuv1_private.h create mode 100644 include/imxdpuv1.h create mode 100644 include/imxdpuv1_events.h create mode 100644 include/imxdpuv1_registers.h diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2898c391d2..e02883c716 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -513,6 +513,13 @@ config VIDEO_IPUV3 This enables framebuffer driver for i.MX processors working on the IPUv3(Image Processing Unit) internal graphic processor. +config VIDEO_IMXDPUV1 + bool "i.MX DPU V1 display support" + default n + depends on VIDEO && IMX8 + help + Support for IMXDPU V1 display controller for i.MX8 processors. + config MXC_EPDC bool "i.MX EPDC support" depends on LCD && (MX7 || MX6) diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a9c1ccb768..5c7a5d80f0 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o diff --git a/drivers/video/imxdpuv1.c b/drivers/video/imxdpuv1.c new file mode 100644 index 0000000000..6b1864d359 --- /dev/null +++ b/drivers/video/imxdpuv1.c @@ -0,0 +1,6219 @@ +/* + * Copyright 2015-2017 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "imxdpuv1_private.h" +#include "imxdpuv1_registers.h" +#include "imxdpuv1_events.h" + +#include "imxdpuv1_be.h" + +#define ptr_to_uint32(__ptr__) ((uint32_t)((uint64_t)(__ptr__))) + +/* Private data*/ +static struct imxdpuv1_soc imxdpuv1_array[IMXDPUV1_MAX_NUM]; + +typedef struct { + uint8_t len; + uint8_t buffers; +} imxdpuv1_burst_entry_t; + +static const imxdpuv1_burst_entry_t burst_param[] = { + { 0, 0 }, /* IMXDPUV1_SCAN_DIR_UNKNOWN */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_LEFT_RIGHT_DOWN */ + { 16, 16 }, /* IMXDPUV1_SCAN_DIR_HORIZONTAL */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_VERTICAL possibly 8/32 here */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_FREE */ +}; + +typedef struct { + uint32_t extdst; + uint32_t sub; +} trigger_entry_t; + +static const trigger_entry_t trigger_list[IMXDPUV1_SHDLD_IDX_MAX] = { + /* IMXDPUV1_SHDLD_* extdst, sub */ + /* _DISP0 */{ 1, 0 }, + /* _DISP1 */{ 1, 0 }, + /* _CONST0 */{ IMXDPUV1_SHDLD_CONSTFRAME0, 0 }, + /* _CONST1 */{ IMXDPUV1_SHDLD_CONSTFRAME1, 0 }, + /* _CHAN_00 */{ IMXDPUV1_SHDLD_FETCHDECODE2, 0 }, + /* _CHAN_01 */{ IMXDPUV1_SHDLD_FETCHDECODE0, 0 }, + /* _CHAN_02 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_1 }, + /* _CHAN_03 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_2 }, + /* _CHAN_04 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_3 }, + /* _CHAN_05 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_4 }, + /* _CHAN_06 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_5 }, + /* _CHAN_07 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_6 }, + /* _CHAN_08 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_7 }, + /* _CHAN_09 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_8 }, + /* _CHAN_10 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_1 << 16 }, + /* _CHAN_11 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_2 << 16 }, + /* _CHAN_12 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_3 << 16 }, + /* _CHAN_13 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_4 << 16 }, + /* _CHAN_14 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_5 << 16 }, + /* _CHAN_15 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_6 << 16 }, + /* _CHAN_16 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_7 << 16 }, + /* _CHAN_17 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_8 << 16 }, + /* _CHAN_18 */{ IMXDPUV1_SHDLD_FETCHDECODE3, 0 }, + /* _CHAN_19 */{ IMXDPUV1_SHDLD_FETCHDECODE1, 0 }, + /* _CHAN_20 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_1 << 8 }, + /* _CHAN_21 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_2 << 8 }, + /* _CHAN_22 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_3 << 8 }, + /* _CHAN_23 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_4 << 8 }, + /* _CHAN_24 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_5 << 8 }, + /* _CHAN_25 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_6 << 8 }, + /* _CHAN_26 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_7 << 8 }, + /* _CHAN_27 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_8 << 8 }, + /* _CHAN_28 */{ IMXDPUV1_SHDLD_FETCHECO0, 0 }, + /* _CHAN_29 */{ IMXDPUV1_SHDLD_FETCHECO1, 0 }, + /* _CHAN_30 */{ IMXDPUV1_SHDLD_FETCHECO2, 0 } +}; + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *imxdpu, uint32_t offset, char *file, + int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} + +void _imxdpuv1_write(struct imxdpuv1_soc *imxdpu, uint32_t offset, uint32_t value, + char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} + +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, + void *values, uint32_t cnt, char *file, int line) +{ + int i; + uint32_t *dest = (uint32_t *)(imxdpu->base + offset); + uint32_t *src = (uint32_t *)values; + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- cnt 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)cnt); + for (i = 0; i < cnt; i++) { + dest[i] = src[i]; + IMXDPUV1_TRACE_REG("%s:%d WB reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t) ((uint64_t)(&dest[i])), (uint32_t)(src[i])); + + } +} + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + char *file, int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + uint32_t value, char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} +#endif + +/* static prototypes */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +static bool imxdpuv1_is_yuv(uint32_t fmt); +bool imxdpuv1_is_rgb(uint32_t fmt); + +/*! + * Returns IMXDPUV1_TRUE for a valid channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + if ((chan_idx >= IMXDPUV1_CHAN_IDX_IN_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_IN_MAX)) + return IMXDPUV1_TRUE; + if ((chan_idx >= IMXDPUV1_CHAN_IDX_OUT_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_OUT_MAX)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid store channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_store_chan(imxdpuv1_chan_t chan) +{ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_STORE4) || (blk_id == IMXDPUV1_ID_STORE4)) + return IMXDPUV1_TRUE; +#endif + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHECO0) || + (blk_id == IMXDPUV1_ID_FETCHECO1) || + (blk_id == IMXDPUV1_ID_FETCHECO2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch decode channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_decode_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHDECODE2) + || (blk_id == IMXDPUV1_ID_FETCHDECODE3) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE if a fetch channel has an eco fetch + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int has_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) || + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch warp channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_warp_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch layer channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHLAYER1) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid layer sub1 channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_sub_chan1(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) || +#ifdef IMXDPUV1_VERSION_0 + (blk_id == IMXDPUV1_ID_FETCHLAYER1) || +#endif + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + if (get_channel_sub(chan) == IMXDPUV1_SUB_1) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns subindex of a channel + * + * @param channel + * + * @return returns the subindex of a channel + */ +static int imxdpuv1_get_channel_subindex(imxdpuv1_chan_t chan) +{ + switch (get_channel_sub(chan)) { + case IMXDPUV1_SUB_2: + return 1; + case IMXDPUV1_SUB_3: + return 2; + case IMXDPUV1_SUB_4: + return 3; + case IMXDPUV1_SUB_5: + return 4; + case IMXDPUV1_SUB_6: + return 5; + case IMXDPUV1_SUB_7: + return 6; + case IMXDPUV1_SUB_8: + return 7; + case IMXDPUV1_SUB_1: + case IMXDPUV1_SUBWINDOW_NONE: + default: + return 0; + } +} + +/*! + * Returns returns the eco channel for a channel index + * + * @param chan + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +imxdpuv1_chan_t imxdpuv1_get_eco(imxdpuv1_chan_t chan) +{ + switch (get_eco_idx(chan)) { + case get_channel_idx(IMXDPUV1_CHAN_28): + return IMXDPUV1_CHAN_28; + case get_channel_idx(IMXDPUV1_CHAN_29): + return IMXDPUV1_CHAN_29; + case get_channel_idx(IMXDPUV1_CHAN_30): + return IMXDPUV1_CHAN_30; + default: + return 0; + } +} +/*! + * Returns the start address offset for a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2blockoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + /*case IMXDPUV1_ID_NONE: return IMXDPUV1_NONE_LOCKUNLOCK; */ + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_FETCHDECODE9_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_FETCHPERSP9_LOCKUNLOCK; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_FETCHWARP9_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHECO9: + return IMXDPUV1_FETCHECO9_LOCKUNLOCK; + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_ROP9_LOCKUNLOCK; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_CLUT9_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_MATRIX9_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_HSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_VSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_FILTER9_LOCKUNLOCK; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_BLITBLEND9_LOCKUNLOCK; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_STORE9_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME0: + return IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_EXTDST0_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME4: + return IMXDPUV1_CONSTFRAME4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_EXTDST4_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME1: + return IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_EXTDST1_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME5: + return IMXDPUV1_CONSTFRAME5_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_EXTDST5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTSRC4: + return IMXDPUV1_EXTSRC4_LOCKUNLOCK; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_STORE4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC5: + return IMXDPUV1_EXTSRC5_LOCKUNLOCK; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_STORE5_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_FETCHDECODE2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_FETCHDECODE3_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_FETCHWARP2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO2: + return IMXDPUV1_FETCHECO2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_FETCHDECODE0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO0: + return IMXDPUV1_FETCHECO0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_FETCHDECODE1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO1: + return IMXDPUV1_FETCHECO1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHLAYER0: + return IMXDPUV1_FETCHLAYER0_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHLAYER1: + return IMXDPUV1_FETCHLAYER1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_GAMMACOR4_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_MATRIX4_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_HSCALER4_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_VSCALER4_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_HISTOGRAM4_CONTROL; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_GAMMACOR5_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_MATRIX5_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_HSCALER5_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_VSCALER5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_HISTOGRAM5_CONTROL; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_LAYERBLEND0_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_LAYERBLEND1_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_LAYERBLEND2_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_LAYERBLEND3_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_LAYERBLEND4_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_LAYERBLEND5_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_LAYERBLEND6_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC0: + return IMXDPUV1_EXTSRC0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC1: + return IMXDPUV1_EXTSRC1_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_DISENGCFG: + return IMXDPUV1_DISENGCFG_LOCKUNLOCK0; + case IMXDPUV1_ID_FRAMEGEN0: + return IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX0: + return IMXDPUV1_MATRIX0_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR0: + return IMXDPUV1_GAMMACOR0_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER0: + return IMXDPUV1_DITHER0_LOCKUNLOCK; + case IMXDPUV1_ID_TCON0: + return IMXDPUV1_TCON0_LOCKUNLOCK; + case IMXDPUV1_ID_SIG0: + return IMXDPUV1_SIG0_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMEGEN1: + return IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX1: + return IMXDPUV1_MATRIX1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR1: + return IMXDPUV1_GAMMACOR1_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER1: + return IMXDPUV1_DITHER1_LOCKUNLOCK; + case IMXDPUV1_ID_TCON1: + return IMXDPUV1_TCON1_LOCKUNLOCK; + case IMXDPUV1_ID_SIG1: + return IMXDPUV1_SIG1_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FRAMECAP4: + return IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMECAP5: + return IMXDPUV1_FRAMECAP5_LOCKUNLOCK; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for the dynamic configuraiton for + * a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2dynamicoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC; + +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC; +#endif + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for a given shadow index + * + * @param block id + * + * @return This function returns the address offset if the shadow + * index matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +imxdpuv1_chan_t shadowindex2channel(imxdpuv1_shadow_load_index_t shadow_index) +{ + switch (shadow_index) { + case IMXDPUV1_SHDLD_IDX_CHAN_00: + return IMXDPUV1_CHAN_00; + case IMXDPUV1_SHDLD_IDX_CHAN_01: + return IMXDPUV1_CHAN_01; + case IMXDPUV1_SHDLD_IDX_CHAN_02: + return IMXDPUV1_CHAN_02; + case IMXDPUV1_SHDLD_IDX_CHAN_03: + return IMXDPUV1_CHAN_03; + case IMXDPUV1_SHDLD_IDX_CHAN_04: + return IMXDPUV1_CHAN_04; + case IMXDPUV1_SHDLD_IDX_CHAN_05: + return IMXDPUV1_CHAN_05; + case IMXDPUV1_SHDLD_IDX_CHAN_06: + return IMXDPUV1_CHAN_06; + case IMXDPUV1_SHDLD_IDX_CHAN_07: + return IMXDPUV1_CHAN_07; + case IMXDPUV1_SHDLD_IDX_CHAN_08: + return IMXDPUV1_CHAN_08; + case IMXDPUV1_SHDLD_IDX_CHAN_09: + return IMXDPUV1_CHAN_09; + case IMXDPUV1_SHDLD_IDX_CHAN_10: + return IMXDPUV1_CHAN_10; + case IMXDPUV1_SHDLD_IDX_CHAN_11: + return IMXDPUV1_CHAN_11; + case IMXDPUV1_SHDLD_IDX_CHAN_12: + return IMXDPUV1_CHAN_12; + case IMXDPUV1_SHDLD_IDX_CHAN_13: + return IMXDPUV1_CHAN_13; + case IMXDPUV1_SHDLD_IDX_CHAN_14: + return IMXDPUV1_CHAN_14; + case IMXDPUV1_SHDLD_IDX_CHAN_15: + return IMXDPUV1_CHAN_15; + case IMXDPUV1_SHDLD_IDX_CHAN_16: + return IMXDPUV1_CHAN_16; + case IMXDPUV1_SHDLD_IDX_CHAN_17: + return IMXDPUV1_CHAN_17; + case IMXDPUV1_SHDLD_IDX_CHAN_18: + return IMXDPUV1_CHAN_18; + case IMXDPUV1_SHDLD_IDX_CHAN_19: + return IMXDPUV1_CHAN_19; + case IMXDPUV1_SHDLD_IDX_CHAN_20: + return IMXDPUV1_CHAN_20; + case IMXDPUV1_SHDLD_IDX_CHAN_21: + return IMXDPUV1_CHAN_21; + case IMXDPUV1_SHDLD_IDX_CHAN_22: + return IMXDPUV1_CHAN_22; + case IMXDPUV1_SHDLD_IDX_CHAN_23: + return IMXDPUV1_CHAN_23; + case IMXDPUV1_SHDLD_IDX_CHAN_24: + return IMXDPUV1_CHAN_24; + case IMXDPUV1_SHDLD_IDX_CHAN_25: + return IMXDPUV1_CHAN_25; + case IMXDPUV1_SHDLD_IDX_CHAN_26: + return IMXDPUV1_CHAN_26; + case IMXDPUV1_SHDLD_IDX_CHAN_27: + return IMXDPUV1_CHAN_27; + case IMXDPUV1_SHDLD_IDX_CHAN_28: + return IMXDPUV1_CHAN_28; + case IMXDPUV1_SHDLD_IDX_CHAN_29: + return IMXDPUV1_CHAN_29; + case IMXDPUV1_SHDLD_IDX_CHAN_30: + return IMXDPUV1_CHAN_30; + default: + return IMXDPUV1_CHANNEL_INVALID; + } +} + + +/*! + * This function returns the pointer to the imxdpu structutre + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns the pointer to the imxdpu structutre + * return a NULL pointer for a failure. + */ +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id) +{ + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return NULL; + } + return &(imxdpuv1_array[imxdpuv1_id]); +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to enable interrupt for. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + if (irq == 0) + panic("Trying to enable irq 0!"); +#endif + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] |= INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] |= INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] |= INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function disables the interrupt for the specified interrupt line.g + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to disable interrupt for. + * + */ +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] &= ~INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] &= ~INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] &= ~INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function clears all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2_USERINTERRUPTCLEAR2_MASK); +#endif +#if 1 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2_INTERRUPTCLEAR2_MASK); +#endif +#endif + return ret; +} + +/*! + * This function disables all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_disable_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + +#if 1 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE2, 0); +#endif +#endif + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + return ret; +} + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in ipu_irq_line enum. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to clear interrupt for. + * + */ +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + 1U << irq); + } + if (irq < 64) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + 1U << (irq - 32)); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + 1U << (irq - 64)); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_init_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_all_irqs(imxdpuv1_id); + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all irq to user mode */ + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* enable needed interupts */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_FRAMECOMPLETE_IRQ); +#endif + /* enable the frame interrupts as IMXDPUV1_IRQF_ONESHOT */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN0_INT0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN1_INT0_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW1_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ); + + IMXDPUV1_TRACE("%s() enabled_int[0] 0x%08x\n", __func__, + imxdpu->enabled_int[0]); + IMXDPUV1_TRACE("%s() enabled_int[1] 0x%08x\n", __func__, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_TRACE("%s() enabled_int[2] 0x%08x\n", __func__, + imxdpu->enabled_int[2]); +#endif + return ret; +} + +/*! + * This function checks pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst = IMXDPUV1_OFFSET_INVALID; /* address for extdst */ + uint32_t extdst = 0; + uint32_t extdst_stat = 0; + uint32_t fgen = 1; + uint32_t fgen_stat = 0; + uint32_t sub = 0; + uint32_t sub_stat = 0; + uint32_t stat; + + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + stat = imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + if (disp == 0) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ) { + fgen = 0; + } + } else if (disp == 1) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ) { + fgen = 0; + } + } else { + return -EINVAL; + } + + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE)) & 0xff; +#ifdef IMXDPUV1_VERSION_0 + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE) << 8) & 0xff00; +#endif + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE) << 16) & 0xff0000; + extdst = imxdpuv1_read(imxdpu, addr_extdst); + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + if (i > IMXDPUV1_SHDLD_IDX_CONST1) { + if (!(extdst & trigger_list[i].extdst) && !fgen) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + fgen_stat |= 1 << i; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + /* fetch layer and fetchwarp */ + if ((trigger_list[i].extdst != 0) && + (trigger_list[i].sub != 0)) { + if (!(extdst & trigger_list[i].extdst) && + !(sub & trigger_list[i].sub)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + sub_stat |= trigger_list[i].sub; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst_stat |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + if ((extdst_stat == 0) && (sub_stat == 0) && (fgen_stat == 0)) { + /* clear interrupt */ + IMXDPUV1_TRACE_IRQ("shadow requests are complete.\n"); + } else { + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst 0x%08x, sub 0x%08x, fgen 0x%08x\n", + extdst, sub, fgen); + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst_stat 0x%08x, sub_stat 0x%08x, fgen_stat 0x%08x\n", + extdst_stat, sub_stat, fgen_stat); + } + + return ret; +} + +/*! + * This function starts pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + extdst |= trigger_list[i].extdst; + /* only trigger frame generator for const frames*/ + if (i >= IMXDPUV1_SHDLD_IDX_CONST0) { + fgen |= 1; + } + } + } + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + /*todo: need a completion handler */ + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + } + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function handles the VYNC interrupt for a display + * + * @param imxdpu imxdpu instance + * @param disp display index + * + */ +static void imxdpuv1_disp_vsync_handler(int8_t imxdpuv1_id, int8_t disp) +{ + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + if (!((disp == 0) || (disp == 1))) + return; + + /* send notifications + shadow load finished + */ + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + imxdpuv1_disp_update_fgen_status(imxdpuv1_id, disp); + + return; + +} + +/*! + * This function calls a register handler for an interrupt + * + * @param imxdpu imxdpu instance + * @param irq interrupt line + * + */ +static void imxdpuv1_handle_registered_irq(int8_t imxdpuv1_id, int8_t irq) +{ + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if ((irq < 0) || (irq >= IMXDPUV1_INTERRUPT_MAX)) + return; + + if (imxdpu->irq_list[irq].handler == NULL) + return; + + imxdpu->irq_list[irq].handler(irq, imxdpu->irq_list[irq].data); + + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) != 0) { + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + } + return; + +} + +/* todo: this irq handler assumes all irq are ORed together. + The irqs may be grouped so this function can be + optimized if that is the case*/ +/*! + * This function processes all IRQs for the IMXDPU + * + * @param data pointer to the imxdpu structure + * + */ +int imxdpuv1_handle_irq(int32_t imxdpuv1_id) +{ + uint32_t int_stat[3]; + uint32_t int_temp[3]; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + IMXDPUV1_TRACE_IRQ("%s(): invalid imxdpuv1_id\n", __func__); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("wrong imxdpuv1_id"); +#endif + return IMXDPUV1_FALSE; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->irq_count++; + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + { + uint32_t int_enable0; + int_enable0 = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0); + if (int_enable0 & 1) { + panic("IRQ0 enabled\n"); + } + if (imxdpu->enabled_int[0] & 1) { + panic("IRQ0 in enabled_int is set\n"); + } + } +#endif + /* Get and clear interrupt status */ + int_temp[0] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + int_stat[0] = imxdpu->enabled_int[0] & int_temp[0]; + int_temp[1] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1); + int_stat[1] = imxdpu->enabled_int[1] & int_temp[1]; +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + /* Enable this (IMXDPUV1_ENABLE_INTSTAT2) if intstat2 interrupts + are needed */ + int_temp[2] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS2); + int_stat[2] = imxdpu->enabled_int[2] & int_temp[2]; +#endif +#endif + /* No interrupts are pending */ + if ((int_temp[0] == 0) && (int_temp[1] == 0) +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_temp[2] == 0) +#endif +#endif + ) { + } + + /* No enabled interrupts are pending */ + if ((int_stat[0] == 0) && (int_stat[1] == 0) +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_stat[2] == 0) +#endif + ) { + IMXDPUV1_TRACE_IRQ + ("Error: No enabled interrupts, 0x%08x 0x%08x\n", + int_temp[0] & ~imxdpu->enabled_int[0], + int_temp[1] & ~imxdpu->enabled_int[1]); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("no enabled IMXDPU interrupts"); +#endif + + return IMXDPUV1_FALSE; + } + + /* Clear the enabled interrupts */ + if (int_stat[0]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + int_stat[0]); + } + if (int_stat[1]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + int_stat[1]); + } +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[2]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + int_stat[2]); + } +#endif + +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[1] != 0) { + /* add int_stat[2] if needed */ + } +#endif +#ifdef IMXDPUV1_VERSION_0 + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE("IMXDPUV1_STORE4_SHDLOAD_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SHDLOAD_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_SEQCOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM4_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM4_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM4_VALID_IRQ); + } + } + if (int_stat[0] & 0xff000000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM5_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM5_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM5_VALID_IRQ); + } + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ)) { + IMXDPUV1_PRINT + ("IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ irq\n"); + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT1_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT1_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT1_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & + INTSTAT1_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + + } + } +#else + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + + } + if (int_stat[0] & 0xff000000) { + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + /* Reserved for command sequencer debug */ + } + } +#endif + return IMXDPUV1_TRUE; +} + +/*! + * This function registers an interrupt handler function for the specified + * irq line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param data Input parameter for pointer of data to be + * passed to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int (*handler)(int, void *), + uint32_t irq_flags, const char *devname, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (imxdpu->irq_list[irq].handler != NULL) { + IMXDPUV1_TRACE("handler already installed on irq %d\n", irq); + ret = -EINVAL; + goto out; + } + + imxdpu->irq_list[irq].handler = handler; + imxdpu->irq_list[irq].flags = irq_flags; + imxdpu->irq_list[irq].data = data; + imxdpu->irq_list[irq].name = devname; + + /* Clear and enable the IRQ */ + imxdpuv1_clear_irq(imxdpuv1_id, irq); + /* Don't enable if a one shot */ + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) == 0) + imxdpuv1_enable_irq(imxdpuv1_id, irq); +out: + return ret; +} + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param data Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (imxdpu->irq_list[irq].data == data) + memset(&imxdpu->irq_list[irq], 0, sizeof(imxdpu->irq_list[irq])); + + return ret; +} + +/*! + * This function un-initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all interrupt to user mode */ + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* Set all interrupts to user mode. this will to change to + enable panic mode */ + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + /* enable needed interupts */ + return ret; +} + +/*! + * This function initializes the imxdpu and the required data structures + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +/* todo: replace with probe function or call from probe + use device tree as needed */ +int imxdpuv1_init(int8_t imxdpuv1_id) +{ + int ret = 0; + int i; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* todo: add resource mapping for xrdc, layers, blit, display, ... */ + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + /* Map the channels to display streams + todo: + make this mapping dynamic + add channel features + map capture channels + */ + for (i = IMXDPUV1_CHAN_IDX_IN_FIRST; i < IMXDPUV1_CHAN_IDX_MAX; i++) { + if (i <= IMXDPUV1_CHAN_IDX_17) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_IN_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else if (i < IMXDPUV1_CHAN_IDX_OUT_FIRST) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_OUT_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + imxdpu->irq_count = 0; + + if (imxdpuv1_id == 0) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY0; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY0); + + } else if (imxdpuv1_id == 1) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY1; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY1); + + } else { + return -ENOMEM; + } + + /* todo: may need to check resource allocaiton/ownership for these */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER1_TRIGGERENABLE_RESET_VALUE); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY0, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY1, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY2, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY3, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY4, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY5, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY6, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY7, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE); + + /* Initial StaticControl configuration - reset values */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_FETCHPERSP9_STATICCONTROL_RESET_VALUE); +#else + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE); +#endif + + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST4_STATICCONTROL, + IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST5_STATICCONTROL, + IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_EXTSRC4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_STORE4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_EXTSRC5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_STORE5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_FETCHDECODE2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_FETCHDECODE3_STATICCONTROL_RESET_VALUE); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_RESET_VALUE); +#endif + /* Dynamic config */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#else + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + /* Static configuration - reset values */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_STATIC, + IMXDPUV1_PIXENGCFG_STORE5_STATIC_RESET_VALUE); +#endif + /* Static configuration - initial settings */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET */ + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET */ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); +#endif + /* todo: IMXDPUV1_PIXENGCFG_STORE4_STATIC */ + /* Static Control configuration */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHPERSP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHPERSP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#else + /* IMXDPUV1_FETCHWARP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_ROP9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_STATICCONTROL_SHDEN, 1)); + + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_UNSHADOWEDCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE)); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FILTER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE4_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE5_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE3_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE, + 0)); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHLAYER0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHLAYER1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_GAMMACOR4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR4_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX4_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER4_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER4_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_GAMMACOR5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR5_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH)); + +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL__BOTH)); +#endif + /* todo: IMXDPUV1_EXTSRC0_STATICCONTROL */ + /* todo: IMXDPUV1_EXTSRC1_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX0_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR0_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* todo: IMXDPUV1_SIG0_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX1_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR1_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* IMXDPUV1_SIG1_STATICCONTROL */ + + imxdpuv1_init_irqs(imxdpuv1_id); + + return ret; +} + +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, + int8_t disp, + uint32_t pixel_fmt, struct imxdpuv1_videomode mode) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +/*! + * This function initializes the display + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + struct imxdpuv1_videomode *mode; + int reg = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + mode = &imxdpu->video_mode[disp]; + /*imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]);*/ + + if (disp == 0) { +#ifdef IMXDPUV1_TCON0_MAP_24BIT_0_23 + /* Static 24-bit TCON bit mapping for FPGA */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x17161514); + +#endif + + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0)); */ + + } else if (disp == 1) { +#ifdef IMXDPUV1_TCON1_MAP_24BIT_0_23 + /* Static TCON bit mapping */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x17161514); +#endif + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1)); */ + + } else { + return -EINVAL; + } + /* todo: initialize prefetch */ + + return ret; +} + +int imxdpuv1_disp_setup_tcon_bypass_mode( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode) +{ + struct imxdpuv1_soc *imxdpu; + uint32_t b_off; /* block offset for tcon generator */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_TCON0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_TCON1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_TCON_CTRL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE, + IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE, + IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION, + 0x140)); + /* setup hsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0, mode->hlen + mode->hfp)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0, mode->hlen + mode->hfp + mode->hsync)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET, 0xffff); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0, 2)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET, 1); + + /* Setup Vsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1, mode->hlen + mode->hfp + mode->hsync) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1, mode->vlen + mode->vfp - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1, mode->hlen + mode->hfp + mode->hsync)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1, mode->vlen + mode->vfp + mode->vsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0, 3)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET, 1); + + /* data enable horizontal */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2, mode->hlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET, 0xffff); + /* data enable vertical */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKON_OFFSET, 0x7fff0000); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET, 0x7fff0000); + + /* use both SPG2 and SPG3 to generate data enable */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0, 4)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1, 5)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET, 8); + + /* shadow load trigger (aka kachunk) */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4, 10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4, 26) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0, 6)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET, 2); + + return 0; +} + +/*! + * This function sets up the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * @param mode to set the display to + * @param cc_red constant color red + * @param cc_green constant color green + * @param cc_blue constant color blue + * @param cc_alpha constant color alpha +* + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable) +{ /* 1 bits, yes 1 bit */ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: here we need to use two outputs to make one */ + if (disp == 0) { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER); + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC); + } + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HACT, mode->hlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL, + (mode->hlen + mode->hfp + mode->hbp + mode->hsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC, + mode->hsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP, + mode->hbp + mode->hsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VACT, mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL, + (mode->vlen + mode->vfp + mode->vbp + mode->vsync - + 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC, + mode->vsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP, + mode->vbp + mode->vsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET, reg); + + /* Interupt at position (0, vlen - 3) for end of frame interrupt */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW, + mode->vlen - 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET, reg); + + /* Interupt at position 1, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET, reg); + + /* Interupt at position 2, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL, 2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET, reg); + + /* Interupt at position 3, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL, 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET, reg); + + /* todo: these need to be checked + _SKICKCOL for verification: =(FW - 40) , for ref driver = 1 ? + _SKICKROW for verif. =(FH - 1), ref driver = vlen-2 + */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL, + mode->hlen - 40) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW, + mode->vlen + 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_PACFG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SACFG_OFFSET, reg); + + if (IMXDPUV1_ENABLE == test_mode_enable) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST); + } else { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA, 0); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC, + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC, 0); + imxdpuv1_write(imxdpu, b_off + + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET, reg); + + /* Set the constant color - ARGB 1-10-10-10 */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCRED, cc_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE, cc_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN, cc_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA, cc_alpha); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET, reg); + + + imxdpuv1_disp_setup_tcon_bypass_mode(imxdpuv1_id, disp, mode); + + /* save the mode */ + imxdpu->video_mode[disp] = *mode; + + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]); */ + + return ret; +} + +/*! + * This function updates the frame generator status + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + uint32_t temp; + struct imxdpuv1_soc *imxdpu; + static uint32_t fcount[IMXDPUV1_NUM_DI_MAX] = { 0, 0 }; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET); + IMXDPUV1_TRACE_IRQ("DISP %d: findex %d, lindex %d\n", disp, + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg), + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX, reg)); + + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg); + if (temp != fcount[disp]) { + fcount[disp] = temp; + /* Just increment we assume this is called one per frame */ + imxdpu->fgen_stats[disp].frame_count++; + } + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET); + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 1)) { + imxdpu->fgen_stats[disp].sec_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: sec in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: sec out of sync\n", disp); + } + imxdpu->fgen_stats[disp].sec_sync_state = temp; + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 1)) { + imxdpu->fgen_stats[disp].prim_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: prim in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: prim out of sync\n", disp); + } + imxdpu->fgen_stats[disp].prim_sync_state = temp; + + /* primary fifo bit should be clear if in use (panic stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: primary fifo empty\n", disp); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK); + imxdpu->fgen_stats[disp].prim_fifo_empty_count++; + } + /* secondary fifo and skew error bits should be clear + if in use (content stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg) || + IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary fifo empty\n", + disp); + imxdpu->fgen_stats[disp].sec_fifo_empty_count++; + } + if (IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary skew error\n", + disp); + imxdpu->fgen_stats[disp].skew_error_count++; + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK); + } + return ret; +} +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param src_id id of the capture source block + * @param dest_id id of the capture dest block + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_frame; /* block offset for capture source */ + uint32_t b_off_extsrc; /* block offset for extsrc */ + + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMECAP5_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMEDUMP0_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMEDUMP1_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (dest_id == IMXDPUV1_ID_STORE4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_STORE5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } else if (dest_id == IMXDPUV1_ID_EXTDST0) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_EXTDST1) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5); + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_STATICCONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL) | + IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN_MASK); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONSTANTCOLOR_OFFSET, 0); + + if (cap_mode->format == IMXDPUV1_PIX_FMT_BGR24) { + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x00)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE__ITU601) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else if (cap_mode->format == IMXDPUV1_PIX_FMT_YUYV) { + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x0)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else { + IMXDPUV1_PRINT("%s(): invalid capture interface format\n", __func__); + return -EINVAL; + } + + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + /* setup cature */ + uint8_t capture_interface_mode; + /* Fixme: change these mode bits to an enumeration */ + if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ENHSVS_32BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_10BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_8BIT; + } else { + return -EINVAL; + } + + if (cap_id == 0) { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT0, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT0_CAPTUREMODE0, + capture_interface_mode)); + } else { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT1, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1, + capture_interface_mode)); + } + + imxdpuv1_write(imxdpu, b_off_frame + IMXDPUV1_FRAMECAP4_FDR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_WIDTH, cap_mode->hlen - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_FDR1_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen1 - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SCR_OFFSET, sync_count); + + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_KCR_OFFSET, 0); + if ((cap_mode->clip_height != 0) && (cap_mode->clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, cap_mode->clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, cap_mode->clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, cap_mode->clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, cap_mode->clip_top)); + } + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SPR_OFFSET, + + /* low is active low, high is active high */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLHS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLVS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLEN, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) == 0)) + ); + + + /* fixme: may need to move this mapping */ + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + + /* save the mode */ + imxdpu->capture_mode[cap_id] = *cap_mode; + /* imxdpuv1_disp_dump_mode(cap_mode); */ + return ret; +#endif +} + +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param cap id of the capture inpute + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_extsrc; /* block offset for extsrc */ +#if 0 + uint32_t b_off_dest; /* block offset for destination */ +#endif + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + if ((clip_height != 0) && (clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, clip_top)); + /* save the clip data */ + imxdpu->capture_mode[cap_id].clip_height = clip_height; + imxdpu->capture_mode[cap_id].clip_width = clip_width; + imxdpu->capture_mode[cap_id].clip_top = clip_top; + imxdpu->capture_mode[cap_id].clip_left = clip_left; + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[cap_id]); */ + return ret; +#endif +} +/*! + * This function enables the frame capture + * + * @param imxdpuv1_id id of the display unit + * @param cap id of the capture output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (cap == 0) { + b_off = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (enable) { + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + } + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 0); + + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMECAP4_CTR_OFFSET, reg); + + return ret; +#endif +} + +/*! + * This function triggers a shadow load + * + * @param imxdpuv1_id id of the diplay unit + * @param dest_id id of the capture dest block + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + switch (dest_id) { + case IMXDPUV1_ID_STORE4: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER_STORE4_SYNC_TRIGGER_MASK); + break; + case IMXDPUV1_ID_STORE5: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER_STORE5_SYNC_TRIGGER_MASK); + break; + + default: + return -EINVAL; + + } + return ret; +#endif +} + +/*! + * This function requests a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_request_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + imxdpuv1_shadow_load_index_t shadow_load_idx) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s(): imxdpuv1_id %d, disp %d, shadow_load_idx %d\n", + __func__, imxdpuv1_id, disp, shadow_load_idx); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + /* trigger configuration of the pipeline */ + + if ((disp == 0) || (disp == 1)) { + /* last request was complete or no request in progress, + then start a new request */ + if (imxdpu->shadow_load_state[disp][shadow_load_idx].word == 0) { + imxdpu->shadow_load_state[disp][shadow_load_idx].state. + request = IMXDPUV1_TRUE; + } else { /* check ifg the request is busy */ + IMXDPUV1_TRACE("%s(): shadow load not complete.", __func__); + return -EBUSY; + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function force a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + struct imxdpuv1_soc *imxdpu; + int i; + uint64_t temp_mask; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((disp == 0) || (disp == 1))) { + return -EINVAL; + } + + if (mask == 0) { + return -EINVAL; + } + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + for (i = 0; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + temp_mask = 1 << i; + if ((mask & temp_mask) == 0) + continue; + + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + + if ((i == IMXDPUV1_SHDLD_IDX_CONST0) || + (i == IMXDPUV1_SHDLD_IDX_CONST1)) { + fgen |= 1; + } + mask &= ~temp_mask; + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function shows the frame generators status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id) +{ +#ifndef ENABLE_IMXDPUV1_TRACE + return 0; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_PRINT("IMXDPU %d stat fg0 fg1\n" + "prim_sync_state: %10d %10d\n" + "sec_sync_state: %10d %10d\n" + "prim_sync_count: %10d %10d\n" + "sec_sync_count: %10d %10d\n" + "skew_error_count: %10d %10d\n" + "prim_fifo_empty_count: %10d %10d\n" + "sec_fifo_empty_count: %10d %10d\n" + "frame_count: %10d %10d\n" + "irq_count: %10u\n\n", + imxdpuv1_id, + imxdpu->fgen_stats[0].prim_sync_state, + imxdpu->fgen_stats[1].prim_sync_state, + imxdpu->fgen_stats[0].sec_sync_state, + imxdpu->fgen_stats[1].sec_sync_state, + imxdpu->fgen_stats[0].prim_sync_count, + imxdpu->fgen_stats[1].prim_sync_count, + imxdpu->fgen_stats[0].sec_sync_count, + imxdpu->fgen_stats[1].sec_sync_count, + imxdpu->fgen_stats[0].skew_error_count, + imxdpu->fgen_stats[1].skew_error_count, + imxdpu->fgen_stats[0].prim_fifo_empty_count, + imxdpu->fgen_stats[1].prim_fifo_empty_count, + imxdpu->fgen_stats[0].sec_fifo_empty_count, + imxdpu->fgen_stats[1].sec_fifo_empty_count, + imxdpu->fgen_stats[0].frame_count, + imxdpu->fgen_stats[1].frame_count, + imxdpu->irq_count); + + return ret; +#endif +} + +/*! + * This function enables the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, int8_t disp, bool enable) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET, reg); + + return ret; +} + +/*! + * This function sets up the constframe generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param bg_red background red + * @param bg_green background green + * @param bg_blue background blue + * @param bg_alpha background alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_constframe( + int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_shadow_load_index_t shadow_idx; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* todo: add constfram4 and constframe5 */ + if (disp == 0) { + b_off = IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST0; + } else if (disp == 1) { + b_off = IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST1; + } else { + return -EINVAL; + } + + if (imxdpu->video_mode[disp].flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: need to handle sync display case */ + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + imxdpu->video_mode[disp].vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + imxdpu->video_mode[disp].hlen - 1); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET, reg); + + /* todo: add linear light correction if needed */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTRED, bg_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTGREEN, bg_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTBLUE, bg_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTALPHA, bg_alpha)); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, disp, shadow_idx); + + /* todo: add linear light correction if needed */ + return ret; +} + +/*! + * This function sets up a layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer layer data to use + * @param layer_idx layer index to use + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer) +{ + int ret = 0; + uint32_t dynamic_offset; + uint32_t static_offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_TRACE("%s(): enable %d, primary %d, secondary %d, stream 0x%08x\n", __func__, + layer->enable, + layer->primary, + layer->secondary, + layer->stream); + imxdpu->blend_layer[layer_idx] = *layer; + + dynamic_offset = id2dynamicoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (dynamic_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + static_offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (static_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL, + imxdpu->blend_layer[layer_idx].primary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL, + imxdpu->blend_layer[layer_idx].secondary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN, + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC); + imxdpuv1_write(imxdpu, dynamic_offset, reg); + + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_0) { + + IMXDPUV1_TRACE("%s(): IMXDPUV1_DISPLAY_STREAM_0\n", __func__); + if (is_top_layer) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, reg); + } + + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 0, + IMXDPUV1_SHDLD_IDX_DISP0); + } + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_1) { + IMXDPUV1_TRACE_IRQ("%s(): IMXDPUV1_DISPLAY_STREAM_1\n", __func__); + if (is_top_layer) { + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, reg); + + } + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 1, + IMXDPUV1_SHDLD_IDX_DISP1); + } + + /* todo: add code to disable a layer */ + return ret; +} + +/*! + * This function sets global alpha for a blend layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param alpha global alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA, + alpha) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET, + reg); + + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_MODE, + IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE, + IMXDPUV1_DISABLE); + + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a blend layer secondary input + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_XPOS, x) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_YPOS, y); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_POSITION_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = y; + imxdpu->chan_data[idx].dest_left = x; + + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer or warp\n", __func__); + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_position(imxdpuv1_id, + imxdpuv1_get_eco(chan), + x, y); + } + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else { + return -EINVAL; + } + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets the source and destination crop + * position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_crop( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + if ((imxdpu->chan_data[idx].clip_height < 0) || + (imxdpu->chan_data[idx].clip_width < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = dest_top; + imxdpu->chan_data[idx].dest_left = dest_left; + imxdpu->chan_data[idx].dest_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].dest_height = IMXDPUV1_MIN(dest_height, clip_height); + imxdpu->chan_data[idx].clip_top = clip_top; + imxdpu->chan_data[idx].clip_left = clip_left; + imxdpu->chan_data[idx].clip_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].clip_height = IMXDPUV1_MIN(dest_height, clip_height); + + /* Need to check more cases here */ + if ((imxdpu->chan_data[idx].clip_height != 0) && + (imxdpu->chan_data[idx].clip_width != 0)) { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 |= + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + IMXDPUV1_ENABLE); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[idx].clip_width - 1); + } else { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 &= + ~IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK; + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[idx].dest_left - imxdpu->chan_data[idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[idx].dest_top - imxdpu->chan_data[idx].clip_top); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + imxdpuv1_get_eco(chan), + clip_top, + clip_left, + clip_width, + clip_height, + dest_top, + dest_left, + dest_width, + dest_height); + } + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else { + return -EINVAL; + } + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets initializes a channel and buffer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param src_pixel_fmt source pixel format + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param stride stride of the buffer + * @param disp_id display id + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * @param const_color constant color for clip region + * @param disp_addr display buffer physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr) +{ + int ret = 0; + imxdpuv1_channel_params_t channel; + uint32_t uv_offset = 0; + + IMXDPUV1_TRACE("%s(): " + "imxdpuv1_id %d\n" + "chan_t chan %x\n" + "src_pixel_fmt 0x%x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d\n" + "clip_left %d\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "disp_id %d\n" + "dest_top %d\n" + "dest_left %d\n" + "dest_width %d\n" + "dest_height %d\n" + "const_color 0x%x\n" + "disp_addr 0x%x\n", + __func__, + imxdpuv1_id, + chan, + src_pixel_fmt, + src_width, + src_height, + clip_top, + clip_left, + clip_width, + clip_height, + stride, + disp_id, + dest_top, + dest_left, + dest_width, + dest_height, + const_color, + disp_addr); + + channel.common.chan = chan; + channel.common.src_pixel_fmt = src_pixel_fmt; + channel.common.src_width = src_width; + channel.common.src_height = src_height; + channel.common.clip_top = clip_top; + channel.common.clip_left = clip_left; + channel.common.clip_width = clip_width; + channel.common.clip_height = clip_height; + channel.common.stride = stride; + channel.common.disp_id = disp_id; + channel.common.dest_top = dest_top; + channel.common.dest_left = dest_left; + channel.common.dest_width = dest_width; + channel.common.dest_height = dest_height; + channel.common.const_color = const_color; + channel.common.use_global_alpha = use_global_alpha; + channel.common.use_local_alpha = use_local_alpha; + + if (imxdpuv1_get_planes(src_pixel_fmt) == 2) { + uv_offset = src_width * src_height; /* works for NV12 and NV16*/ + } + ret = imxdpuv1_init_channel(imxdpuv1_id, &channel); + + ret = imxdpuv1_init_channel_buffer(imxdpuv1_id, channel.common.chan, channel.common.stride, IMXDPUV1_ROTATE_NONE, + disp_addr, + uv_offset, + 0); + + ret = imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + channel.common.chan, + channel.common.clip_top, + channel.common.clip_left, + channel.common.clip_width, + channel.common.clip_height, + channel.common.dest_top, + channel.common.dest_left, + channel.common.dest_width, + channel.common.dest_height); + +#ifdef DEBUG + { + imxdpuv1_chan_t eco_chan; + imxdpuv1_dump_channel(imxdpuv1_id, channel.common.chan); + eco_chan = imxdpuv1_get_eco(channel.common.chan); + if (eco_chan != 0) { + imxdpuv1_dump_channel(imxdpuv1_id, eco_chan); + } + } +#endif + return ret; +} + +/*! + * This function prints the video mode passed as a parameter + * + * @param *mode pointer to video mode struct to show + */ +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode) +{ + IMXDPUV1_PRINT("%s():\n", __func__); + IMXDPUV1_PRINT("\thlen %4d\n", mode->hlen); + IMXDPUV1_PRINT("\thfp %4d\n", mode->hfp); + IMXDPUV1_PRINT("\thbp %4d\n", mode->hbp); + IMXDPUV1_PRINT("\thsync %4d\n", mode->hsync); + IMXDPUV1_PRINT("\tvlen %4d\n", mode->vlen); + IMXDPUV1_PRINT("\tvfp %4d\n", mode->vfp); + IMXDPUV1_PRINT("\tvbp %4d\n", mode->vbp); + IMXDPUV1_PRINT("\tvsync %4d\n", mode->vsync); + IMXDPUV1_PRINT("\tvlen1 %4d\n", mode->vlen1); + IMXDPUV1_PRINT("\tvfp1 %4d\n", mode->vfp1); + IMXDPUV1_PRINT("\tvbp1 %4d\n", mode->vbp1); + IMXDPUV1_PRINT("\tvsync1 %4d\n", mode->vsync1); + + IMXDPUV1_PRINT("\tflags 0x%08x:\n", mode->flags); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is low\n"); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_INTERLACED) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_INTERLACED is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_LRSYNC is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_SPLIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_SPLIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_32BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_10BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_8BIT is set\n"); +} + +/*! + * Returns the bytes per pixel + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bytes_per_pixel(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, and NV16 */ + case IMXDPUV1_PIX_FMT_NV12: + return 1; /* luma */ + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return 2; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + return 3; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + return 4; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + return 0; + } +} + +/*! + * Returns the number of bits per color component for the color + * component bits register + * + * @param pixel format + * + * @return Returns the number of bits per color component for + * the color component bits register. + */ +uint32_t imxdpuv1_get_colorcomponentbits(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, NV16, YUYV, and UYVY */ + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_NV12: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 11) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x08); + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format 0x%08x", __func__, fmt); + return 0; + } + return 0; +} + +/*! + * Returns the number of planes for the pixel format + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +uint32_t imxdpuv1_get_planes(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_NV12: + return 2; + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_ARGB32: + return 1; + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns the color component bit position shifts + * + * @param pixel format + * + * @return returns the register setting for the + * colorcomponentshift register + * + */ +uint32_t imxdpuv1_get_colorcomponentshift(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + + case IMXDPUV1_PIX_FMT_NV12: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 6) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0); + case IMXDPUV1_PIX_FMT_YUYV: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + case IMXDPUV1_PIX_FMT_UYVY: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + /* 0xaaRRGGBB */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + case IMXDPUV1_PIX_FMT_AYUV: + /* 0xVVUUYYAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ABGR32: + /* 0xRRGGBBAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ARGB32: + /* 0xBBGGRRAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + /* 0xaaBBGGRR or 0xaaUUVVYY */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns true is the format has local alpha + * + * @param pixel format + * + * @return Returns true is the format has local alpha + */ +uint32_t imxdpuv1_has_localalpha(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_RGBA32: + return IMXDPUV1_TRUE; + default: + return IMXDPUV1_FALSE; + } +} + +/*! + * Returns the bits per pixel + * + * @param pixel format + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bits_per_pixel(uint32_t fmt) +{ + int ret = 0; + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV12: + ret = 8; + break; + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YVYU: + ret = 16; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + ret = 24; + break; + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + ret = 32; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format\n", __func__); + ret = 1; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for YUV + * + * @param pixel format + * + * @return returns true if the format is YUV. + */ +static bool imxdpuv1_is_yuv(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + ret = IMXDPUV1_TRUE; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_FALSE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for RGB formats + * + * @param pixel format + * + * @return returns true if the format is any supported RGB + */ +bool imxdpuv1_is_rgb(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_GENERIC_32: + ret = IMXDPUV1_FALSE; + break; + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_TRUE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Intializes buffers to be used for a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to use for this buffer + * @param stride total width in the buffer in pixels + * @param rot_mode rotatation mode + * @param phyaddr_0 buffer 0 address + * @param u_offset U offset + * @param v_offset V offset + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset) +{ + int ret = 0; + uint32_t b_off; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + int sub_idx = imxdpuv1_get_channel_subindex(chan); + bool enable_clip = IMXDPUV1_FALSE; + bool enable_buffer = IMXDPUV1_TRUE; + uint8_t enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF; + uint8_t input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE; + uint32_t fwidth; + uint32_t fheight; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].u_offset = u_offset; + imxdpu->chan_data[chan_idx].v_offset = v_offset; + + /* update stride if provided */ + if (stride != 0) { + /* todo: check stride range */ + imxdpu->chan_data[chan_idx].stride = stride; + } + + /* common fetch setup */ + if (!is_store_chan(chan)) { + /* default horizontal scan + * todo: add support for vertical and warp scans + */ + if (sub_idx == 0) { + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET, + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH, + burst_param[IMXDPUV1_BURST_HORIZONTAL]. + len) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS, + burst_param[IMXDPUV1_BURST_HORIZONTAL].buffers)); + } + /* todo: Add range checking here */ + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].src_pixel_fmt)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[chan_idx].dest_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[chan_idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[chan_idx].clip_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + if ((imxdpu->chan_data[chan_idx].clip_height != 0) && + (imxdpu->chan_data[chan_idx].clip_width != 0)) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + + enable_clip = IMXDPUV1_ENABLE; + } else { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + + imxdpu->chan_data[chan_idx].fetch_layer_prop.constantcolor0 = + imxdpu->chan_data[chan_idx].const_color; + + if (imxdpu->chan_data[chan_idx].phyaddr_0 == 0) { + enable_buffer = IMXDPUV1_FALSE; + } + if (imxdpuv1_is_yuv(imxdpu->chan_data[chan_idx].src_pixel_fmt)) { + /* TODO: need to get correct encoding range */ + enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601; + } + } + + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK; + if (chan == IMXDPUV1_CHAN_01) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0)); + } else if (chan == IMXDPUV1_CHAN_19) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1)); + } + imxdpuv1_init_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + stride, + rot_mode, + phyaddr_0, + u_offset, v_offset); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + (0x08 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + (0x00 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE) | + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) | /*needed for clip */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT, input_select)); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer channel\n", __func__); + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) + ); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_warp_chan(chan)) { + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROL_OFFSET, 0x700); + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET + + (IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch eco setup\n", __func__); + if (imxdpu->chan_data[chan_idx].src_pixel_fmt == IMXDPUV1_PIX_FMT_NV12) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0 + u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, 16) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + + /* chroma resolution*/ + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height / 2 - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width / 2 - 1); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX, 0x2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY, 0x2) + ); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR, 1)); + + /* luma resolution */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + + } else if (is_store_chan(chan)) { + imxdpu->chan_data[chan_idx].store_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferattributes0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].dest_pixel_fmt)) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE, + imxdpu->chan_data[chan_idx].stride-1); + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferdimension0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT, + imxdpu->chan_data[chan_idx].dest_height - 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - 1); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.frameoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET, + -imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET, + -imxdpu->chan_data[chan_idx].dest_top); + + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_STORE9_BASEADDRESS_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + store_layer_prop, + sizeof(store_layer_setup_t) / 4); + + if ((imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YUYV) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YVYU) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_UYVY)) { + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_STORE9_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_CONTROL_RASTERMODE, + IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422)); + } + + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to update + * @param phyaddr_0 physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t imxdpuv1_update_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + if (imxdpu->chan_data[chan_idx].use_eco_fetch == IMXDPUV1_FALSE) { + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + } +#ifdef IMXDPUV1_VERSION_0 + if (is_store_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): store channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_STORE4_BASEADDRESS_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + + /* fixme: need to handle all pipline elements */ + imxdpuv1_write_irq(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_REQUEST, 1); + + return ret; + } +#endif + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + imxdpuv1_update_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + phyaddr_0); + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch layer channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch warp channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch eco channel\n", __func__); + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0 + imxdpu->chan_data[chan_idx].u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = imxdpu->chan_data[chan_idx].phyaddr_0; + + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param params pointer to channel parameters + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel(int8_t imxdpuv1_id, imxdpuv1_channel_params_t *params) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_t chan = params->common.chan; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + /* here we use the video mode for channel frame width, todo: we may need to + add a paramter for this */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + imxdpu->chan_data[chan_idx].chan = chan; + + memset(&imxdpu->chan_data[chan_idx].fetch_layer_prop, 0, + sizeof(fetch_layer_setup_t)); + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_FALSE; + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): decode channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + if (imxdpuv1_get_planes(imxdpu->chan_data[chan_idx].src_pixel_fmt) == 2) { + if (has_fetch_eco_chan(chan)) { + imxdpuv1_channel_params_t temp_params = *params; + + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_TRUE; + temp_params.fetch_decode.chan = imxdpuv1_get_eco(params->fetch_decode.chan); + imxdpuv1_init_channel(imxdpuv1_id, &temp_params); + } else { + return -EINVAL; + } + } + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): layer channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_layer.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_layer.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_layer.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_layer.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_layer.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_layer.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_layer.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_layer.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_layer.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_layer.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_layer.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_layer.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_layer.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_layer.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_layer.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_layer.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_layer.disp_id; + + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): warp channel setup\n", __func__); + + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_warp.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_warp.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_warp.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_warp.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_warp.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_warp.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_warp.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_warp.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_warp.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_warp.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_warp.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_warp.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_warp.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_warp.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_warp.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_warp.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_warp.disp_id; + + } else if (is_fetch_eco_chan(chan)) { + + IMXDPUV1_TRACE("%s(): fetch eco channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + } else if (is_store_chan(chan)) { + IMXDPUV1_TRACE("%s(): store setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->store.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->store.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->store.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->store.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->store.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->store.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->store.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->store.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->store.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->store.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->store.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->store.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->store.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->store.const_color; + imxdpu->chan_data[chan_idx].source_id = + params->store.capture_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->store.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->store.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->store.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->store.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->store.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->store.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->store.v_phase[1][1]; + } + + } else { + IMXDPUV1_TRACE("%s(): ERROR, invalid channel type!\n", __func__); + return -EINVAL; + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Dumps the fetch layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_fetch_layer(fetch_layer_setup_t *layer) +{ + IMXDPUV1_PRINT("baseaddress 0x%08x\n" + "sourcebufferattributes 0x%08x\n" + "sourcebufferdimension h %d w %d\n" + "colorcomponentbits 0x%08x\n" + "colorcomponentshift 0x%08x\n" + "layeroffset y(top) %d x(left) %d\n" + "clipwindowoffset y(top) %d x(left) %d\n" + "clipwindowdimensions h %d w %d\n" + "constantcolor 0x%08x\n" + "layerproperty 0x%08x\n", + layer->baseaddress0, + layer->sourcebufferattributes0, + layer->sourcebufferdimension0 >> 16, + layer->sourcebufferdimension0 & 0x3fff, + layer->colorcomponentbits0, layer->colorcomponentshift0, + layer->layeroffset0 >> 16, layer->layeroffset0 & 0x3fff, + layer->clipwindowoffset0 >> 16, + layer->clipwindowoffset0 & 0x3fff, + layer->clipwindowdimensions0 >> 16, + layer->clipwindowdimensions0 & 0x3fff, + layer->constantcolor0, layer->layerproperty0); + return; +} +/*! + * Dumps the store layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_store_layer(store_layer_setup_t *layer) +{ + IMXDPUV1_TRACE( + "baseaddress0 0x%08x\n" + "destbufferattributes0 0x%08x\n" + "destbufferdimension0 h %d w %d\n" + "frameoffset0 %d\n" + "colorcomponentbits0 0x%08x\n" + "colorcomponentshift0 0x%08x\n", + layer->baseaddress0, + layer->destbufferattributes0, + layer->destbufferdimension0 >> 16, layer->destbufferdimension0 & 0x3fff, + layer->frameoffset0, + layer->colorcomponentbits0, + layer->colorcomponentshift0); + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS); + IMXDPUV1_TRACE("LAYERBLEND0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND0_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS); + IMXDPUV1_PRINT("LAYERBLEND1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND1_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS); + IMXDPUV1_PRINT("LAYERBLEND2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND2_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS); + IMXDPUV1_PRINT("LAYERBLEND3_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND3_LOCKSTATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_STATUS); + IMXDPUV1_PRINT("LAYERBLEND4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND4_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_STATUS); + IMXDPUV1_PRINT("LAYERBLEND5_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND5_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_STATUS); + IMXDPUV1_PRINT("LAYERBLEND6_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND6_LOCKSTATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST); + IMXDPUV1_PRINT("EXTDST0_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST); + IMXDPUV1_PRINT("EXTDST1_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST); + IMXDPUV1_PRINT("EXTDST4_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST); + IMXDPUV1_PRINT("EXTDST5_REQUEST: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATUS); + IMXDPUV1_PRINT("EXTDST0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATUS); + IMXDPUV1_PRINT("EXTDST1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATUS); + IMXDPUV1_PRINT("EXTDST4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATUS); + IMXDPUV1_PRINT("EXTDST5_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_STATUS); + IMXDPUV1_PRINT("FETCHDECODE2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_STATUS); + IMXDPUV1_PRINT("FETCHDECODE3_STATUS: 0x%08x\n", reg); +#endif + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS); + IMXDPUV1_PRINT("FETCHWARP2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS); + IMXDPUV1_PRINT("FETCHECO2_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS); + IMXDPUV1_PRINT("FETCHDECODE0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS); + IMXDPUV1_PRINT("FETCHECO0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS); + IMXDPUV1_PRINT("FETCHDECODE1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS); + IMXDPUV1_PRINT("FETCHECO1_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS); + IMXDPUV1_PRINT("FETCHLAYER0_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER1_STATUS); + IMXDPUV1_PRINT("FETCHLAYER1_STATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the channel data + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to dump + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + if (is_store_chan(chan)) { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_store_layer(&imxdpu->chan_data[chan_idx].store_layer_prop); + + } else { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "u_offset 0x%08x\n" + "v_offset 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].u_offset, + imxdpu->chan_data[chan_idx].v_offset, + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_fetch_layer(&imxdpu->chan_data[chan_idx].fetch_layer_prop); + } + return ret; +} + +/*! + * Shows the interrupt status registers + * + * @param id of the diplay unit + * + */ +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id) +{ + int i; + struct imxdpuv1_soc *imxdpu; + uint32_t reg; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTMASK%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTENABLE%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTSTATUS%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTENABLE0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTENABLE%i: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTSTATUS%i: 0x%08x\n", i, reg); + } +} diff --git a/drivers/video/imxdpuv1_be.h b/drivers/video/imxdpuv1_be.h new file mode 100644 index 0000000000..a004bf8244 --- /dev/null +++ b/drivers/video/imxdpuv1_be.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_BE_H +#define IMXDPUV1_BE_H + +struct fetch_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t color_bits; + uint32_t color_shift; + uint32_t layer_offset; + uint32_t clip_offset; + uint32_t clip_dimension; + uint32_t const_color; + uint32_t layer_property; + uint32_t frame_dimension; + uint32_t frame_resample; +}; + +struct store_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t frame_offset; + uint32_t color_bits; + uint32_t color_shift; +}; +struct rop_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct matrix_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct hscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; +}; +struct vscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; + uint32_t setup3; + uint32_t setup4; + uint32_t setup5; +}; +struct blitblend_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t const_color; + uint32_t red_func; + uint32_t green_func; + uint32_t blue_func; + uint32_t alpha_func; + uint32_t blend_mode1; + uint32_t blend_mode2; +}; +struct engcfg_unit { + uint32_t fetchpersp9_dynamic; + uint32_t fetchdecode9_dynamic; + uint32_t rop9_dynamic; + uint32_t matrix9_dynamic; + uint32_t hscaler9_dynamic; + uint32_t vscaler9_dynamic; + uint32_t blitblend9_dynamic; + uint32_t store9_dynamic; +}; + +struct be_blit_cfg { + struct fetch_unit fetch_decode; + struct fetch_unit fetch_persp; + struct fetch_unit fetch_eco; + struct store_unit store; + struct rop_unit rop; + struct matrix_unit matrix; + struct hscaler_unit hscaler; + struct vscaler_unit vscaler; + struct blitblend_unit blitblend; + struct engcfg_unit engcfg; +}; + +/* PRIVATE DATA */ +struct imxdpuv1_info { + /*reg */ + void __iomem *base; +}; + +#define IMXDPUV1_IOC_MAGIC 'i' +#define IMXDPUV1_IOC_BLIT _IOW(IMXDPUV1_IOC_MAGIC, 1, struct be_blit_cfg) +#define IMXDPUV1_IOC_WAIT _IO(IMXDPUV1_IOC_MAGIC, 2) + +void imxdpuv1_be_irq_handler(int8_t imxdpuv1_id, int8_t irq); +int imxdpuv1_be_init(int8_t imxdpuv1_id, void __iomem *imxdpuv1_base); +int imxdpuv1_be_blit(struct imxdpuv1_info *imxdpu, struct be_blit_cfg *cfg); +int imxdpuv1_be_wait_shadow_load(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_wait_complete(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_load(struct imxdpuv1_info *imxdpu, void __user *p); +int imxdpuv1_be_wait(struct imxdpuv1_info *imxdpu); + +#endif diff --git a/drivers/video/imxdpuv1_private.h b/drivers/video/imxdpuv1_private.h new file mode 100644 index 0000000000..b874c38b47 --- /dev/null +++ b/drivers/video/imxdpuv1_private.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Instance: imxdpuv1_private.h */ +#ifndef IMXDPUV1_PRIVATE_H +#define IMXDPUV1_PRIVATE_H + +#include +#include + +#include +#include "imxdpuv1.h" + +typedef enum { + IMXDPUV1_BURST_UNKNOWN = 0, + IMXDPUV1_BURST_LEFT_RIGHT_DOWN, + IMXDPUV1_BURST_HORIZONTAL, + IMXDPUV1_BURST_VERTICAL, + IMXDPUV1_BURST_FREE, +} imxdpuv1_burst_t; + +#define INTSTAT0_BIT(__bit__) (1U<<(__bit__)) +#define INTSTAT1_BIT(__bit__) (1U<<((__bit__)-32)) +#define INTSTAT2_BIT(__bit__) (1U<<((__bit__)-64)) + +struct imxdpuv1_irq_node { + int(*handler) (int, void *); + const char *name; + void *data; + uint32_t flags; +}; + +/* Generic definitions that are common to many registers */ +#define IMXDPUV1_COLOR_BITSALPHA0_MASK 0xFU +#define IMXDPUV1_COLOR_BITSALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_BITSBLUE0_MASK 0xF00U +#define IMXDPUV1_COLOR_BITSBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_BITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_COLOR_BITSGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_BITSRED0_MASK 0xF000000U +#define IMXDPUV1_COLOR_BITSRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_SHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_COLOR_SHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_SHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_COLOR_SHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_SHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_COLOR_SHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_SHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_COLOR_SHIFTRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +/* these are common for fetch but not store */ +#define IMXDPUV1_BUFF_ATTR_STRIDE_MASK 0xFFFFU +#define IMXDPUV1_BUFF_ATTR_STRIDE_SHIFT 0U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_MASK 0x3F0000U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_SHIFT 16U + +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_SHIFT 16U +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_MASK 0x3FFF0000U + +#define IMXDPUV1_LAYER_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_LAYER_XOFFSET_SHIFT 0U +#define IMXDPUV1_LAYER_XSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_XSBIT_SHIFT 0U + +#define IMXDPUV1_LAYER_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_LAYER_YOFFSET_SHIFT 16U +#define IMXDPUV1_LAYER_YSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_YSBIT_SHIFT 16U + +#define IMXDPUV1_CLIP_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_CLIP_XOFFSET_SHIFT 0U +#define IMXDPUV1_CLIP_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_CLIP_YOFFSET_SHIFT 16U + +#define IMXDPUV1_CLIP_WIDTH_MASK 0x3FFFU +#define IMXDPUV1_CLIP_WIDTH_SHIFT 0U +#define IMXDPUV1_CLIP_HEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CLIP_HEIGHT_SHIFT 16U + +#define IMXDPUV1_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_EMPTYFRAME_SHIFT 31U + +#define IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE 0U +#define IMXDPUV1_PIXENGCFG_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_SRC_SEL_SHIFT 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_SHIFT 8U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_CLKEN_SHIFT 24U +/* Field Value: _CLKEN__DISABLE, Clock for block is disabled */ +#define IMXDPUV1_PIXENGCFG_CLKEN__DISABLE 0U +/* Field Value: _CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC 0x1U +/* Field Value: _CLKEN__FULL, Clock for block is without gating */ +#define IMXDPUV1_PIXENGCFG_CLKEN__FULL 0x3U + + +/* Register: IMXDPUV1_LayerProperty0 Common Bits */ +#define IMXDPUV1_LAYERPROPERTY_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_LAYERPROPERTY_RESET_VALUE 0x80000100U +#define IMXDPUV1_LAYERPROPERTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_SHIFT 0U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_MASK 0x30U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_MASK 0x100U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_SHIFT 8U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_MASK 0x200U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_SHIFT 9U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_MASK 0x400U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_SHIFT 10U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_MASK 0x800U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_SHIFT 11U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_MASK 0x1000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_SHIFT 12U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_MASK 0x2000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_SHIFT 13U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_MASK 0x4000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_SHIFT 14U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_MASK 0x8000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_SHIFT 15U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_MASK 0x10000U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_SHIFT 16U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_MASK 0x60000U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_MASK 0x100000U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_SHIFT 20U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_SHIFT 30U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_SHIFT 31U + +typedef struct { + /* Source buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Source buffer attributes for layer 0. */ + uint32_t sourcebufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t sourcebufferdimension0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; + /* Position of layer 0 within the destination frame. */ + uint32_t layeroffset0; + /* Clip window position for layer 0. */ + uint32_t clipwindowoffset0; + /* Clip window size for layer 0. */ + uint32_t clipwindowdimensions0; + /* Constant color for layer 0. */ + uint32_t constantcolor0; + /* Common properties of layer 0. */ + uint32_t layerproperty0; +} fetch_layer_setup_t; + +typedef struct { + /* Destination buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Destination buffer attributes for layer 0. */ + uint32_t destbufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t destbufferdimension0; + /* Frame offset of layer 0. */ + uint32_t frameoffset0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; +} store_layer_setup_t; + +typedef enum { + IMXDPUV1_SHDLD_IDX_DISP0 = (0), + IMXDPUV1_SHDLD_IDX_DISP1 = (1), + IMXDPUV1_SHDLD_IDX_CONST0 = (2), /* IMXDPUV1_ID_CONSTFRAME0 */ + IMXDPUV1_SHDLD_IDX_CONST1 = (3), /* IMXDPUV1_ID_CONSTFRAME1 */ + IMXDPUV1_SHDLD_IDX_CHAN_00 = (4), /* IMXDPUV1_ID_FETCHDECODE2 */ + IMXDPUV1_SHDLD_IDX_CHAN_01 = (5), /* IMXDPUV1_ID_FETCHDECODE0 */ + IMXDPUV1_SHDLD_IDX_CHAN_02 = (6), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_03 = (7), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_04 = (8), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_05 = (9), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_06 = (10), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_07 = (11), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_08 = (12), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_09 = (13), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_10 = (14), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_11 = (15), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_12 = (16), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_13 = (17), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_14 = (18), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_15 = (19), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_16 = (20), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_17 = (21), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_18 = (22), /* IMXDPUV1_ID_FETCHDECODE3 */ + IMXDPUV1_SHDLD_IDX_CHAN_19 = (23), /* IMXDPUV1_ID_FETCHDECODE1 */ + IMXDPUV1_SHDLD_IDX_CHAN_20 = (24), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_21 = (25), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_22 = (26), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_23 = (27), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_24 = (28), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_25 = (29), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_26 = (30), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_27 = (31), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_28 = (32), /* IMXDPUV1_ID_FETCHECO0*/ + IMXDPUV1_SHDLD_IDX_CHAN_29 = (33), /* IMXDPUV1_ID_FETCHECO1*/ + IMXDPUV1_SHDLD_IDX_CHAN_30 = (34), /* IMXDPUV1_ID_FETCHECO2*/ + IMXDPUV1_SHDLD_IDX_MAX = (35), +} imxdpuv1_shadow_load_index_t; + +typedef struct { + bool prim_sync_state; + bool sec_sync_state; + uint32_t prim_sync_count; + uint32_t sec_sync_count; + uint32_t skew_error_count; + uint32_t prim_fifo_empty_count; + uint32_t sec_fifo_empty_count; + uint32_t frame_count; +} frame_gen_stats_t; + +/*! + * Definition of IMXDPU channel structure + */ +typedef struct { + int8_t disp_id; /* Iris instance id of "owner" */ + + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + int16_t src_top; + int16_t src_left; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint16_t const_color; + + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + + bool use_video_proc; + bool interlaced; + bool use_eco_fetch; + bool use_global_alpha; + bool use_local_alpha; + + /* note: dma_addr_t changes for 64-bit arch */ + dma_addr_t phyaddr_0; + + uint32_t u_offset; + uint32_t v_offset; + + uint8_t blend_layer; + uint8_t destination_stream; + uint8_t source_id; + + imxdpuv1_rotate_mode_t rot_mode; + + /* todo add features sub-windows, upscaling, warping */ + fetch_layer_setup_t fetch_layer_prop; + store_layer_setup_t store_layer_prop; + + bool in_use; + + /* todo: add channel features */ +} chan_private_t; + +typedef union { + struct { + uint8_t request; + uint8_t processing; + uint8_t complete; + uint8_t trys; + } state; + uint32_t word; +} imxdpuv1_shadow_state_t; + +/* PRIVATE DATA */ +struct imxdpuv1_soc { + int8_t devtype; + int8_t online; + uint32_t enabled_int[3]; + struct imxdpuv1_irq_node irq_list[IMXDPUV1_INTERRUPT_MAX]; + + struct device *dev; + struct imxdpuv1_videomode video_mode[IMXDPUV1_NUM_DI]; + struct imxdpuv1_videomode capture_mode[IMXDPUV1_NUM_CI]; + frame_gen_stats_t fgen_stats[IMXDPUV1_NUM_DI]; + uint32_t irq_count; + + + /* + * Bypass reset to avoid display channel being + * stopped by probe since it may starts to work + * in bootloader. + */ + int8_t bypass_reset; + + /* todo: need to decide where the locking is implemented */ + + /*clk*/ + + /*irq*/ + + /*reg*/ + void __iomem *base; + + /*use count*/ + imxdpuv1_layer_t blend_layer[IMXDPUV1_LAYER_MAX]; + chan_private_t chan_data[IMXDPUV1_CHAN_IDX_MAX]; + + uint8_t shadow_load_pending[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; + imxdpuv1_shadow_state_t shadow_load_state[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; +}; + + + +/* PRIVATE FUNCTIONS */ +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read(_inst_, _offset_) _imxdpuv1_read(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read_irq(_inst_, _offset_) _imxdpuv1_read_irq(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +void _imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write(_inst_, _value_, _offset_) _imxdpuv1_write(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write_irq(_inst_, _value_, _offset_) _imxdpuv1_write_irq(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, void *values, uint32_t cnt, char *file, int line); +#define imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_) _imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_, __FILE__, __LINE__) + +/* mapping of RGB, Tcon, or static values to output */ +#define IMXDPUV1_TCON_MAPBIT__RGB(_x_) ((_x_)) +#define IMXDPUV1_TCON_MAPBIT__Tsig(_x_) ((_x_) + 30) +#define IMXDPUV1_TCON_MAPBIT__HIGH 42U +#define IMXDPUV1_TCON_MAPBIT__LOW 43U + +/* these match the bit definitions for the shadlow load + request registers + */ +typedef enum { + IMXDPUV1_SHLDREQID_FETCHDECODE9 = 0, + IMXDPUV1_SHLDREQID_FETCHPERSP9, + IMXDPUV1_SHLDREQID_FETCHECO9, + IMXDPUV1_SHLDREQID_CONSTFRAME0, + IMXDPUV1_SHLDREQID_CONSTFRAME4, + IMXDPUV1_SHLDREQID_CONSTFRAME1, + IMXDPUV1_SHLDREQID_CONSTFRAME5, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_EXTSRC4, + IMXDPUV1_SHLDREQID_EXTSRC5, + IMXDPUV1_SHLDREQID_FETCHDECODE2, + IMXDPUV1_SHLDREQID_FETCHDECODE3, +#endif + IMXDPUV1_SHLDREQID_FETCHWARP2, + IMXDPUV1_SHLDREQID_FETCHECO2, + IMXDPUV1_SHLDREQID_FETCHDECODE0, + IMXDPUV1_SHLDREQID_FETCHECO0, + IMXDPUV1_SHLDREQID_FETCHDECODE1, + IMXDPUV1_SHLDREQID_FETCHECO1, + IMXDPUV1_SHLDREQID_FETCHLAYER0, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_FETCHLAYER1, + IMXDPUV1_SHLDREQID_EXTSRC0, + IMXDPUV1_SHLDREQID_EXTSRC1 +#endif +} imxdpuv1_shadow_load_req_t; + +#define IMXDPUV1_PIXENGCFG_DIVIDER_RESET 0x80 + +#endif /* IMXDPUV1_PRIVATE_H */ + diff --git a/include/imxdpuv1.h b/include/imxdpuv1.h new file mode 100644 index 0000000000..cb12bb8c0f --- /dev/null +++ b/include/imxdpuv1.h @@ -0,0 +1,998 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_H +#define IMXDPUV1_H + +#include +#include + +/* these will be removed */ +#undef IMXDPUV1_VERSION_0 +#define IMXDPUV1_VERSION_1 + +/* #define DEBUG */ +/* #define ENABLE_IMXDPUV1_TRACE */ +/* #define ENABLE_IMXDPUV1_TRACE_REG */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_READ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_WRITE */ + +#ifdef ENABLE_IMXDPUV1_TRACE +#define IMXDPUV1_TRACE(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ +#define IMXDPUV1_TRACE_IRQ(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_IRQ(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +#define IMXDPUV1_TRACE_REG(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_REG(fmt, ...) do {} while (0) +#endif + +#define IMXDPUV1_PRINT(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) + +/* #define IMXDPUV1_TCON0_MAP_24BIT_0_23 */ +/* #define IMXDPUV1_TCON1_MAP_24BIT_0_23 */ + +/* todo: this need to come from device tree */ +#define IMXDPUV1_NUM_DI_MAX 2 +#define IMXDPUV1_MAX_NUM 2 +#define IMXDPUV1_NUM_DI 2 +#define IMXDPUV1_NUM_CI 2 +#define IMXDPUV1_REGS_BASE_PHY0 0x56180000 +#define IMXDPUV1_REGS_BASE_PHY1 0x57180000 +#define IMXDPUV1_REGS_BASE_SIZE 0x14000 + +#ifdef IMXDPUV1_VERSION_0 +#define IMXDPUV1_ENABLE_INTSTAT2 +#endif +#define IMXDPUV1_SET_FIELD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +#define IMXDPUV1_GET_FIELD(field, reg) (((reg)&(field ## _MASK)) >> (field ## _SHIFT)) + +/* + IMXDPU windows, planes, layers, streams + + IMXDPU hardware documentation confuses the meaning of layers and + planes. These are software usages of these terms. + + window - a logical buffer of pixels in a rectangular arrangment. + Image, Integral and video planes suport one window. + Fractional and warp plane support 8 windows. Blending is not + supported between the sub-windows of a fractional or warp plane. + + sub-window - one of the eight logical windows of a fractional or warp + plane. + + channel - the logical DMA configuration for etiher a fetch or store unit + + plane - a plane is a hardware supported feature. There are four types + of display planes: + + video x2 + fractional x2 + intergral x2 + warp + + layer - each of the 7 planes is fed to a layer blender. Full Alpha + blending is supported for all of the planes fed to the layer + blender. + + streams - the layer bleder produces four streams: two normal streams + (0 and 1) and two panic streams (4 and 5). + + In normal mode, streams 0 and 1 are fed to the displays. + In panic mode, streams 4 and 5 are fed to the displays. +*/ + + +/*! + * Enumeration of IMXDPU blend mode flags + */ +typedef enum { + IMXDPUV1_PLANE_CLUT = 1 << 0, /* Color lookup */ + IMXDPUV1_PLANE_DECODE = 1 << 1, /* Decode compressed bufers */ + IMXDPUV1_PLANE_ETERNAL_ALPHA = 1 << 2, /* supports external alpha buffer */ + IMXDPUV1_PLANE_VIDEO_PROC = 1 << 2, /* Gamma, Matrix, Scaler, histogram */ + IMXDPUV1_PLANE_PLANAR = 1 << 3, /* Support Planar pixel buffers*/ + IMXDPUV1_PLANE_WARP = 1 << 4, /* Warping */ + IMXDPUV1_PLANE_MULTIWINDOW = 1 << 5, /* Support multiple buffers per plane */ + IMXDPUV1_PLANE_CAPTURE = 1 << 6, /* Video capture */ +} imxdpuv1_plane_features_t; + +/*! + * Enumeration of IMXDPU layer blend mode flags + */ +typedef enum { + IMXDPUV1_LAYER_NONE = 1 << 0, /* Disable blending */ + IMXDPUV1_LAYER_TRANSPARENCY = 1 << 1, /* Transparency */ + IMXDPUV1_LAYER_GLOBAL_ALPHA = 1 << 2, /* Global alpha mode */ + IMXDPUV1_LAYER_LOCAL_ALPHA = 1 << 3, /* Alpha contained in source buffer */ + IMXDPUV1_LAYER_EXTERN_ALPHA = 1 << 4, /* Alpha is contained in a separate plane */ + IMXDPUV1_LAYER_PRE_MULITPLY = 1 << 5, /* Pre-multiply alpha mode */ +} imxdpuv1_layer_blend_modes_t; + +/*! + * Enumeration of IMXDPU layers + */ +typedef enum { + IMXDPUV1_LAYER_0 = 0, + IMXDPUV1_LAYER_1, + IMXDPUV1_LAYER_2, + IMXDPUV1_LAYER_3, + IMXDPUV1_LAYER_4, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_LAYER_5, + IMXDPUV1_LAYER_6, +#endif + IMXDPUV1_LAYER_MAX, +} imxdpuv1_layer_idx_t; + +/*! + * Enumeration of IMXDPU sub-windows + */ +typedef enum { + IMXDPUV1_SUBWINDOW_NONE = 0, + IMXDPUV1_SUBWINDOW_1, + IMXDPUV1_SUBWINDOW_2, + IMXDPUV1_SUBWINDOW_3, + IMXDPUV1_SUBWINDOW_4, + IMXDPUV1_SUBWINDOW_5, + IMXDPUV1_SUBWINDOW_6, + IMXDPUV1_SUBWINDOW_7, + IMXDPUV1_SUBWINDOW_8, +} imxdpuv1_subwindow_id_t; + +/*! + * Enumeration of IMXDPU display streams + */ +typedef enum { + IMXDPUV1_DISPLAY_STREAM_NONE = (0), + IMXDPUV1_DISPLAY_STREAM_0 = (1U<<0), + IMXDPUV1_DISPLAY_STREAM_1 = (1U<<1), + IMXDPUV1_DISPLAY_STREAM_4 = (1U<<4), + IMXDPUV1_DISPLAY_STREAM_5 = (1U<<5), +} imxdpuv1_display_stream_t; + +/*! + * Enumeration of IMXDPU rotation modes + */ +typedef enum { + /* todo: these need to aligh to imxdpu scan direction */ + IMXDPUV1_ROTATE_NONE = 0, + IMXDPUV1_ROTATE_VERT_FLIP = 1, + IMXDPUV1_ROTATE_HORIZ_FLIP = 2, + IMXDPUV1_ROTATE_180 = 3, + IMXDPUV1_ROTATE_90_RIGHT = 4, + IMXDPUV1_ROTATE_90_RIGHT_VFLIP = 5, + IMXDPUV1_ROTATE_90_RIGHT_HFLIP = 6, + IMXDPUV1_ROTATE_90_LEFT = 7, +} imxdpuv1_rotate_mode_t; + + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IMXDPUV1_OUTPUT_BUFFER = 0, /*!< Buffer for output from IMXDPU BLIT or capture */ + IMXDPUV1_ALPHA_IN_BUFFER = 1, /*!< Buffer for alpha input to IMXDPU */ + IMXDPUV1_GRAPH_IN_BUFFER = 2, /*!< Buffer for graphics input to IMXDPU */ + IMXDPUV1_VIDEO_IN_BUFFER = 3, /*!< Buffer for video input to IMXDPU */ +} imxdpuv1_buffer_t; + +#ifdef IMXDPUV1_VERSION_0 +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHPERSP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_EXTSRC4, + IMXDPUV1_ID_STORE4, + IMXDPUV1_ID_EXTSRC5, + IMXDPUV1_ID_STORE5, + IMXDPUV1_ID_FETCHDECODE2, + IMXDPUV1_ID_FETCHDECODE3, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_FETCHLAYER1, + IMXDPUV1_ID_GAMMACOR4, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_HISTOGRAM4, + IMXDPUV1_ID_GAMMACOR5, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_HISTOGRAM5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_LAYERBLEND4, + IMXDPUV1_ID_LAYERBLEND5, + IMXDPUV1_ID_LAYERBLEND6, + IMXDPUV1_ID_EXTSRC0, + IMXDPUV1_ID_EXTSRC1, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEDUMP0, + IMXDPUV1_ID_FRAMEDUMP1, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_CAPENGCFG, + IMXDPUV1_ID_FRAMECAP4, + IMXDPUV1_ID_FRAMECAP5, + IMXDPUV1_ID_ANALYSER4, + IMXDPUV1_ID_ANALYSER5, + /* the following are added arbitrarily */ + IMXDPUV1_ID_DPUXPC, + +} imxdpuv1_id_t; +#else +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHWARP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_DPUXPC, +} imxdpuv1_id_t; +#endif + +#ifdef IMXDPUV1_VERSION_0 +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_EXTSRC4 = 1U << 8, + IMXDPUV1_SHDLD_EXTSRC5 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE2 = 1U << 10, + IMXDPUV1_SHDLD_FETCHDECODE3 = 1U << 11, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 13, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 14, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 15, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 16, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 17, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 18, + IMXDPUV1_SHDLD_FETCHLAYER1 = 1U << 19, + IMXDPUV1_SHDLD_EXTSRC0 = 1U << 20, + IMXDPUV1_SHDLD_EXTSRC1 = 1U << 21, +} imxdpuv1_shadow_load_req_id_t; +#else +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 8, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 10, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 11, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 13, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 14, + + IMXDPUV1_SHDLD_EXTSRC4 = 0, + IMXDPUV1_SHDLD_EXTSRC5 = 0, + IMXDPUV1_SHDLD_FETCHDECODE2 = 0, + IMXDPUV1_SHDLD_FETCHDECODE3 = 0, + IMXDPUV1_SHDLD_FETCHLAYER1 = 0, + IMXDPUV1_SHDLD_EXTSRC0 = 0, + IMXDPUV1_SHDLD_EXTSRC1 = 0, + +} imxdpuv1_shadow_load_req_id_t; + + +#endif +typedef struct { + imxdpuv1_id_t primary; + imxdpuv1_id_t secondary; + imxdpuv1_display_stream_t stream; + bool enable; +} imxdpuv1_layer_t; + +typedef enum { + /* Fetch Channels */ + IMXDPUV1_CHAN_IDX_IN_FIRST = 0, + IMXDPUV1_CHAN_IDX_00 = 0, /* IMXDPUV1_ID_SRC_FETCHDECODE2 */ + IMXDPUV1_CHAN_IDX_01, /* IMXDPUV1_ID_SRC_FETCHDECODE0 */ + IMXDPUV1_CHAN_IDX_02, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_03, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_04, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_05, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_06, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_07, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_08, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_09, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_10, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_11, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_12, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_13, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_14, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_15, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_16, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_17, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_18, /* IMXDPUV1_ID_SRC_FETCHDECODE3 */ + IMXDPUV1_CHAN_IDX_19, /* IMXDPUV1_ID_SRC_FETCHDECODE1 */ + IMXDPUV1_CHAN_IDX_20, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_21, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_22, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_23, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_24, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_25, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_26, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_27, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_28, /* IMXDPUV1_ID_SRC_ECO0 */ + IMXDPUV1_CHAN_IDX_29, /* IMXDPUV1_ID_SRC_ECO1 */ + IMXDPUV1_CHAN_IDX_30, /* IMXDPUV1_ID_SRC_ECO2 */ + IMXDPUV1_CHAN_IDX_IN_MAX, /* Last fetch channel + 1 */ + + /* Store Channels */ + IMXDPUV1_CHAN_IDX_OUT_FIRST = 32, + IMXDPUV1_CHAN_IDX_32 = 32,/* IMXDPUV1_ID_DST_STORE4 */ + IMXDPUV1_CHAN_IDX_33, /* IMXDPUV1_ID_DST_STORE5 */ + IMXDPUV1_CHAN_IDX_OUT_MAX,/* Last fetch channel + 1 */ + IMXDPUV1_CHAN_IDX_MAX = IMXDPUV1_CHAN_IDX_OUT_MAX, +} imxdpuv1_chan_idx_t; + +typedef enum { + IMXDPUV1_SUB_NONE = 0, + IMXDPUV1_SUB_1 = 1U << 0, /* IMXDPUV1_ID_FETCHLAYER0, layer 1 */ + IMXDPUV1_SUB_2 = 1U << 1, /* IMXDPUV1_ID_FETCHLAYER0, layer 2 */ + IMXDPUV1_SUB_3 = 1U << 2, /* IMXDPUV1_ID_FETCHLAYER0, layer 3 */ + IMXDPUV1_SUB_4 = 1U << 3, /* IMXDPUV1_ID_FETCHLAYER0, layer 4 */ + IMXDPUV1_SUB_5 = 1U << 4, /* IMXDPUV1_ID_FETCHLAYER0, layer 5 */ + IMXDPUV1_SUB_6 = 1U << 5, /* IMXDPUV1_ID_FETCHLAYER0, layer 6 */ + IMXDPUV1_SUB_7 = 1U << 6, /* IMXDPUV1_ID_FETCHLAYER0, layer 7 */ + IMXDPUV1_SUB_8 = 1U << 7, /* IMXDPUV1_ID_FETCHLAYER0, layer 8 */ +} imxdpuv1_chan_sub_idx_t; + +/* IMXDPU Channel + * Consistist of four fields + * src - block id of source or destination + * sec - block id of secondary source for fetcheco + * sub - sub index of block for fetchlayer or fetchwarp + * idx - logical channel index + * + */ +#define make_channel(__blk_id, __eco_id, __sub, __idx) \ +(((__u32)(__idx)<<0)|((__u32)(__eco_id)<<8)|((__u32)(__sub)<<16)|((__u32)(__blk_id)<<24)) + +#define get_channel_blk(chan) (((__u32)(chan) >> 24) & 0xff) +#define get_channel_sub(chan) (((__u32)(chan) >> 16) & 0xff) +#define get_eco_idx(chan) (((__u32)(chan) >> 8) & 0xff) +#define get_channel_idx(chan) (((__u32)(chan) >> 0) & 0xff) +#define IMXDPUV1_SUBCHAN_LAYER_OFFSET 0x28 + +typedef enum { +#ifdef IMXDPUV1_VERSION_0 + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(IMXDPUV1_ID_FETCHDECODE2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(IMXDPUV1_ID_FETCHDECODE3, 30, IMXDPUV1_SUB_NONE, 18), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 20), + IMXDPUV1_CHAN_21 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 21), + IMXDPUV1_CHAN_22 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 22), + IMXDPUV1_CHAN_23 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 23), + IMXDPUV1_CHAN_24 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 24), + IMXDPUV1_CHAN_25 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 25), + IMXDPUV1_CHAN_26 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 26), + IMXDPUV1_CHAN_27 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 27), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(IMXDPUV1_ID_STORE4, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 32), + IMXDPUV1_CHAN_33 = make_channel(IMXDPUV1_ID_STORE5, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 33), +#else + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_21 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_22 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_23 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_24 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_25 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_26 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_27 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_33 = make_channel(0, 0, 0, 0), +#endif +} imxdpuv1_chan_t; + +/* Aliases for Channels */ +#define IMXDPUV1_CHAN_VIDEO_0 IMXDPUV1_CHAN_01 +#define IMXDPUV1_CHAN_VIDEO_1 IMXDPUV1_CHAN_19 + +#define IMXDPUV1_CHAN_INTEGRAL_0 IMXDPUV1_CHAN_00 +#define IMXDPUV1_CHAN_INTEGRAL_1 IMXDPUV1_CHAN_18 + +#define IMXDPUV1_CHAN_FRACTIONAL_0_1 IMXDPUV1_CHAN_02 +#define IMXDPUV1_CHAN_FRACTIONAL_0_2 IMXDPUV1_CHAN_03 +#define IMXDPUV1_CHAN_FRACTIONAL_0_3 IMXDPUV1_CHAN_04 +#define IMXDPUV1_CHAN_FRACTIONAL_0_4 IMXDPUV1_CHAN_05 +#define IMXDPUV1_CHAN_FRACTIONAL_0_5 IMXDPUV1_CHAN_06 +#define IMXDPUV1_CHAN_FRACTIONAL_0_6 IMXDPUV1_CHAN_07 +#define IMXDPUV1_CHAN_FRACTIONAL_0_7 IMXDPUV1_CHAN_08 +#define IMXDPUV1_CHAN_FRACTIONAL_0_8 IMXDPUV1_CHAN_09 + +#define IMXDPUV1_CHAN_FRACTIONAL_1_1 IMXDPUV1_CHAN_20 +#define IMXDPUV1_CHAN_FRACTIONAL_1_2 IMXDPUV1_CHAN_21 +#define IMXDPUV1_CHAN_FRACTIONAL_1_3 IMXDPUV1_CHAN_22 +#define IMXDPUV1_CHAN_FRACTIONAL_1_4 IMXDPUV1_CHAN_23 +#define IMXDPUV1_CHAN_FRACTIONAL_1_5 IMXDPUV1_CHAN_24 +#define IMXDPUV1_CHAN_FRACTIONAL_1_6 IMXDPUV1_CHAN_25 +#define IMXDPUV1_CHAN_FRACTIONAL_1_7 IMXDPUV1_CHAN_26 +#define IMXDPUV1_CHAN_FRACTIONAL_1_8 IMXDPUV1_CHAN_27 + +#define IMXDPUV1_CHAN_WARP_2_1 IMXDPUV1_CHAN_10 +#define IMXDPUV1_CHAN_WARP_2_2 IMXDPUV1_CHAN_11 +#define IMXDPUV1_CHAN_WARP_2_3 IMXDPUV1_CHAN_12 +#define IMXDPUV1_CHAN_WARP_2_4 IMXDPUV1_CHAN_13 +#define IMXDPUV1_CHAN_WARP_2_5 IMXDPUV1_CHAN_14 +#define IMXDPUV1_CHAN_WARP_2_6 IMXDPUV1_CHAN_15 +#define IMXDPUV1_CHAN_WARP_2_7 IMXDPUV1_CHAN_16 +#define IMXDPUV1_CHAN_WARP_2_8 IMXDPUV1_CHAN_17 + +#define IMXDPUV1_CHAN_CAPTURE_0 IMXDPUV1_CHAN_32 +#define IMXDPUV1_CHAN_CAPTURE_1 IMXDPUV1_CHAN_33 + + +/* IMXDPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#ifdef fourcc +#warning "fourcc is already defined ... redeifining it here!" +#undef fourcc +#endif +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + + +/*! @} */ +/*! @name Generic Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_GENERIC fourcc('D', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_32 fourcc('D', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_16 fourcc('D', 'P', 'U', '2') /*!< IPU Generic Data */ + +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IMXDPUV1_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IMXDPUV1_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 16 RGB-5-6-5 */ +#define IMXDPUV1_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */ +#define IMXDPUV1_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */ +#define IMXDPUV1_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IMXDPUV1_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ARGB32 fourcc('A', 'R', 'G', 'B') /*!< 32 ARGB-8-8-8-8 */ + +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IMXDPUV1_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +#define IMXDPUV1_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */ +#define IMXDPUV1_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */ + +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IMXDPUV1_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define IMXDPUV1_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ + +#define IMXDPUV1_CAP_FMT_RGB24 fourcc('R', 'G', 'B', '3') +#define IMXDPUV1_CAP_FMT_BT656 fourcc('B', '6', '5', '6') +#define IMXDPUV1_CAP_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') + +struct imxdpuv1_soc; +/*! + * Definition of IMXDPU rectangle structure + */ +typedef struct { + int16_t top; /* y coordinate of top/left pixel */ + int16_t left; /* x coordinate top/left pixel */ + int16_t width; + int16_t height; +} imxdpuv1_rect_t; + + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } common; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t capture_id; /* disp_id/capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } store; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } fetch_decode; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_layer; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_warp; +} imxdpuv1_channel_params_t; + +/*! + * Enumeration of IMXDPU video mode flags + */ +enum imxdpuv1_mode_flags { + /* 1 is active high 0 is active low */ + IMXDPUV1_MODE_FLAGS_HSYNC_POL = 1 << 0, + IMXDPUV1_MODE_FLAGS_VSYNC_POL = 1 << 1, + IMXDPUV1_MODE_FLAGS_DE_POL = 1 << 2, + + /* drive data on positive .edge */ + IMXDPUV1_MODE_FLAGS_CLK_POL = 1 << 3, + + IMXDPUV1_MODE_FLAGS_INTERLACED = 1 << 4 , + + /* Left/Right Synchronous display mode, both display pipe are + combined to make one display. All mode timings are divided by + two for each half screen. + Note: This may not be needed we may force this for any width + over ~2048 + */ + IMXDPUV1_MODE_FLAGS_LRSYNC = 1 << 8, + + /* Split mode each pipe is split into two displays */ + IMXDPUV1_MODE_FLAGS_SPLIT = 1 << 9, + + IMXDPUV1_MODE_FLAGS_32BIT = 1 << 16, + IMXDPUV1_MODE_FLAGS_BT656_10BIT = 1 << 17, + IMXDPUV1_MODE_FLAGS_BT656_8BIT = 1 << 18, +}; + +struct imxdpuv1_videomode { + char name[64]; /* may not be needed */ + + uint32_t pixelclock; /* Hz */ + + /* htotal (pixels) = hlen + hfp + hsync + hbp */ + uint32_t hlen; + uint32_t hfp; + uint32_t hbp; + uint32_t hsync; + + /* field0 - vtotal (lines) = vlen + vfp + vsync + vbp */ + uint32_t vlen; + uint32_t vfp; + uint32_t vbp; + uint32_t vsync; + + /* field1 */ + uint32_t vlen1; + uint32_t vfp1; + uint32_t vbp1; + uint32_t vsync1; + + uint32_t flags; + uint32_t format; + uint32_t dest_format; /*buffer format for capture*/ + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + +}; + +#define IMXDPUV1_ENABLE 1 +#define IMXDPUV1_DISABLE 0 + +#define IMXDPUV1_TRUE 1 +#define IMXDPUV1_FALSE 0 +#define IMXDPUV1_OFFSET_INVALID 0x10000000 /* this should force an access error */ +#define IMXDPUV1_CHANNEL_INVALID 0x0 /* this should force an access error */ + +#define IMXDPUV1_MIN(_X, _Y) ((_X) < (_Y) ? (_X) : (_Y)) + +/* Native color type */ +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +#define IMXDPUV1_IRQF_NONE 0x0 +#define IMXDPUV1_IRQF_ONESHOT 0x1 +#define IMXDPUV1_INTERRUPT_MAX (66 + 1) /* IMXDPUV1_FRAMECAP5_SYNC_OFF_IRQ + (66) is last interrupt */ + +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id); +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_init_irqs(int8_t imxdpuv1_id); +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int(*handler) (int, void *), + uint32_t irq_flags, + const char *devname, void *data) ; +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data); +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id); +int imxdpuv1_handle_irq(int32_t imxdpuv1_id); +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id); +int imxdpuv1_init(int8_t imxdpuv1_id); +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, int8_t disp, + uint32_t pixel_fmt, + struct imxdpuv1_videomode mode); +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable); +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, + int8_t disp, + bool enable); +int imxdpuv1_disp_setup_constframe(int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha); +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer); +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode); +int imxdpuv1_bytes_per_pixel(uint32_t fmt); +int imxdpuv1_init_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset); +int32_t imxdpuv1_update_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0); +int imxdpuv1_init_channel(int8_t imxdpuv1_id, + imxdpuv1_channel_params_t *params); +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha); +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y); +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t x, int16_t y); +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id); +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id); +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id); +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask); +int imxdpuv1_disp_set_chan_crop(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +uint32_t imxdpuv1_get_planes(uint32_t fmt); + +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr); +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp); + +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode); +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height); + +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable); +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask); + +/* FIXME: add api if needed */ +static inline int32_t imxdpuv1_csi_enable_mclk_if(int8_t imxdpuv1_id, int src, uint32_t cap, + bool flag, bool wait) +{ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + return 0; +} +#endif /* IMXDPUV1_H */ diff --git a/include/imxdpuv1_events.h b/include/imxdpuv1_events.h new file mode 100644 index 0000000000..7f8ed8157d --- /dev/null +++ b/include/imxdpuv1_events.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_EVENTS_H +#define IMXDPUV1_EVENTS_H + +/* Shadow load (Blit Engine) */ +#define IMXDPUV1_STORE9_SHDLOAD_IRQ 0U +#define IMXDPUV1_STORE9_SHDLOAD_CMD 0U + +/* Frame complete (Blit Engine) */ +#define IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ 1U +#define IMXDPUV1_STORE9_FRAMECOMPLETE_CMD 1U + +/* Sequence complete (Blit Engine) */ +#define IMXDPUV1_STORE9_SEQCOMPLETE_IRQ 2U +#define IMXDPUV1_STORE9_SEQCOMPLETE_CMD 2U + +/* Shadow load (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SHDLOAD_IRQ 3U +#define IMXDPUV1_EXTDST0_SHDLOAD_CMD 3U + +/* Frame complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ 4U +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_CMD 4U + +/* Sequence complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_IRQ 5U +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_CMD 5U + +/* Shadow load (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SHDLOAD_IRQ 6U +#define IMXDPUV1_EXTDST4_SHDLOAD_CMD 6U + +/* Frame complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_IRQ 7U +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_CMD 7U + +/* Sequence complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_IRQ 8U +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_CMD 8U + +/* Shadow load (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SHDLOAD_IRQ 9U +#define IMXDPUV1_EXTDST1_SHDLOAD_CMD 9U + +/* Frame complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ 10U +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_CMD 10U + +/* Sequence complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_IRQ 11U +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_CMD 11U + +/* Shadow load (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SHDLOAD_IRQ 12U +#define IMXDPUV1_EXTDST5_SHDLOAD_CMD 12U + +/* Frame complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_IRQ 13U +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_CMD 13U + +/* Sequence complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_IRQ 14U +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_CMD 14U + +/* Shadow load (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ 15U +#define IMXDPUV1_DISENGCFG_SHDLOAD0_CMD 15U + +/* Frame complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ 16U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_CMD 16U + +/* Sequence complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_IRQ 17U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_CMD 17U + +/* Programmable interrupt 0 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT0_IRQ 18U +#define IMXDPUV1_FRAMEGEN0_INT0_CMD 18U + +/* Programmable interrupt 1 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT1_IRQ 19U +#define IMXDPUV1_FRAMEGEN0_INT1_CMD 19U + +/* Programmable interrupt 2 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT2_IRQ 20U +#define IMXDPUV1_FRAMEGEN0_INT2_CMD 20U + +/* Programmable interrupt 3 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT3_IRQ 21U +#define IMXDPUV1_FRAMEGEN0_INT3_CMD 21U + +/* Shadow load (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_SHDLOAD_IRQ 22U +#define IMXDPUV1_SIG0_SHDLOAD_CMD 22U + +/* Measurement valid (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_VALID_IRQ 23U +#define IMXDPUV1_SIG0_VALID_CMD 23U + +/* Error condition (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_ERROR_IRQ 24U +#define IMXDPUV1_SIG0_ERROR_CMD 24U + +/* Shadow load (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ 25U +#define IMXDPUV1_DISENGCFG_SHDLOAD1_CMD 25U + +/* Frame complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_IRQ 26U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_CMD 26U + +/* Sequence complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_IRQ 27U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_CMD 27U + +/* Programmable interrupt 0 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT0_IRQ 28U +#define IMXDPUV1_FRAMEGEN1_INT0_CMD 28U + +/* Programmable interrupt 1 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT1_IRQ 29U +#define IMXDPUV1_FRAMEGEN1_INT1_CMD 29U + +/* Programmable interrupt 2 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT2_IRQ 30U +#define IMXDPUV1_FRAMEGEN1_INT2_CMD 30U + +/* Programmable interrupt 3 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT3_IRQ 31U +#define IMXDPUV1_FRAMEGEN1_INT3_CMD 31U + +/* Shadow load (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_SHDLOAD_IRQ 32U +#define IMXDPUV1_SIG1_SHDLOAD_CMD 32U + +/* Measurement valid (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_VALID_IRQ 33U +#define IMXDPUV1_SIG1_VALID_CMD 33U + +/* Error condition (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_ERROR_IRQ 34U +#define IMXDPUV1_SIG1_ERROR_CMD 34U + +/* Reserved Do not use */ +#define IMXDPUV1_RESERVED35_IRQ 35U +#define IMXDPUV1_RESERVED35_CMD 35U + +/* Error condition (Command Sequencer) */ +#define IMXDPUV1_CMDSEQ_ERROR_IRQ 36U +#define IMXDPUV1_CMDSEQ_ERROR_CMD 36U + +/* Software interrupt 0 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW0_IRQ 37U +#define IMXDPUV1_COMCTRL_SW0_CMD 37U + +/* Software interrupt 1 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW1_IRQ 38U +#define IMXDPUV1_COMCTRL_SW1_CMD 38U + +/* Software interrupt 2 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW2_IRQ 39U +#define IMXDPUV1_COMCTRL_SW2_CMD 39U + +/* Software interrupt 3 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW3_IRQ 40U +#define IMXDPUV1_COMCTRL_SW3_CMD 40U + +/* Synchronization status activated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_IRQ 41U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_CMD 41U + +/* Synchronization status deactivated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_IRQ 42U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_CMD 42U + +/* Synchronization status activated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_IRQ 43U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_CMD 43U + +/* Synchronization status deactivated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_IRQ 44U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_CMD 44U + +/* Synchronization status activated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_IRQ 45U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_CMD 45U + +/* Synchronization status deactivated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_IRQ 46U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_CMD 46U + +/* Synchronization status activated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_IRQ 47U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_CMD 47U + +/* Synchronization status deactivated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_IRQ 48U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_CMD 48U + +/* Synchronization status (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_CMD 49U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_STS 0U + +/* Synchronization status (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_CMD 50U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_STS 1U + +/* Synchronization status (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_CMD 51U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_STS 2U + +/* Synchronization status (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_CMD 52U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_STS 3U + +/* Shadow load request (Display Controller Pixel Engine configuration Store #9 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_STORE9_SHDLDREQ_CMD 53U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #0 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SHDLDREQ_CMD 54U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #4 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SHDLDREQ_CMD 55U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #1 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SHDLDREQ_CMD 56U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #5 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SHDLDREQ_CMD 57U + +/* Shadow load request (Blit Engine FetchDecode #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_SHDLDREQ_CMD 58U + +/* Shadow load request (Blit Engine FetchWarp #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_SHDLDREQ_CMD 59U + +/* Shadow load request (Blit Engine FetchEco #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_SHDLDREQ_CMD 60U + +/* Shadow load request (Display Controller ConstFrame #0 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_SHDLDREQ_CMD 61U + +/* Shadow load request (Display Controller ConstFrame #4 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_SHDLDREQ_CMD 62U + +/* Shadow load request (Display Controller ConstFrame #1 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_SHDLDREQ_CMD 63U + +/* Shadow load request (Display Controller ConstFrame #5 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_SHDLDREQ_CMD 64U + +/* Shadow load request (Display Controller FetchWarp #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_SHDLDREQ_CMD 65U + +/* Shadow load request (Display Controller FetchEco #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_SHDLDREQ_CMD 66U + +/* Shadow load request (Display Controller FetchDecode #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_SHDLDREQ_CMD 67U + +/* Shadow load request (Display Controller FetchEco #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_SHDLDREQ_CMD 68U + +/* Shadow load request (Display Controller FetchDecode #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_SHDLDREQ_CMD 69U + +/* Shadow load request (Display Controller FetchEco #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_SHDLDREQ_CMD 70U + +/* Shadow load request (Display Controller FetchLayer #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_SHDLDREQ_CMD 71U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ0_CMD 72U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ1_CMD 73U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ2_CMD 74U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ3_CMD 75U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ4_CMD 76U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ5_CMD 77U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ6_CMD 78U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ7_CMD 79U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ0_CMD 80U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ1_CMD 81U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ2_CMD 82U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ3_CMD 83U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ4_CMD 84U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ5_CMD 85U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ6_CMD 86U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ7_CMD 87U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 0) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ0_CMD 88U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 1) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ1_CMD 89U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 2) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ2_CMD 90U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 3) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ3_CMD 91U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 4) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ4_CMD 92U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 5) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ5_CMD 93U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 6) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ6_CMD 94U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 7) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ7_CMD 95U + + +#endif /* IMXDPUV1_EVENTS */ diff --git a/include/imxdpuv1_registers.h b/include/imxdpuv1_registers.h new file mode 100644 index 0000000000..eb9676b0bb --- /dev/null +++ b/include/imxdpuv1_registers.h @@ -0,0 +1,22682 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* Instance: IMXDPU */ + +#ifndef IMXDPUV1_REGISTERS_H +#define IMXDPUV1_REGISTERS_H +/* Register: IMXDPUV1_comctrl_IPIdentifier */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_VALUE 0x21340400U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_MASK 0xF0U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_SHIFT 4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_MASK 0xF00U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_SHIFT 8U +/* Field Value: DESIGNMATURITYLEVEL__PREFS, Pre feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__PREFS 0x1U +/* Field Value: DESIGNMATURITYLEVEL__FS, Feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__FS 0x2U +/* Field Value: DESIGNMATURITYLEVEL__R0, Functionality complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R0 0x3U +/* Field Value: DESIGNMATURITYLEVEL__R1, Verification complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R1 0x4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_MASK 0xF000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_SHIFT 12U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_MASK 0xF0000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_SHIFT 16U +/* Field Value: IPFEATURESET__E, Minimal functionality (Eco). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__E 0x1U +/* Field Value: IPFEATURESET__L, Reduced functionality (Light). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__L 0x2U +/* Field Value: IPFEATURESET__P, Advanced functionality (Plus). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__P 0x4U +/* Field Value: IPFEATURESET__X, Extensive functionality (eXtensive). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__X 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_MASK 0xF00000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_SHIFT 20U +/* Field Value: IPAPPLICATION__B, Blit Engine only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__B 0x1U +/* Field Value: IPAPPLICATION__D, Blit Engine and Display Controller. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__D 0x2U +/* Field Value: IPAPPLICATION__V, Display Controller only (with direct capture). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__V 0x3U +/* Field Value: IPAPPLICATION__G, Blit Engine, Display Controller (with direct + * capture), Capture Controller (buffered capture) and Drawing Engine. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__G 0x4U +/* Field Value: IPAPPLICATION__C, Display Controller only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__C 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_MASK 0xF000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_SHIFT 24U +/* Field Value: IPCONFIGURATION__M, Graphics core only (Module). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__M 0x1U +/* Field Value: IPCONFIGURATION__S, Subsystem including a graphics core (System). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__S 0x2U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_MASK 0xF0000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_SHIFT 28U +/* Field Value: IPFAMILY__IMXDPU2010, IMXDPU building block generation 2010. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2010 0U +/* Field Value: IPFAMILY__IMXDPU2012, IMXDPU building block generation 2012. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2012 0x1U +/* Field Value: IPFAMILY__IMXDPU2013, IMXDPU building block generation 2013. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2013 0x2U + +/* Register: IMXDPUV1_comctrl_LockUnlock */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_comctrl_LockStatus */ +#define IMXDPUV1_COMCTRL_LOCKSTATUS ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1 ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0 ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1 ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0 ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1 ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0 ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1 ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1 ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1 ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0 ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1 ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0 ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1 ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1 ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_GeneralPurpose */ +#define IMXDPUV1_COMCTRL_GENERALPURPOSE ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_HIF */ +#define IMXDPUV1_CMDSEQ_HIF ((uint32_t)(0x400)) +#define IMXDPUV1_CMDSEQ_HIF_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CMDSEQ_HIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_HIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_LockUnlockHIF */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF ((uint32_t)(0x500)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_SHIFT 0U +/* Field Value: LOCKUNLOCKHIF__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCKHIF__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCKHIF__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCKHIF__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCKHIF__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatusHIF */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF ((uint32_t)(0x504)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_LockUnlock */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK ((uint32_t)(0x580)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatus */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUS ((uint32_t)(0x584)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_BufferAddress */ +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS ((uint32_t)(0x588)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_MASK 0x1U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_SHIFT 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_MASK 0xFFFFFFE0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_SHIFT 5U + +/* Register: IMXDPUV1_cmdseq_BufferSize */ +#define IMXDPUV1_CMDSEQ_BUFFERSIZE ((uint32_t)(0x58C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_VALUE 0x80U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_SHIFT 3U + +/* Register: IMXDPUV1_cmdseq_WatermarkControl */ +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL ((uint32_t)(0x590)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_VALUE 0x600020U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_MASK 0xFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_SHIFT 0U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_MASK 0xFFFF0000U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_SHIFT 16U + +/* Register: IMXDPUV1_cmdseq_Control */ +#define IMXDPUV1_CMDSEQ_CONTROL ((uint32_t)(0x594)) +#define IMXDPUV1_CMDSEQ_CONTROL_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_MASK 0x1U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_SHIFT 0U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_MASK 0x4U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_SHIFT 2U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_MASK 0x8U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_SHIFT 3U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_Status */ +#define IMXDPUV1_CMDSEQ_STATUS ((uint32_t)(0x598)) +#define IMXDPUV1_CMDSEQ_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_CMDSEQ_STATUS_RESET_VALUE 0x41000080U +#define IMXDPUV1_CMDSEQ_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_MASK 0x1FFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_SHIFT 0U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_MASK 0x1000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_SHIFT 24U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_MASK 0x2000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_SHIFT 25U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_MASK 0x4000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_SHIFT 26U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_MASK 0x8000000U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_SHIFT 27U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_MASK 0x10000000U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_SHIFT 28U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_MASK 0x20000000U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_SHIFT 29U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_MASK 0x40000000U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_SHIFT 30U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowStart */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART ((uint32_t)(0x59C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_OFFSET ((uint32_t)(0x19C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_SHIFT 2U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowEnd */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND ((uint32_t)(0x5A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_VALUE 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_SHIFT 2U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockUnlock */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK ((uint32_t)(0x800)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_SHIFT 0U +/* Field Value: SAFETYLOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: SAFETYLOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: SAFETYLOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: SAFETYLOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockStatus */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS ((uint32_t)(0x804)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK ((uint32_t)(0x808)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK ((uint32_t)(0x80C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK ((uint32_t)(0x810)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_SafetyMask_0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0 ((uint32_t)(0x814)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK ((uint32_t)(0x818)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x820)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x824)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC ((uint32_t)(0x828)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE9_SRC_SEL__DISABLE, Unit fetchdecode9 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHECO9, Unit fetchdecode9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHECO9 0x3U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHPERSP9, Unit fetchdecode9 input + * port src is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS ((uint32_t)(0x82C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_SHIFT 16U +/* Field Value: FETCHDECODE9_SEL__STORE9, fetchdecode9 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE9_SEL__EXTDST0, fetchdecode9 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE9_SEL__EXTDST4, fetchdecode9 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE9_SEL__EXTDST1, fetchdecode9 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE9_SEL__EXTDST5, fetchdecode9 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE9_SEL__STORE4, fetchdecode9 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE9_SEL__STORE5, fetchdecode9 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE9_SEL__DISABLE, fetchdecode9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x840)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x844)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC ((uint32_t)(0x848)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP9_SRC_SEL__DISABLE, Unit fetchpersp9 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP9_SRC_SEL__FETCHECO9, Unit fetchpersp9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__FETCHECO9 0x3U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS ((uint32_t)(0x84C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_SHIFT 16U +/* Field Value: FETCHWARP9_SEL__STORE9, fetchpersp9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE9 0x1U +/* Field Value: FETCHWARP9_SEL__EXTDST0, fetchpersp9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP9_SEL__EXTDST4, fetchpersp9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP9_SEL__EXTDST1, fetchpersp9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP9_SEL__EXTDST5, fetchpersp9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP9_SEL__STORE4, fetchpersp9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE4 0x6U +/* Field Value: FETCHWARP9_SEL__STORE5, fetchpersp9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE5 0x7U +/* Field Value: FETCHWARP9_SEL__DISABLE, fetchpersp9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x850)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS ((uint32_t)(0x854)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS ((uint32_t)(0x858)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_SHIFT 16U +/* Field Value: FETCHECO9_SEL__STORE9, fetcheco9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE9 0x1U +/* Field Value: FETCHECO9_SEL__EXTDST0, fetcheco9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO9_SEL__EXTDST4, fetcheco9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO9_SEL__EXTDST1, fetcheco9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO9_SEL__EXTDST5, fetcheco9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO9_SEL__STORE4, fetcheco9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE4 0x6U +/* Field Value: FETCHECO9_SEL__STORE5, fetcheco9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE5 0x7U +/* Field Value: FETCHECO9_SEL__DISABLE, fetcheco9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK ((uint32_t)(0x860)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: ROP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: ROP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: ROP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: ROP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS ((uint32_t)(0x864)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_rop9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC ((uint32_t)(0x868)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_SHIFT 0U +/* Field Value: ROP9_PRIM_SEL__DISABLE, Unit rop9 input port prim is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__DISABLE 0U +/* Field Value: ROP9_PRIM_SEL__FETCHDECODE9, Unit rop9 input port prim is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_PRIM_SEL__FETCHPERSP9, Unit rop9 input port prim is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_SHIFT 8U +/* Field Value: ROP9_SEC_SEL__DISABLE, Unit rop9 input port sec is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__DISABLE 0U +/* Field Value: ROP9_SEC_SEL__FETCHECO9, Unit rop9 input port sec is connected + * to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__FETCHECO9 0x3U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_MASK 0x3F0000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_SHIFT 16U +/* Field Value: ROP9_TERT_SEL__DISABLE, Unit rop9 input port tert is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__DISABLE 0U +/* Field Value: ROP9_TERT_SEL__FETCHDECODE9, Unit rop9 input port tert is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_TERT_SEL__FETCHPERSP9, Unit rop9 input port tert is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_SHIFT 24U +/* Field Value: ROP9_CLKEN__DISABLE, Clock for rop9 is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__DISABLE 0U +/* Field Value: ROP9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, frequency + * is defined by the register setting for this pipeline (see [endpoint_name]_Static + * register) */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__AUTOMATIC 0x1U +/* Field Value: ROP9_CLKEN__FULL, Clock for rop9 is without gating */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_rop9_Status */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS ((uint32_t)(0x86C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_SHIFT 16U +/* Field Value: ROP9_SEL__STORE9, rop9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE9 0x1U +/* Field Value: ROP9_SEL__EXTDST0, rop9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST0 0x2U +/* Field Value: ROP9_SEL__EXTDST4, rop9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST4 0x3U +/* Field Value: ROP9_SEL__EXTDST1, rop9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST1 0x4U +/* Field Value: ROP9_SEL__EXTDST5, rop9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST5 0x5U +/* Field Value: ROP9_SEL__STORE4, rop9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE4 0x6U +/* Field Value: ROP9_SEL__STORE5, rop9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE5 0x7U +/* Field Value: ROP9_SEL__DISABLE, rop9 module is not used */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK ((uint32_t)(0x880)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_SHIFT 0U +/* Field Value: CLUT9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CLUT9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CLUT9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CLUT9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS ((uint32_t)(0x884)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_clut9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC ((uint32_t)(0x888)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_SHIFT 0U +/* Field Value: CLUT9_SRC_SEL__DISABLE, Unit clut9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__DISABLE 0U +/* Field Value: CLUT9_SRC_SEL__BLITBLEND9, Unit clut9 input port src is connected + * to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: CLUT9_SRC_SEL__ROP9, Unit clut9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__ROP9 0x4U + +/* Register: IMXDPUV1_pixengcfg_clut9_Status */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS ((uint32_t)(0x88C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_SHIFT 16U +/* Field Value: CLUT9_SEL__STORE9, clut9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE9 0x1U +/* Field Value: CLUT9_SEL__EXTDST0, clut9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST0 0x2U +/* Field Value: CLUT9_SEL__EXTDST4, clut9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST4 0x3U +/* Field Value: CLUT9_SEL__EXTDST1, clut9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST1 0x4U +/* Field Value: CLUT9_SEL__EXTDST5, clut9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST5 0x5U +/* Field Value: CLUT9_SEL__STORE4, clut9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE4 0x6U +/* Field Value: CLUT9_SEL__STORE5, clut9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE5 0x7U +/* Field Value: CLUT9_SEL__DISABLE, clut9 module is not used */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK ((uint32_t)(0x8A0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS ((uint32_t)(0x8A4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC ((uint32_t)(0x8A8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX9_SRC_SEL__DISABLE, Unit matrix9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX9_SRC_SEL__CLUT9, Unit matrix9 input port src is connected + * to output of unit clut9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__CLUT9 0x5U +/* Field Value: MATRIX9_SRC_SEL__BLITBLEND9, Unit matrix9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: MATRIX9_SRC_SEL__ROP9, Unit matrix9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_SHIFT 24U +/* Field Value: MATRIX9_CLKEN__DISABLE, Clock for matrix9 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__DISABLE 0U +/* Field Value: MATRIX9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX9_CLKEN__FULL, Clock for matrix9 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS ((uint32_t)(0x8AC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_SHIFT 16U +/* Field Value: MATRIX9_SEL__STORE9, matrix9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE9 0x1U +/* Field Value: MATRIX9_SEL__EXTDST0, matrix9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST0 0x2U +/* Field Value: MATRIX9_SEL__EXTDST4, matrix9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST4 0x3U +/* Field Value: MATRIX9_SEL__EXTDST1, matrix9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST1 0x4U +/* Field Value: MATRIX9_SEL__EXTDST5, matrix9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST5 0x5U +/* Field Value: MATRIX9_SEL__STORE4, matrix9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE4 0x6U +/* Field Value: MATRIX9_SEL__STORE5, matrix9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE5 0x7U +/* Field Value: MATRIX9_SEL__DISABLE, matrix9 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK ((uint32_t)(0x8C0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS ((uint32_t)(0x8C4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC ((uint32_t)(0x8C8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER9_SRC_SEL__DISABLE, Unit hscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER9_SRC_SEL__VSCALER9, Unit hscaler9 input port src is + * connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__VSCALER9 0x8U +/* Field Value: HSCALER9_SRC_SEL__FILTER9, Unit hscaler9 input port src is + * connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__FILTER9 0x9U +/* Field Value: HSCALER9_SRC_SEL__MATRIX9, Unit hscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_SHIFT 24U +/* Field Value: HSCALER9_CLKEN__DISABLE, Clock for hscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__DISABLE 0U +/* Field Value: HSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER9_CLKEN__FULL, Clock for hscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS ((uint32_t)(0x8CC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_SHIFT 16U +/* Field Value: HSCALER9_SEL__STORE9, hscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE9 0x1U +/* Field Value: HSCALER9_SEL__EXTDST0, hscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST0 0x2U +/* Field Value: HSCALER9_SEL__EXTDST4, hscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST4 0x3U +/* Field Value: HSCALER9_SEL__EXTDST1, hscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST1 0x4U +/* Field Value: HSCALER9_SEL__EXTDST5, hscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST5 0x5U +/* Field Value: HSCALER9_SEL__STORE4, hscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE4 0x6U +/* Field Value: HSCALER9_SEL__STORE5, hscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE5 0x7U +/* Field Value: HSCALER9_SEL__DISABLE, hscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK ((uint32_t)(0x8E0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS ((uint32_t)(0x8E4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC ((uint32_t)(0x8E8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER9_SRC_SEL__DISABLE, Unit vscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER9_SRC_SEL__HSCALER9, Unit vscaler9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: VSCALER9_SRC_SEL__MATRIX9, Unit vscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_SHIFT 24U +/* Field Value: VSCALER9_CLKEN__DISABLE, Clock for vscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__DISABLE 0U +/* Field Value: VSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER9_CLKEN__FULL, Clock for vscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS ((uint32_t)(0x8EC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_SHIFT 16U +/* Field Value: VSCALER9_SEL__STORE9, vscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE9 0x1U +/* Field Value: VSCALER9_SEL__EXTDST0, vscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST0 0x2U +/* Field Value: VSCALER9_SEL__EXTDST4, vscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST4 0x3U +/* Field Value: VSCALER9_SEL__EXTDST1, vscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST1 0x4U +/* Field Value: VSCALER9_SEL__EXTDST5, vscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST5 0x5U +/* Field Value: VSCALER9_SEL__STORE4, vscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE4 0x6U +/* Field Value: VSCALER9_SEL__STORE5, vscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE5 0x7U +/* Field Value: VSCALER9_SEL__DISABLE, vscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK ((uint32_t)(0x900)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FILTER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FILTER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FILTER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FILTER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS ((uint32_t)(0x904)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_filter9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC ((uint32_t)(0x908)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_SHIFT 0U +/* Field Value: FILTER9_SRC_SEL__DISABLE, Unit filter9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__DISABLE 0U +/* Field Value: FILTER9_SRC_SEL__HSCALER9, Unit filter9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: FILTER9_SRC_SEL__MATRIX9, Unit filter9 input port src is connected + * to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_SHIFT 24U +/* Field Value: FILTER9_CLKEN__DISABLE, Clock for filter9 is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__DISABLE 0U +/* Field Value: FILTER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: FILTER9_CLKEN__FULL, Clock for filter9 is without gating */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_filter9_Status */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS ((uint32_t)(0x90C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_SHIFT 16U +/* Field Value: FILTER9_SEL__STORE9, filter9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE9 0x1U +/* Field Value: FILTER9_SEL__EXTDST0, filter9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST0 0x2U +/* Field Value: FILTER9_SEL__EXTDST4, filter9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST4 0x3U +/* Field Value: FILTER9_SEL__EXTDST1, filter9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST1 0x4U +/* Field Value: FILTER9_SEL__EXTDST5, filter9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST5 0x5U +/* Field Value: FILTER9_SEL__STORE4, filter9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE4 0x6U +/* Field Value: FILTER9_SEL__STORE5, filter9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE5 0x7U +/* Field Value: FILTER9_SEL__DISABLE, filter9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x920)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_SHIFT 0U +/* Field Value: BLITBLEND9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: BLITBLEND9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x924)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC ((uint32_t)(0x928)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_SHIFT 0U +/* Field Value: BLITBLEND9_PRIM_SEL__DISABLE, Unit blitblend9 input port prim + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_PRIM_SEL__HSCALER9, Unit blitblend9 input port + * prim is connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__HSCALER9 0x7U +/* Field Value: BLITBLEND9_PRIM_SEL__VSCALER9, Unit blitblend9 input port + * prim is connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__VSCALER9 0x8U +/* Field Value: BLITBLEND9_PRIM_SEL__FILTER9, Unit blitblend9 input port prim + * is connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__FILTER9 0x9U +/* Field Value: BLITBLEND9_PRIM_SEL__ROP9, Unit blitblend9 input port prim + * is connected to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_SHIFT 8U +/* Field Value: BLITBLEND9_SEC_SEL__DISABLE, Unit blitblend9 input port sec + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHDECODE9, Unit blitblend9 input port + * sec is connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHDECODE9 0x1U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHPERSP9, Unit blitblend9 input port + * sec is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_SHIFT 24U +/* Field Value: BLITBLEND9_CLKEN__DISABLE, Clock for blitblend9 is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__DISABLE 0U +/* Field Value: BLITBLEND9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__AUTOMATIC 0x1U +/* Field Value: BLITBLEND9_CLKEN__FULL, Clock for blitblend9 is without gating */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Status */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS ((uint32_t)(0x92C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_SHIFT 16U +/* Field Value: BLITBLEND9_SEL__STORE9, blitblend9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE9 0x1U +/* Field Value: BLITBLEND9_SEL__EXTDST0, blitblend9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST0 0x2U +/* Field Value: BLITBLEND9_SEL__EXTDST4, blitblend9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST4 0x3U +/* Field Value: BLITBLEND9_SEL__EXTDST1, blitblend9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST1 0x4U +/* Field Value: BLITBLEND9_SEL__EXTDST5, blitblend9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST5 0x5U +/* Field Value: BLITBLEND9_SEL__STORE4, blitblend9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE4 0x6U +/* Field Value: BLITBLEND9_SEL__STORE5, blitblend9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE5 0x7U +/* Field Value: BLITBLEND9_SEL__DISABLE, blitblend9 module is not used */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_store9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK ((uint32_t)(0x940)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: STORE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: STORE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: STORE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: STORE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_store9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS ((uint32_t)(0x944)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_Static */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC ((uint32_t)(0x948)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U +/* Field Value: STORE9_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U +/* Field Value: STORE9_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U +/* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U +/* Field Value: STORE9_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_store9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC ((uint32_t)(0x94C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_VALUE 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_SHIFT 0U +/* Field Value: STORE9_SRC_SEL__DISABLE, Unit store9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__DISABLE 0U +/* Field Value: STORE9_SRC_SEL__HSCALER9, Unit store9 input port src is connected + * to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__HSCALER9 0x7U +/* Field Value: STORE9_SRC_SEL__VSCALER9, Unit store9 input port src is connected + * to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__VSCALER9 0x8U +/* Field Value: STORE9_SRC_SEL__FILTER9, Unit store9 input port src is connected + * to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FILTER9 0x9U +/* Field Value: STORE9_SRC_SEL__BLITBLEND9, Unit store9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: STORE9_SRC_SEL__FETCHDECODE9, Unit store9 input port src is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHDECODE9 0x1U +/* Field Value: STORE9_SRC_SEL__FETCHPERSP9, Unit store9 input port src is + * connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_store9_Request */ +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST ((uint32_t)(0x950)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_store9_Trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER ((uint32_t)(0x954)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_store9_Status */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS ((uint32_t)(0x958)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_SHIFT 0U +/* Field Value: STORE9_PIPELINE_STATUS__EMPTY, Pipeline with endpoint store9 + * is empty */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__EMPTY 0U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING, Pipeline with endpoint store9 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint store9 is currently processing one operation with a second one + * already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: STORE9_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_SHIFT 8U +/* Field Value: STORE9_SYNC_BUSY__IDLE, store9 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__IDLE 0U +/* Field Value: STORE9_SYNC_BUSY__BUSY, store9 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x960)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x964)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe0_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS ((uint32_t)(0x968)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_SHIFT 16U +/* Field Value: CONSTFRAME0_SEL__STORE9, constframe0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME0_SEL__EXTDST0, constframe0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME0_SEL__EXTDST4, constframe0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME0_SEL__EXTDST1, constframe0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME0_SEL__EXTDST5, constframe0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME0_SEL__STORE4, constframe0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME0_SEL__STORE5, constframe0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME0_SEL__DISABLE, constframe0 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK ((uint32_t)(0x980)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS ((uint32_t)(0x984)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC ((uint32_t)(0x988)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST0_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST0_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_SHIFT 11U +/* Field Value: EXTDST0_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION 0U +/* Field Value: EXTDST0_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC ((uint32_t)(0x98C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_VALUE 0x2CU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST0_SRC_SEL__DISABLE, Unit extdst0 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST0_SRC_SEL__BLITBLEND9, Unit extdst0 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME0, Unit extdst0 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME1, Unit extdst0 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME4, Unit extdst0 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME5, Unit extdst0 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST0_SRC_SEL__MATRIX4, Unit extdst0 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST0_SRC_SEL__HSCALER4, Unit extdst0 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST0_SRC_SEL__VSCALER4, Unit extdst0 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST0_SRC_SEL__EXTSRC4, Unit extdst0 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST0_SRC_SEL__MATRIX5, Unit extdst0 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST0_SRC_SEL__HSCALER5, Unit extdst0 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST0_SRC_SEL__VSCALER5, Unit extdst0 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST0_SRC_SEL__EXTSRC5, Unit extdst0 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND6, Unit extdst0 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND5, Unit extdst0 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND4, Unit extdst0 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND3, Unit extdst0 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND2, Unit extdst0 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND1, Unit extdst0 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND0, Unit extdst0 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst0_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST ((uint32_t)(0x990)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER ((uint32_t)(0x994)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS ((uint32_t)(0x998)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst0 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst0 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst0 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST0_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST0_SYNC_BUSY__IDLE, extdst0 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST0_SYNC_BUSY__BUSY, extdst0 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x9A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x9A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x1A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe4_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS ((uint32_t)(0x9A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_SHIFT 16U +/* Field Value: CONSTFRAME4_SEL__STORE9, constframe4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME4_SEL__EXTDST0, constframe4 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME4_SEL__EXTDST4, constframe4 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME4_SEL__EXTDST1, constframe4 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME4_SEL__EXTDST5, constframe4 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME4_SEL__STORE4, constframe4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME4_SEL__STORE5, constframe4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME4_SEL__DISABLE, constframe4 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK ((uint32_t)(0x9C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS ((uint32_t)(0x9C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x1C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC ((uint32_t)(0x9C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET ((uint32_t)(0x1C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST4_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST4_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_SHIFT 11U +/* Field Value: EXTDST4_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__OPERATION 0U +/* Field Value: EXTDST4_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC ((uint32_t)(0x9CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_OFFSET ((uint32_t)(0x1CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_VALUE 0x30U +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST4_SRC_SEL__DISABLE, Unit extdst4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST4_SRC_SEL__BLITBLEND9, Unit extdst4 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME0, Unit extdst4 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME1, Unit extdst4 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME4, Unit extdst4 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME5, Unit extdst4 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST4_SRC_SEL__MATRIX4, Unit extdst4 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST4_SRC_SEL__HSCALER4, Unit extdst4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST4_SRC_SEL__VSCALER4, Unit extdst4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST4_SRC_SEL__MATRIX5, Unit extdst4 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST4_SRC_SEL__HSCALER5, Unit extdst4 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST4_SRC_SEL__VSCALER5, Unit extdst4 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND6, Unit extdst4 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND5, Unit extdst4 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND4, Unit extdst4 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND3, Unit extdst4 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND2, Unit extdst4 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND1, Unit extdst4 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND0, Unit extdst4 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst4_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST ((uint32_t)(0x9D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_OFFSET ((uint32_t)(0x1D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER ((uint32_t)(0x9D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_OFFSET ((uint32_t)(0x1D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS ((uint32_t)(0x9D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_OFFSET ((uint32_t)(0x1D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst4 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst4 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst4 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST4_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST4_SYNC_BUSY__IDLE, extdst4 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST4_SYNC_BUSY__BUSY, extdst4 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x9E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0x1E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x9E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x1E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe1_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS ((uint32_t)(0x9E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_SHIFT 16U +/* Field Value: CONSTFRAME1_SEL__STORE9, constframe1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME1_SEL__EXTDST0, constframe1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME1_SEL__EXTDST4, constframe1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME1_SEL__EXTDST1, constframe1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME1_SEL__EXTDST5, constframe1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME1_SEL__STORE4, constframe1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME1_SEL__STORE5, constframe1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME1_SEL__DISABLE, constframe1 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK ((uint32_t)(0xA00)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0x200)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS ((uint32_t)(0xA04)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x204)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC ((uint32_t)(0xA08)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_OFFSET ((uint32_t)(0x208)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST1_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST1_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_SHIFT 11U +/* Field Value: EXTDST1_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION 0U +/* Field Value: EXTDST1_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC ((uint32_t)(0xA0C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_OFFSET ((uint32_t)(0x20C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_VALUE 0x2DU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST1_SRC_SEL__DISABLE, Unit extdst1 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST1_SRC_SEL__BLITBLEND9, Unit extdst1 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME0, Unit extdst1 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME1, Unit extdst1 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME4, Unit extdst1 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME5, Unit extdst1 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST1_SRC_SEL__MATRIX4, Unit extdst1 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST1_SRC_SEL__HSCALER4, Unit extdst1 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST1_SRC_SEL__VSCALER4, Unit extdst1 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST1_SRC_SEL__EXTSRC4, Unit extdst1 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST1_SRC_SEL__MATRIX5, Unit extdst1 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST1_SRC_SEL__HSCALER5, Unit extdst1 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST1_SRC_SEL__VSCALER5, Unit extdst1 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST1_SRC_SEL__EXTSRC5, Unit extdst1 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND6, Unit extdst1 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND5, Unit extdst1 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND4, Unit extdst1 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND3, Unit extdst1 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND2, Unit extdst1 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND1, Unit extdst1 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND0, Unit extdst1 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst1_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST ((uint32_t)(0xA10)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_OFFSET ((uint32_t)(0x210)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER ((uint32_t)(0xA14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_OFFSET ((uint32_t)(0x214)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS ((uint32_t)(0xA18)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_OFFSET ((uint32_t)(0x218)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst1 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst1 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst1 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST1_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST1_SYNC_BUSY__IDLE, extdst1 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST1_SYNC_BUSY__BUSY, extdst1 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0xA20)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0x220)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0xA24)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x224)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe5_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS ((uint32_t)(0xA28)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x228)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_SHIFT 16U +/* Field Value: CONSTFRAME5_SEL__STORE9, constframe5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME5_SEL__EXTDST0, constframe5 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME5_SEL__EXTDST4, constframe5 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME5_SEL__EXTDST1, constframe5 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME5_SEL__EXTDST5, constframe5 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME5_SEL__STORE4, constframe5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME5_SEL__STORE5, constframe5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME5_SEL__DISABLE, constframe5 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK ((uint32_t)(0xA40)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0x240)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS ((uint32_t)(0xA44)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x244)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC ((uint32_t)(0xA48)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET ((uint32_t)(0x248)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST5_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST5_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_SHIFT 11U +/* Field Value: EXTDST5_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__OPERATION 0U +/* Field Value: EXTDST5_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC ((uint32_t)(0xA4C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_OFFSET ((uint32_t)(0x24C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_VALUE 0x31U +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST5_SRC_SEL__DISABLE, Unit extdst5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST5_SRC_SEL__BLITBLEND9, Unit extdst5 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME0, Unit extdst5 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME1, Unit extdst5 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME4, Unit extdst5 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME5, Unit extdst5 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST5_SRC_SEL__MATRIX4, Unit extdst5 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST5_SRC_SEL__HSCALER4, Unit extdst5 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST5_SRC_SEL__VSCALER4, Unit extdst5 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST5_SRC_SEL__MATRIX5, Unit extdst5 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST5_SRC_SEL__HSCALER5, Unit extdst5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST5_SRC_SEL__VSCALER5, Unit extdst5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND6, Unit extdst5 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND5, Unit extdst5 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND4, Unit extdst5 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND3, Unit extdst5 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND2, Unit extdst5 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND1, Unit extdst5 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND0, Unit extdst5 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst5_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST ((uint32_t)(0xA50)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_OFFSET ((uint32_t)(0x250)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER ((uint32_t)(0xA54)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_OFFSET ((uint32_t)(0x254)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS ((uint32_t)(0xA58)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_OFFSET ((uint32_t)(0x258)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst5 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst5 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst5 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST5_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST5_SYNC_BUSY__IDLE, extdst5 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST5_SYNC_BUSY__BUSY, extdst5 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0xA60)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0x260)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS ((uint32_t)(0xA64)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x264)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC ((uint32_t)(0xA68)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_OFFSET ((uint32_t)(0x268)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP2_SRC_SEL__DISABLE, Unit fetchwarp2 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP2_SRC_SEL__FETCHECO2, Unit fetchwarp2 input port + * src is connected to output of unit fetcheco2 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__FETCHECO2 0x1BU + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS ((uint32_t)(0xA6C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x26C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_SHIFT 16U +/* Field Value: FETCHWARP2_SEL__STORE9, fetchwarp2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE9 0x1U +/* Field Value: FETCHWARP2_SEL__EXTDST0, fetchwarp2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP2_SEL__EXTDST4, fetchwarp2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP2_SEL__EXTDST1, fetchwarp2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP2_SEL__EXTDST5, fetchwarp2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP2_SEL__STORE4, fetchwarp2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE4 0x6U +/* Field Value: FETCHWARP2_SEL__STORE5, fetchwarp2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE5 0x7U +/* Field Value: FETCHWARP2_SEL__DISABLE, fetchwarp2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK ((uint32_t)(0xA70)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0x270)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS ((uint32_t)(0xA74)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x274)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS ((uint32_t)(0xA78)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_OFFSET ((uint32_t)(0x278)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_SHIFT 16U +/* Field Value: FETCHECO2_SEL__STORE9, fetcheco2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE9 0x1U +/* Field Value: FETCHECO2_SEL__EXTDST0, fetcheco2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO2_SEL__EXTDST4, fetcheco2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO2_SEL__EXTDST1, fetcheco2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO2_SEL__EXTDST5, fetcheco2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO2_SEL__STORE4, fetcheco2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE4 0x6U +/* Field Value: FETCHECO2_SEL__STORE5, fetcheco2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE5 0x7U +/* Field Value: FETCHECO2_SEL__DISABLE, fetcheco2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0xA80)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0x280)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0xA84)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x284)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC ((uint32_t)(0xA88)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_OFFSET ((uint32_t)(0x288)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE0_SRC_SEL__DISABLE, Unit fetchdecode0 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHECO0, Unit fetchdecode0 input port + * src is connected to output of unit fetcheco0 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0 0x1DU +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHDECODE2, Unit fetchdecode0 input + * port src is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHDECODE2 0x18U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS ((uint32_t)(0xA8C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x28C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_SHIFT 16U +/* Field Value: FETCHDECODE0_SEL__STORE9, fetchdecode0 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE0_SEL__EXTDST0, fetchdecode0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE0_SEL__EXTDST4, fetchdecode0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE0_SEL__EXTDST1, fetchdecode0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE0_SEL__EXTDST5, fetchdecode0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE0_SEL__STORE4, fetchdecode0 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE0_SEL__STORE5, fetchdecode0 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE0_SEL__DISABLE, fetchdecode0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK ((uint32_t)(0xA90)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0x290)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS ((uint32_t)(0xA94)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x294)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS ((uint32_t)(0xA98)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_OFFSET ((uint32_t)(0x298)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_SHIFT 16U +/* Field Value: FETCHECO0_SEL__STORE9, fetcheco0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE9 0x1U +/* Field Value: FETCHECO0_SEL__EXTDST0, fetcheco0 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO0_SEL__EXTDST4, fetcheco0 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO0_SEL__EXTDST1, fetcheco0 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO0_SEL__EXTDST5, fetcheco0 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO0_SEL__STORE4, fetcheco0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE4 0x6U +/* Field Value: FETCHECO0_SEL__STORE5, fetcheco0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE5 0x7U +/* Field Value: FETCHECO0_SEL__DISABLE, fetcheco0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0xAA0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2A0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0xAA4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x2A4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC ((uint32_t)(0xAA8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_OFFSET ((uint32_t)(0x2A8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE1_SRC_SEL__DISABLE, Unit fetchdecode1 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHECO1, Unit fetchdecode1 input port + * src is connected to output of unit fetcheco1 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1 0x1FU +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHDECODE3, Unit fetchdecode1 input + * port src is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHDECODE3 0x19U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS ((uint32_t)(0xAAC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x2AC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_SHIFT 16U +/* Field Value: FETCHDECODE1_SEL__STORE9, fetchdecode1 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE1_SEL__EXTDST0, fetchdecode1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE1_SEL__EXTDST4, fetchdecode1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE1_SEL__EXTDST1, fetchdecode1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE1_SEL__EXTDST5, fetchdecode1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE1_SEL__STORE4, fetchdecode1 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE1_SEL__STORE5, fetchdecode1 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE1_SEL__DISABLE, fetchdecode1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK ((uint32_t)(0xAB0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2B0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS ((uint32_t)(0xAB4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x2B4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS ((uint32_t)(0xAB8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_OFFSET ((uint32_t)(0x2B8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_SHIFT 16U +/* Field Value: FETCHECO1_SEL__STORE9, fetcheco1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE9 0x1U +/* Field Value: FETCHECO1_SEL__EXTDST0, fetcheco1 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO1_SEL__EXTDST4, fetcheco1 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO1_SEL__EXTDST1, fetcheco1 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO1_SEL__EXTDST5, fetcheco1 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO1_SEL__STORE4, fetcheco1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE4 0x6U +/* Field Value: FETCHECO1_SEL__STORE5, fetcheco1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE5 0x7U +/* Field Value: FETCHECO1_SEL__DISABLE, fetcheco1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0xAC0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0x2C0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0xAC4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x2C4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS ((uint32_t)(0xAC8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x2C8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_SHIFT 16U +/* Field Value: FETCHLAYER0_SEL__STORE9, fetchlayer0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE9 0x1U +/* Field Value: FETCHLAYER0_SEL__EXTDST0, fetchlayer0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST0 0x2U +/* Field Value: FETCHLAYER0_SEL__EXTDST4, fetchlayer0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST4 0x3U +/* Field Value: FETCHLAYER0_SEL__EXTDST1, fetchlayer0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST1 0x4U +/* Field Value: FETCHLAYER0_SEL__EXTDST5, fetchlayer0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST5 0x5U +/* Field Value: FETCHLAYER0_SEL__STORE4, fetchlayer0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE4 0x6U +/* Field Value: FETCHLAYER0_SEL__STORE5, fetchlayer0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE5 0x7U +/* Field Value: FETCHLAYER0_SEL__DISABLE, fetchlayer0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK ((uint32_t)(0xAE0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0x2E0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS ((uint32_t)(0xAE4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x2E4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC ((uint32_t)(0xAE8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_OFFSET ((uint32_t)(0x2E8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX4_SRC_SEL__DISABLE, Unit matrix4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX4_SRC_SEL__GAMMACOR4, Unit matrix4 input port src is + * connected to output of unit gammacor4 */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__GAMMACOR4 0x22U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_SHIFT 24U +/* Field Value: MATRIX4_CLKEN__DISABLE, Clock for matrix4 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__DISABLE 0U +/* Field Value: MATRIX4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX4_CLKEN__FULL, Clock for matrix4 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS ((uint32_t)(0xAEC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_OFFSET ((uint32_t)(0x2EC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_SHIFT 16U +/* Field Value: MATRIX4_SEL__STORE9, matrix4 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE9 0x1U +/* Field Value: MATRIX4_SEL__EXTDST0, matrix4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST0 0x2U +/* Field Value: MATRIX4_SEL__EXTDST4, matrix4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST4 0x3U +/* Field Value: MATRIX4_SEL__EXTDST1, matrix4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST1 0x4U +/* Field Value: MATRIX4_SEL__EXTDST5, matrix4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST5 0x5U +/* Field Value: MATRIX4_SEL__STORE4, matrix4 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE4 0x6U +/* Field Value: MATRIX4_SEL__STORE5, matrix4 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE5 0x7U +/* Field Value: MATRIX4_SEL__DISABLE, matrix4 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK ((uint32_t)(0xB00)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x300)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS ((uint32_t)(0xB04)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x304)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC ((uint32_t)(0xB08)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x308)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER4_SRC_SEL__DISABLE, Unit hscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER4_SRC_SEL__EXTSRC4, Unit hscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE0, Unit hscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE2, Unit hscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: HSCALER4_SRC_SEL__MATRIX4, Unit hscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__MATRIX4 0x23U +/* Field Value: HSCALER4_SRC_SEL__VSCALER4, Unit hscaler4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__VSCALER4 0x25U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_SHIFT 24U +/* Field Value: HSCALER4_CLKEN__DISABLE, Clock for hscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__DISABLE 0U +/* Field Value: HSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER4_CLKEN__FULL, Clock for hscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS ((uint32_t)(0xB0C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_OFFSET ((uint32_t)(0x30C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_SHIFT 16U +/* Field Value: HSCALER4_SEL__STORE9, hscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE9 0x1U +/* Field Value: HSCALER4_SEL__EXTDST0, hscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST0 0x2U +/* Field Value: HSCALER4_SEL__EXTDST4, hscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST4 0x3U +/* Field Value: HSCALER4_SEL__EXTDST1, hscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST1 0x4U +/* Field Value: HSCALER4_SEL__EXTDST5, hscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST5 0x5U +/* Field Value: HSCALER4_SEL__STORE4, hscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE4 0x6U +/* Field Value: HSCALER4_SEL__STORE5, hscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE5 0x7U +/* Field Value: HSCALER4_SEL__DISABLE, hscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK ((uint32_t)(0xB20)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x320)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS ((uint32_t)(0xB24)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x324)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC ((uint32_t)(0xB28)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x328)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER4_SRC_SEL__DISABLE, Unit vscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER4_SRC_SEL__EXTSRC4, Unit vscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE0, Unit vscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE2, Unit vscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: VSCALER4_SRC_SEL__HSCALER4, Unit vscaler4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__HSCALER4 0x24U +/* Field Value: VSCALER4_SRC_SEL__MATRIX4, Unit vscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__MATRIX4 0x23U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_SHIFT 24U +/* Field Value: VSCALER4_CLKEN__DISABLE, Clock for vscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__DISABLE 0U +/* Field Value: VSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER4_CLKEN__FULL, Clock for vscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS ((uint32_t)(0xB2C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_OFFSET ((uint32_t)(0x32C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_SHIFT 16U +/* Field Value: VSCALER4_SEL__STORE9, vscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE9 0x1U +/* Field Value: VSCALER4_SEL__EXTDST0, vscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST0 0x2U +/* Field Value: VSCALER4_SEL__EXTDST4, vscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST4 0x3U +/* Field Value: VSCALER4_SEL__EXTDST1, vscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST1 0x4U +/* Field Value: VSCALER4_SEL__EXTDST5, vscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST5 0x5U +/* Field Value: VSCALER4_SEL__STORE4, vscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE4 0x6U +/* Field Value: VSCALER4_SEL__STORE5, vscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE5 0x7U +/* Field Value: VSCALER4_SEL__DISABLE, vscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK ((uint32_t)(0xB40)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0x340)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS ((uint32_t)(0xB44)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x344)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC ((uint32_t)(0xB48)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_OFFSET ((uint32_t)(0x348)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX5_SRC_SEL__DISABLE, Unit matrix5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX5_SRC_SEL__GAMMACOR5, Unit matrix5 input port src is + * connected to output of unit gammacor5 */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__GAMMACOR5 0x27U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_SHIFT 24U +/* Field Value: MATRIX5_CLKEN__DISABLE, Clock for matrix5 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__DISABLE 0U +/* Field Value: MATRIX5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX5_CLKEN__FULL, Clock for matrix5 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS ((uint32_t)(0xB4C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_OFFSET ((uint32_t)(0x34C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_SHIFT 16U +/* Field Value: MATRIX5_SEL__STORE9, matrix5 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE9 0x1U +/* Field Value: MATRIX5_SEL__EXTDST0, matrix5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST0 0x2U +/* Field Value: MATRIX5_SEL__EXTDST4, matrix5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST4 0x3U +/* Field Value: MATRIX5_SEL__EXTDST1, matrix5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST1 0x4U +/* Field Value: MATRIX5_SEL__EXTDST5, matrix5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST5 0x5U +/* Field Value: MATRIX5_SEL__STORE4, matrix5 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE4 0x6U +/* Field Value: MATRIX5_SEL__STORE5, matrix5 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE5 0x7U +/* Field Value: MATRIX5_SEL__DISABLE, matrix5 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK ((uint32_t)(0xB60)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x360)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS ((uint32_t)(0xB64)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x364)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC ((uint32_t)(0xB68)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x368)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER5_SRC_SEL__DISABLE, Unit hscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER5_SRC_SEL__EXTSRC5, Unit hscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE1, Unit hscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE3, Unit hscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: HSCALER5_SRC_SEL__MATRIX5, Unit hscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__MATRIX5 0x28U +/* Field Value: HSCALER5_SRC_SEL__VSCALER5, Unit hscaler5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__VSCALER5 0x2AU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_SHIFT 24U +/* Field Value: HSCALER5_CLKEN__DISABLE, Clock for hscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__DISABLE 0U +/* Field Value: HSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER5_CLKEN__FULL, Clock for hscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS ((uint32_t)(0xB6C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_OFFSET ((uint32_t)(0x36C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_SHIFT 16U +/* Field Value: HSCALER5_SEL__STORE9, hscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE9 0x1U +/* Field Value: HSCALER5_SEL__EXTDST0, hscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST0 0x2U +/* Field Value: HSCALER5_SEL__EXTDST4, hscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST4 0x3U +/* Field Value: HSCALER5_SEL__EXTDST1, hscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST1 0x4U +/* Field Value: HSCALER5_SEL__EXTDST5, hscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST5 0x5U +/* Field Value: HSCALER5_SEL__STORE4, hscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE4 0x6U +/* Field Value: HSCALER5_SEL__STORE5, hscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE5 0x7U +/* Field Value: HSCALER5_SEL__DISABLE, hscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK ((uint32_t)(0xB80)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x380)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS ((uint32_t)(0xB84)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x384)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC ((uint32_t)(0xB88)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x388)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER5_SRC_SEL__DISABLE, Unit vscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER5_SRC_SEL__EXTSRC5, Unit vscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE1, Unit vscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE3, Unit vscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: VSCALER5_SRC_SEL__HSCALER5, Unit vscaler5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__HSCALER5 0x29U +/* Field Value: VSCALER5_SRC_SEL__MATRIX5, Unit vscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__MATRIX5 0x28U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_SHIFT 24U +/* Field Value: VSCALER5_CLKEN__DISABLE, Clock for vscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__DISABLE 0U +/* Field Value: VSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER5_CLKEN__FULL, Clock for vscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS ((uint32_t)(0xB8C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_OFFSET ((uint32_t)(0x38C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_SHIFT 16U +/* Field Value: VSCALER5_SEL__STORE9, vscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE9 0x1U +/* Field Value: VSCALER5_SEL__EXTDST0, vscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST0 0x2U +/* Field Value: VSCALER5_SEL__EXTDST4, vscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST4 0x3U +/* Field Value: VSCALER5_SEL__EXTDST1, vscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST1 0x4U +/* Field Value: VSCALER5_SEL__EXTDST5, vscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST5 0x5U +/* Field Value: VSCALER5_SEL__STORE4, vscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE4 0x6U +/* Field Value: VSCALER5_SEL__STORE5, vscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE5 0x7U +/* Field Value: VSCALER5_SEL__DISABLE, vscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xBA0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0x3A0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xBA4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x3A4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC ((uint32_t)(0xBA8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_OFFSET ((uint32_t)(0x3A8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_VALUE 0x1001C0CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__DISABLE, Unit layerblend0 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__BLITBLEND9, Unit layerblend0 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME0, Unit layerblend0 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME1, Unit layerblend0 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME4, Unit layerblend0 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME5, Unit layerblend0 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX4, Unit layerblend0 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER4, Unit layerblend0 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER4, Unit layerblend0 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC4, Unit layerblend0 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX5, Unit layerblend0 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER5, Unit layerblend0 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER5, Unit layerblend0 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC5, Unit layerblend0 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC5 0x16U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND0_SEC_SEL__DISABLE, Unit layerblend0 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE2, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE3, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHWARP2, Unit layerblend0 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE0, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE1, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX4, Unit layerblend0 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER4, Unit layerblend0 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER4, Unit layerblend0 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX5, Unit layerblend0 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER5, Unit layerblend0 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER5, Unit layerblend0 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER0, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER1, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND0_CLKEN__DISABLE, Clock for layerblend0 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND0_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND0_CLKEN__FULL, Clock for layerblend0 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS ((uint32_t)(0xBAC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_OFFSET ((uint32_t)(0x3AC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_SHIFT 16U +/* Field Value: LAYERBLEND0_SEL__STORE9, layerblend0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND0_SEL__EXTDST0, layerblend0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND0_SEL__EXTDST4, layerblend0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND0_SEL__EXTDST1, layerblend0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND0_SEL__EXTDST5, layerblend0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND0_SEL__STORE4, layerblend0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND0_SEL__STORE5, layerblend0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND0_SEL__DISABLE, layerblend0 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xBC0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0x3C0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xBC4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x3C4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC ((uint32_t)(0xBC8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_OFFSET ((uint32_t)(0x3C8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_VALUE 0x1001E10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__DISABLE, Unit layerblend1 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__BLITBLEND9, Unit layerblend1 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME0, Unit layerblend1 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME1, Unit layerblend1 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME4, Unit layerblend1 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME5, Unit layerblend1 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX4, Unit layerblend1 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER4, Unit layerblend1 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER4, Unit layerblend1 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC4, Unit layerblend1 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX5, Unit layerblend1 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER5, Unit layerblend1 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER5, Unit layerblend1 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC5, Unit layerblend1 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND1_PRIM_SEL__LAYERBLEND0, Unit layerblend1 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND1_SEC_SEL__DISABLE, Unit layerblend1 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE2, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE3, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHWARP2, Unit layerblend1 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE0, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE1, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX4, Unit layerblend1 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER4, Unit layerblend1 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER4, Unit layerblend1 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX5, Unit layerblend1 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER5, Unit layerblend1 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER5, Unit layerblend1 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER0, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER1, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND1_CLKEN__DISABLE, Clock for layerblend1 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND1_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND1_CLKEN__FULL, Clock for layerblend1 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS ((uint32_t)(0xBCC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_OFFSET ((uint32_t)(0x3CC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_SHIFT 16U +/* Field Value: LAYERBLEND1_SEL__STORE9, layerblend1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND1_SEL__EXTDST0, layerblend1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND1_SEL__EXTDST4, layerblend1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND1_SEL__EXTDST1, layerblend1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND1_SEL__EXTDST5, layerblend1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND1_SEL__STORE4, layerblend1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND1_SEL__STORE5, layerblend1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND1_SEL__DISABLE, layerblend1 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xBE0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0x3E0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xBE4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x3E4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC ((uint32_t)(0xBE8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_OFFSET ((uint32_t)(0x3E8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__DISABLE, Unit layerblend2 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__BLITBLEND9, Unit layerblend2 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME0, Unit layerblend2 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME1, Unit layerblend2 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME4, Unit layerblend2 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME5, Unit layerblend2 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX4, Unit layerblend2 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER4, Unit layerblend2 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER4, Unit layerblend2 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC4, Unit layerblend2 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX5, Unit layerblend2 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER5, Unit layerblend2 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER5, Unit layerblend2 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC5, Unit layerblend2 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND1, Unit layerblend2 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND0, Unit layerblend2 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND2_SEC_SEL__DISABLE, Unit layerblend2 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE2, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE3, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHWARP2, Unit layerblend2 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE0, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE1, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX4, Unit layerblend2 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER4, Unit layerblend2 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER4, Unit layerblend2 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX5, Unit layerblend2 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER5, Unit layerblend2 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER5, Unit layerblend2 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER0, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER1, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND2_CLKEN__DISABLE, Clock for layerblend2 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND2_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND2_CLKEN__FULL, Clock for layerblend2 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS ((uint32_t)(0xBEC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_OFFSET ((uint32_t)(0x3EC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_SHIFT 16U +/* Field Value: LAYERBLEND2_SEL__STORE9, layerblend2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND2_SEL__EXTDST0, layerblend2 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND2_SEL__EXTDST4, layerblend2 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND2_SEL__EXTDST1, layerblend2 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND2_SEL__EXTDST5, layerblend2 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND2_SEL__STORE4, layerblend2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND2_SEL__STORE5, layerblend2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND2_SEL__DISABLE, layerblend2 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xC00)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xC04)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC ((uint32_t)(0xC08)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__DISABLE, Unit layerblend3 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__BLITBLEND9, Unit layerblend3 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME0, Unit layerblend3 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME1, Unit layerblend3 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME4, Unit layerblend3 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME5, Unit layerblend3 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX4, Unit layerblend3 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER4, Unit layerblend3 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER4, Unit layerblend3 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC4, Unit layerblend3 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX5, Unit layerblend3 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER5, Unit layerblend3 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER5, Unit layerblend3 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC5, Unit layerblend3 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND2, Unit layerblend3 input + * port prim is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND2 0x2EU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND1, Unit layerblend3 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND0, Unit layerblend3 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND3_SEC_SEL__DISABLE, Unit layerblend3 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE2, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE3, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHWARP2, Unit layerblend3 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE0, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE1, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX4, Unit layerblend3 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER4, Unit layerblend3 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER4, Unit layerblend3 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX5, Unit layerblend3 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER5, Unit layerblend3 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER5, Unit layerblend3 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER0, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER1, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND3_CLKEN__DISABLE, Clock for layerblend3 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND3_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND3_CLKEN__FULL, Clock for layerblend3 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS ((uint32_t)(0xC0C)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_SHIFT 16U +/* Field Value: LAYERBLEND3_SEL__STORE9, layerblend3 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND3_SEL__EXTDST0, layerblend3 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND3_SEL__EXTDST4, layerblend3 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND3_SEL__EXTDST1, layerblend3 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND3_SEL__EXTDST5, layerblend3 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND3_SEL__STORE4, layerblend3 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND3_SEL__STORE5, layerblend3 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND3_SEL__DISABLE, layerblend3 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__DISABLE 0U + +/* Register: IMXDPUV1_FetchDecode9_LockUnlock */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x1000)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode9_LockStatus */ +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x1004)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_StaticControl */ +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL ((uint32_t)(0x1008)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x100C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode9_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0 ((uint32_t)(0x1010)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0 ((uint32_t)(0x1014)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0 ((uint32_t)(0x1018)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0 ((uint32_t)(0x101C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1020)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1024)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0 ((uint32_t)(0x1028)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x102C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0 ((uint32_t)(0x1030)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1034)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1038)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0 ((uint32_t)(0x103C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0 ((uint32_t)(0x1040)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS ((uint32_t)(0x1044)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameResampling */ +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING ((uint32_t)(0x1048)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_DecodeControl */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL ((uint32_t)(0x104C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH ((uint32_t)(0x1050)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Control */ +#define IMXDPUV1_FETCHDECODE9_CONTROL ((uint32_t)(0x1054)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode9_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER ((uint32_t)(0x1058)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Start */ +#define IMXDPUV1_FETCHDECODE9_START ((uint32_t)(0x105C)) +#define IMXDPUV1_FETCHDECODE9_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FetchType */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE ((uint32_t)(0x1060)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode9_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS ((uint32_t)(0x1064)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode9_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE9_READADDRESS0 ((uint32_t)(0x1068)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x106C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_Status */ +#define IMXDPUV1_FETCHDECODE9_STATUS ((uint32_t)(0x1070)) +#define IMXDPUV1_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode9_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS ((uint32_t)(0x1074)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_ColorPalette */ +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE ((uint32_t)(0x1400)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_LockUnlock */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x1800)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp9_LockStatus */ +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x1804)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_StaticControl */ +#define IMXDPUV1_FETCHWARP9_STATICCONTROL ((uint32_t)(0x1808)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x180C)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0 ((uint32_t)(0x1810)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1814)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1818)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0 ((uint32_t)(0x181C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1820)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0 ((uint32_t)(0x1824)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1828)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x182C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0 ((uint32_t)(0x1830)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0 ((uint32_t)(0x1834)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1 ((uint32_t)(0x1838)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x183C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x1840)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1 ((uint32_t)(0x1844)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1 ((uint32_t)(0x1848)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1 ((uint32_t)(0x184C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1 ((uint32_t)(0x1850)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x1854)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1 ((uint32_t)(0x1858)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1 ((uint32_t)(0x185C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2 ((uint32_t)(0x1860)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x1864)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x1868)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2 ((uint32_t)(0x186C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2 ((uint32_t)(0x1870)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2 ((uint32_t)(0x1874)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2 ((uint32_t)(0x1878)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x187C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2 ((uint32_t)(0x1880)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2 ((uint32_t)(0x1884)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3 ((uint32_t)(0x1888)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x188C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x1890)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3 ((uint32_t)(0x1894)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3 ((uint32_t)(0x1898)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3 ((uint32_t)(0x189C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3 ((uint32_t)(0x18A0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x18A4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3 ((uint32_t)(0x18A8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3 ((uint32_t)(0x18AC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4 ((uint32_t)(0x18B0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x18B4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x18B8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4 ((uint32_t)(0x18BC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4 ((uint32_t)(0x18C0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4 ((uint32_t)(0x18C4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4 ((uint32_t)(0x18C8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x18CC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4 ((uint32_t)(0x18D0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4 ((uint32_t)(0x18D4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5 ((uint32_t)(0x18D8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x18DC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x18E0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5 ((uint32_t)(0x18E4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5 ((uint32_t)(0x18E8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5 ((uint32_t)(0x18EC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5 ((uint32_t)(0x18F0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x18F4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5 ((uint32_t)(0x18F8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5 ((uint32_t)(0x18FC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6 ((uint32_t)(0x1900)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x1904)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x1908)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6 ((uint32_t)(0x190C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6 ((uint32_t)(0x1910)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6 ((uint32_t)(0x1914)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6 ((uint32_t)(0x1918)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x191C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6 ((uint32_t)(0x1920)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6 ((uint32_t)(0x1924)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7 ((uint32_t)(0x1928)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x192C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x1930)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7 ((uint32_t)(0x1934)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7 ((uint32_t)(0x1938)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7 ((uint32_t)(0x193C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7 ((uint32_t)(0x1940)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x1944)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7 ((uint32_t)(0x1948)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7 ((uint32_t)(0x194C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameDimensions */ +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS ((uint32_t)(0x1950)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameResampling */ +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING ((uint32_t)(0x1954)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_WarpControl */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL ((uint32_t)(0x1958)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartX */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTX ((uint32_t)(0x195C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartY */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTY ((uint32_t)(0x1960)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbDelta */ +#define IMXDPUV1_FETCHWARP9_ARBDELTA ((uint32_t)(0x1964)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_FIRPositions */ +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS ((uint32_t)(0x1968)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS ((uint32_t)(0x196C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_Control */ +#define IMXDPUV1_FETCHWARP9_CONTROL ((uint32_t)(0x1970)) +#define IMXDPUV1_FETCHWARP9_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp9_TriggerEnable */ +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE ((uint32_t)(0x1974)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ControlTrigger */ +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER ((uint32_t)(0x1978)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_Start */ +#define IMXDPUV1_FETCHWARP9_START ((uint32_t)(0x197C)) +#define IMXDPUV1_FETCHWARP9_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_FetchType */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE ((uint32_t)(0x1980)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1984)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_Status */ +#define IMXDPUV1_FETCHWARP9_STATUS ((uint32_t)(0x1988)) +#define IMXDPUV1_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp9_HiddenStatus */ +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS ((uint32_t)(0x198C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_LockUnlock */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x1C00)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco9_LockStatus */ +#define IMXDPUV1_FETCHECO9_LOCKSTATUS ((uint32_t)(0x1C04)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_StaticControl */ +#define IMXDPUV1_FETCHECO9_STATICCONTROL ((uint32_t)(0x1C08)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x1C0C)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco9_BaseAddress0 */ +#define IMXDPUV1_FETCHECO9_BASEADDRESS0 ((uint32_t)(0x1C10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1C14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1C18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0 ((uint32_t)(0x1C1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1C20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerOffset0 */ +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0 ((uint32_t)(0x1C24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1C28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1C2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ConstantColor0 */ +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0 ((uint32_t)(0x1C30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerProperty0 */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0 ((uint32_t)(0x1C34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameDimensions */ +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS ((uint32_t)(0x1C38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameResampling */ +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING ((uint32_t)(0x1C3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_Control */ +#define IMXDPUV1_FETCHECO9_CONTROL ((uint32_t)(0x1C40)) +#define IMXDPUV1_FETCHECO9_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco9_ControlTrigger */ +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER ((uint32_t)(0x1C44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_Start */ +#define IMXDPUV1_FETCHECO9_START ((uint32_t)(0x1C48)) +#define IMXDPUV1_FETCHECO9_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_FetchType */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE ((uint32_t)(0x1C4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1C50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_HiddenStatus */ +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS ((uint32_t)(0x1C54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_LockUnlock */ +#define IMXDPUV1_ROP9_LOCKUNLOCK ((uint32_t)(0x2000)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_rop9_LockStatus */ +#define IMXDPUV1_ROP9_LOCKSTATUS ((uint32_t)(0x2004)) +#define IMXDPUV1_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_StaticControl */ +#define IMXDPUV1_ROP9_STATICCONTROL ((uint32_t)(0x2008)) +#define IMXDPUV1_ROP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_rop9_Control */ +#define IMXDPUV1_ROP9_CONTROL ((uint32_t)(0x200C)) +#define IMXDPUV1_ROP9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_ROP9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_ROP9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode */ +#define IMXDPUV1_ROP9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_ROP9_CONTROL_MODE__OPERATION 0x1U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_MASK 0x10U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_SHIFT 4U +/* Field Value: ALPHAMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ROP 0U +/* Field Value: ALPHAMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_MASK 0x20U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_SHIFT 5U +/* Field Value: BLUEMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ROP 0U +/* Field Value: BLUEMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_MASK 0x40U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_SHIFT 6U +/* Field Value: GREENMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ROP 0U +/* Field Value: GREENMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_MASK 0x80U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_SHIFT 7U +/* Field Value: REDMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ROP 0U +/* Field Value: REDMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_MASK 0x100U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_SHIFT 8U +/* Field Value: PRIMDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__BYPASS 0U +/* Field Value: PRIMDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_MASK 0x200U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_SHIFT 9U +/* Field Value: SECDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__BYPASS 0U +/* Field Value: SECDIV2__DIVIDEBY2, Input is divided by two/shift to the right + * by one */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_MASK 0x400U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_SHIFT 10U +/* Field Value: TERTDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__BYPASS 0U +/* Field Value: TERTDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__DIVIDEBY2 0x1U + +/* Register: IMXDPUV1_rop9_RasterOperationIndices */ +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES ((uint32_t)(0x2010)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_VALUE 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_MASK 0xFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_SHIFT 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_MASK 0xFF00U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_SHIFT 8U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_MASK 0xFF0000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_SHIFT 16U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_MASK 0xFF000000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_SHIFT 24U + +/* Register: IMXDPUV1_rop9_PrimControlWord */ +#define IMXDPUV1_ROP9_PRIMCONTROLWORD ((uint32_t)(0x2014)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_SecControlWord */ +#define IMXDPUV1_ROP9_SECCONTROLWORD ((uint32_t)(0x2018)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_TertControlWord */ +#define IMXDPUV1_ROP9_TERTCONTROLWORD ((uint32_t)(0x201C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LockUnlock */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK ((uint32_t)(0x2400)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_clut9_LockStatus */ +#define IMXDPUV1_CLUT9_LOCKSTATUS ((uint32_t)(0x2404)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_StaticControl */ +#define IMXDPUV1_CLUT9_STATICCONTROL ((uint32_t)(0x2408)) +#define IMXDPUV1_CLUT9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_clut9_UnshadowedControl */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL ((uint32_t)(0x240C)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT 0U +/* Field Value: B_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__DISABLE 0U +/* Field Value: B_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK 0x2U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT 1U +/* Field Value: G_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__DISABLE 0U +/* Field Value: G_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK 0x4U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT 2U +/* Field Value: R_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__DISABLE 0U +/* Field Value: R_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE 0x1U + +/* Register: IMXDPUV1_clut9_Control */ +#define IMXDPUV1_CLUT9_CONTROL ((uint32_t)(0x2410)) +#define IMXDPUV1_CLUT9_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CLUT9_CONTROL_RESET_VALUE 0x800U +#define IMXDPUV1_CLUT9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_CLUT9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, module in neutral mode, input data is bypassed + * to the output */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__LUT, module in color lookup mode (LUT holds a 10bit + * color value for CLut derivate and 8bit color value for CLutL derivate + * for each input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__LUT 0x1U +/* Field Value: MODE__INDEX_10BIT, module in 10bit color index table mode + * (LUT holds a 3x10bit color value for derivate CLut and 3x8bit color value + * for CLUTL derivate, indexed with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_10BIT 0x2U +/* Field Value: MODE__INDEX_RGBA, module in RGBA color index table mode (LUT + * holds a 3x8bit color value and a 6bit alpha value for CLut derivate + * and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed + * with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_RGBA 0x3U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_MASK 0x10U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_SHIFT 4U +/* Field Value: COL_8BIT__DISABLE, color is 10bit output */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__DISABLE 0U +/* Field Value: COL_8BIT__ENABLE, color is 8bit output (dithering of internal + * 10bit value) */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_MASK 0x20U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_SHIFT 5U +/* Field Value: ALPHAMASK__DISABLE, Alpha mask mode disabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__DISABLE 0U +/* Field Value: ALPHAMASK__ENABLE, Alpha mask mode enabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_MASK 0x40U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_SHIFT 6U +/* Field Value: ALPHAINVERT__NORMAL, Disable computation for alpha smaller + * than 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__NORMAL 0U +/* Field Value: ALPHAINVERT__INVERT, Disable computation for alpha greater + * than or equal to 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__INVERT 0x1U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_MASK 0xF00U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_Status */ +#define IMXDPUV1_CLUT9_STATUS ((uint32_t)(0x2414)) +#define IMXDPUV1_CLUT9_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_MASK 0x1U +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT 0U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_MASK 0x10U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_clut9_LastControlWord */ +#define IMXDPUV1_CLUT9_LASTCONTROLWORD ((uint32_t)(0x2418)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LUT */ +#define IMXDPUV1_CLUT9_LUT ((uint32_t)(0x2800)) +#define IMXDPUV1_CLUT9_LUT_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LUT_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LUT_RESET_MASK 0xC0000000U +#define IMXDPUV1_CLUT9_LUT_BLUE_MASK 0x3FFU +#define IMXDPUV1_CLUT9_LUT_BLUE_SHIFT 0U +#define IMXDPUV1_CLUT9_LUT_GREEN_MASK 0xFFC00U +#define IMXDPUV1_CLUT9_LUT_GREEN_SHIFT 10U +#define IMXDPUV1_CLUT9_LUT_RED_MASK 0x3FF00000U +#define IMXDPUV1_CLUT9_LUT_RED_SHIFT 20U + +/* Register: IMXDPUV1_matrix9_LockUnlock */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK ((uint32_t)(0x2C00)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix9_LockStatus */ +#define IMXDPUV1_MATRIX9_LOCKSTATUS ((uint32_t)(0x2C04)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix9_StaticControl */ +#define IMXDPUV1_MATRIX9_STATICCONTROL ((uint32_t)(0x2C08)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix9_Control */ +#define IMXDPUV1_MATRIX9_CONTROL ((uint32_t)(0x2C0C)) +#define IMXDPUV1_MATRIX9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix9_Red0 */ +#define IMXDPUV1_MATRIX9_RED0 ((uint32_t)(0x2C10)) +#define IMXDPUV1_MATRIX9_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX9_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Red1 */ +#define IMXDPUV1_MATRIX9_RED1 ((uint32_t)(0x2C14)) +#define IMXDPUV1_MATRIX9_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX9_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green0 */ +#define IMXDPUV1_MATRIX9_GREEN0 ((uint32_t)(0x2C18)) +#define IMXDPUV1_MATRIX9_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX9_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green1 */ +#define IMXDPUV1_MATRIX9_GREEN1 ((uint32_t)(0x2C1C)) +#define IMXDPUV1_MATRIX9_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX9_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue0 */ +#define IMXDPUV1_MATRIX9_BLUE0 ((uint32_t)(0x2C20)) +#define IMXDPUV1_MATRIX9_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX9_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue1 */ +#define IMXDPUV1_MATRIX9_BLUE1 ((uint32_t)(0x2C24)) +#define IMXDPUV1_MATRIX9_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX9_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha0 */ +#define IMXDPUV1_MATRIX9_ALPHA0 ((uint32_t)(0x2C28)) +#define IMXDPUV1_MATRIX9_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha1 */ +#define IMXDPUV1_MATRIX9_ALPHA1 ((uint32_t)(0x2C2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector0 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0 ((uint32_t)(0x2C30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector1 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1 ((uint32_t)(0x2C34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_LastControlWord */ +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD ((uint32_t)(0x2C38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_LockUnlock */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK ((uint32_t)(0x3000)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler9_LockStatus */ +#define IMXDPUV1_HSCALER9_LOCKSTATUS ((uint32_t)(0x3004)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler9_StaticControl */ +#define IMXDPUV1_HSCALER9_STATICCONTROL ((uint32_t)(0x3008)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup1 */ +#define IMXDPUV1_HSCALER9_SETUP1 ((uint32_t)(0x300C)) +#define IMXDPUV1_HSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup2 */ +#define IMXDPUV1_HSCALER9_SETUP2 ((uint32_t)(0x3010)) +#define IMXDPUV1_HSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Control */ +#define IMXDPUV1_HSCALER9_CONTROL ((uint32_t)(0x3014)) +#define IMXDPUV1_HSCALER9_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler9_LockUnlock */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK ((uint32_t)(0x3400)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler9_LockStatus */ +#define IMXDPUV1_VSCALER9_LOCKSTATUS ((uint32_t)(0x3404)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler9_StaticControl */ +#define IMXDPUV1_VSCALER9_STATICCONTROL ((uint32_t)(0x3408)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup1 */ +#define IMXDPUV1_VSCALER9_SETUP1 ((uint32_t)(0x340C)) +#define IMXDPUV1_VSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup2 */ +#define IMXDPUV1_VSCALER9_SETUP2 ((uint32_t)(0x3410)) +#define IMXDPUV1_VSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup3 */ +#define IMXDPUV1_VSCALER9_SETUP3 ((uint32_t)(0x3414)) +#define IMXDPUV1_VSCALER9_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER9_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup4 */ +#define IMXDPUV1_VSCALER9_SETUP4 ((uint32_t)(0x3418)) +#define IMXDPUV1_VSCALER9_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER9_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup5 */ +#define IMXDPUV1_VSCALER9_SETUP5 ((uint32_t)(0x341C)) +#define IMXDPUV1_VSCALER9_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER9_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Control */ +#define IMXDPUV1_VSCALER9_CONTROL ((uint32_t)(0x3420)) +#define IMXDPUV1_VSCALER9_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER9_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_filter9_LockUnlock */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK ((uint32_t)(0x3800)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_filter9_LockStatus */ +#define IMXDPUV1_FILTER9_LOCKSTATUS ((uint32_t)(0x3804)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_filter9_StaticControl */ +#define IMXDPUV1_FILTER9_STATICCONTROL ((uint32_t)(0x3808)) +#define IMXDPUV1_FILTER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_filter9_Control */ +#define IMXDPUV1_FILTER9_CONTROL ((uint32_t)(0x380C)) +#define IMXDPUV1_FILTER9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FILTER9_CONTROL_RESET_VALUE 0x5500U +#define IMXDPUV1_FILTER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_FILTER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the filter, all + * other settings are ignored. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Filter is active. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_MASK 0x30U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_SHIFT 4U +/* Field Value: TILE_MODE__PAD, Samples outside the frame are padded with + * the last valid border pixels. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD 0U +/* Field Value: TILE_MODE__ZERO, Samples outside the frame are treated as + * zero pixel value. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__ZERO 0x1U +/* Field Value: TILE_MODE__PAD_ZERO, Applies tile mode PAD to RGB channels + * and tile mode ZERO to alpha channel. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD_ZERO 0x2U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_MASK 0xFFFF00U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__FIR_5X5, FIR filter 5x5 window. */ +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE__FIR_5X5 0x55U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_MASK 0x30000000U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_SHIFT 28U +/* Field Value: BUFFER_FORMAT__RGB888, RGB888 format. Alpha is not filtered + * but set to constant value 255. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGB888 0U +/* Field Value: BUFFER_FORMAT__RGBA5658, RGBA5658 format. Alpha is filtered. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA5658 0x1U +/* Field Value: BUFFER_FORMAT__RGBA8888, RGBA8888 format. Alpha is filtered. + * The filter window is limited to 5x4. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA8888 0x2U +/* Field Value: BUFFER_FORMAT__RGBA1010108, RGBA10.10.10.8 format. Alpha is + * filtered. The filter window is limited to 5x3. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA1010108 0x3U + +/* Register: IMXDPUV1_filter9_FIR_control */ +#define IMXDPUV1_FILTER9_FIR_CONTROL ((uint32_t)(0x3810)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_MASK 0xFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_SHIFT 0U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_MASK 0xF00U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_SHIFT 8U + +/* Register: IMXDPUV1_filter9_Coefficients0 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS0 ((uint32_t)(0x3814)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients1 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS1 ((uint32_t)(0x3818)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients2 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS2 ((uint32_t)(0x381C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients3 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS3 ((uint32_t)(0x3820)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_VALUE 0x1U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients4 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS4 ((uint32_t)(0x3824)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients5 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS5 ((uint32_t)(0x3828)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients6 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS6 ((uint32_t)(0x382C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_LockUnlock */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x3C00)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_blitblend9_LockStatus */ +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x3C04)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_blitblend9_StaticControl */ +#define IMXDPUV1_BLITBLEND9_STATICCONTROL ((uint32_t)(0x3C08)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_Control */ +#define IMXDPUV1_BLITBLEND9_CONTROL ((uint32_t)(0x3C0C)) +#define IMXDPUV1_BLITBLEND9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode, only route pixels and commands + * from primary input to output */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__OPERATION 0x1U + +/* Register: IMXDPUV1_blitblend9_NeutralBorder */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER ((uint32_t)(0x3C10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_SHIFT 0U +/* Field Value: NEUTRALBORDERMODE__PRIMARY, Bypasses primary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__PRIMARY 0U +/* Field Value: NEUTRALBORDERMODE__SECONDARY, Bypasses secondary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__SECONDARY 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_MASK 0x700U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_MASK 0x7000U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_SHIFT 12U + +/* Register: IMXDPUV1_blitblend9_ConstantColor */ +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR ((uint32_t)(0x3C14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_blitblend9_ColorRedBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION ((uint32_t)(0x3C18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorGreenBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION ((uint32_t)(0x3C1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorBlueBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION ((uint32_t)(0x3C20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_AlphaBlendFunction */ +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION ((uint32_t)(0x3C24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_BlendMode1 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE1 ((uint32_t)(0x3C28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_BlendMode2 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE2 ((uint32_t)(0x3C2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_DirectSetup */ +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP ((uint32_t)(0x3C30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_MASK 0x3FFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_MASK 0x3FF0000U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_SHIFT 16U + +/* Register: IMXDPUV1_blitblend9_PrimControlWord */ +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD ((uint32_t)(0x3C34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_SecControlWord */ +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD ((uint32_t)(0x3C38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_LockUnlock */ +#define IMXDPUV1_STORE9_LOCKUNLOCK ((uint32_t)(0x4000)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_store9_LockStatus */ +#define IMXDPUV1_STORE9_LOCKSTATUS ((uint32_t)(0x4004)) +#define IMXDPUV1_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_store9_StaticControl */ +#define IMXDPUV1_STORE9_STATICCONTROL ((uint32_t)(0x4008)) +#define IMXDPUV1_STORE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0x100U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 8U + +/* Register: IMXDPUV1_store9_BurstBufferManagement */ +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x400C)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x400U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_RingBufStartAddr */ +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR ((uint32_t)(0x4010)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_RingBufWrapAddr */ +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR ((uint32_t)(0x4014)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_BaseAddress */ +#define IMXDPUV1_STORE9_BASEADDRESS ((uint32_t)(0x4018)) +#define IMXDPUV1_STORE9_BASEADDRESS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_DestinationBufferAttributes */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES ((uint32_t)(0x401C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_VALUE 0x200004FFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_MASK 0x1FFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_MASK 0x7F000000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_SHIFT 24U + +/* Register: IMXDPUV1_store9_DestinationBufferDimension */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION ((uint32_t)(0x4020)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_MASK 0x3FFF0000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_SHIFT 16U + +/* Register: IMXDPUV1_store9_FrameOffset */ +#define IMXDPUV1_STORE9_FRAMEOFFSET ((uint32_t)(0x4024)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_MASK 0x7FFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_SHIFT 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_SHIFT 16U + +/* Register: IMXDPUV1_store9_ColorComponentBits */ +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS ((uint32_t)(0x4028)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_VALUE 0x8080808U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_MASK 0xFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_MASK 0xF00U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_MASK 0xF0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_MASK 0xF000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_ColorComponentShift */ +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT ((uint32_t)(0x402C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_VALUE 0x18100800U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_MASK 0x1FU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_MASK 0x1F00U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_MASK 0x1F0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_MASK 0x1F000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_Control */ +#define IMXDPUV1_STORE9_CONTROL ((uint32_t)(0x4030)) +#define IMXDPUV1_STORE9_CONTROL_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_STORE9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_MASK 0x1U +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_SHIFT 0U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_MASK 0x2U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_SHIFT 1U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_MASK 0xF0U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_SHIFT 4U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_MASK 0x1000U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_SHIFT 12U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_MASK 0x30000U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_SHIFT 16U +/* Field Value: YUVCONVERSIONMODE__OFF, No conversion. Input data must be + * RGB. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_MASK 0xC0000U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_SHIFT 18U +/* Field Value: RASTERMODE__NORMAL, RGBA or YUV 4:4:4 pixel buffer. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__YUV422, [Store derivate only] Packed YUV 4:2:2 + * pixel buffer. Effect is that U samples are written for pixels with even + * and V samples for odd column index only. So BitsPerPixel must be set + * to the size that a pair of YU or YV has in memory (most typically 16 + * bits). All correlated widths and horizontal offsets must be even. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422 0x1U +/* Field Value: RASTERMODE__ENCODE, [Store derivate only] RLAD compressed + * bit stream. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__ENCODE 0x2U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_MASK 0x300000U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_SHIFT 20U +/* Field Value: YUV422DOWNSAMPLINGMODE__NEAREST, Nearest mode. Discards all + * odd samples, outputs even samples. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__NEAREST 0U +/* Field Value: YUV422DOWNSAMPLINGMODE__COALIGNED, Linear coaligned mode. + * 3 nearest UV samples are combined in linear filter to get one output sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__COALIGNED 0x1U +/* Field Value: YUV422DOWNSAMPLINGMODE__INTERSPERSED, Linear interspersed + * mode. 2 nearest UV samples are combined in linear filter to get one output + * sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__INTERSPERSED 0x2U + +/* Register: IMXDPUV1_store9_EncodeControl */ +#define IMXDPUV1_STORE9_ENCODECONTROL ((uint32_t)(0x4034)) +#define IMXDPUV1_STORE9_ENCODECONTROL_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_MASK 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_store9_DestinationBufferLength */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH ((uint32_t)(0x4038)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_SHIFT 0U + +/* Register: IMXDPUV1_store9_Start */ +#define IMXDPUV1_STORE9_START ((uint32_t)(0x403C)) +#define IMXDPUV1_STORE9_START_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_STORE9_START_RESET_VALUE 0U +#define IMXDPUV1_STORE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_STORE9_START_START_MASK 0x1U +#define IMXDPUV1_STORE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_store9_EncoderStatus */ +#define IMXDPUV1_STORE9_ENCODERSTATUS ((uint32_t)(0x4040)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_VALUE 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_SHIFT 0U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_MASK 0x80000000U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_SHIFT 31U + +/* Register: IMXDPUV1_store9_WriteAddress */ +#define IMXDPUV1_STORE9_WRITEADDRESS ((uint32_t)(0x4044)) +#define IMXDPUV1_STORE9_WRITEADDRESS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_FrameProperties */ +#define IMXDPUV1_STORE9_FRAMEPROPERTIES ((uint32_t)(0x4048)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_MASK 0x1U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_SHIFT 0U + +/* Register: IMXDPUV1_store9_BurstBufferProperties */ +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x404C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE0FFU +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_LastControlWord */ +#define IMXDPUV1_STORE9_LASTCONTROLWORD ((uint32_t)(0x4050)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_PerfCounter */ +#define IMXDPUV1_STORE9_PERFCOUNTER ((uint32_t)(0x4054)) +#define IMXDPUV1_STORE9_PERFCOUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_store9_Status */ +#define IMXDPUV1_STORE9_STATUS ((uint32_t)(0x4058)) +#define IMXDPUV1_STORE9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATUS_RESET_MASK 0xFFFFFF8EU +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_MASK 0x100U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_SHIFT 8U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_MASK 0x10000U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_SHIFT 16U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_MASK 0x20000U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_SHIFT 17U + +/* Register: IMXDPUV1_constframe0_LockUnlock */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x4400)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe0_LockStatus */ +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x4404)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe0_StaticControl */ +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL ((uint32_t)(0x4408)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS ((uint32_t)(0x440C)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe0_ConstantColor */ +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR ((uint32_t)(0x4410)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe0_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER ((uint32_t)(0x4414)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Start */ +#define IMXDPUV1_CONSTFRAME0_START ((uint32_t)(0x4418)) +#define IMXDPUV1_CONSTFRAME0_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME0_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Status */ +#define IMXDPUV1_CONSTFRAME0_STATUS ((uint32_t)(0x441C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst0_LockUnlock */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK ((uint32_t)(0x4800)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst0_LockStatus */ +#define IMXDPUV1_EXTDST0_LOCKSTATUS ((uint32_t)(0x4804)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst0_StaticControl */ +#define IMXDPUV1_EXTDST0_STATICCONTROL ((uint32_t)(0x4808)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst0_Control */ +#define IMXDPUV1_EXTDST0_CONTROL ((uint32_t)(0x480C)) +#define IMXDPUV1_EXTDST0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_SoftwareKick */ +#define IMXDPUV1_EXTDST0_SOFTWAREKICK ((uint32_t)(0x4810)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_Status */ +#define IMXDPUV1_EXTDST0_STATUS ((uint32_t)(0x4814)) +#define IMXDPUV1_EXTDST0_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_ControlWord */ +#define IMXDPUV1_EXTDST0_CONTROLWORD ((uint32_t)(0x4818)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_CurPixelCnt */ +#define IMXDPUV1_EXTDST0_CURPIXELCNT ((uint32_t)(0x481C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_LastPixelCnt */ +#define IMXDPUV1_EXTDST0_LASTPIXELCNT ((uint32_t)(0x4820)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_PerfCounter */ +#define IMXDPUV1_EXTDST0_PERFCOUNTER ((uint32_t)(0x4824)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_LockUnlock */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x4C00)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe4_LockStatus */ +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x4C04)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe4_StaticControl */ +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL ((uint32_t)(0x4C08)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS ((uint32_t)(0x4C0C)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe4_ConstantColor */ +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR ((uint32_t)(0x4C10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe4_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER ((uint32_t)(0x4C14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Start */ +#define IMXDPUV1_CONSTFRAME4_START ((uint32_t)(0x4C18)) +#define IMXDPUV1_CONSTFRAME4_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME4_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Status */ +#define IMXDPUV1_CONSTFRAME4_STATUS ((uint32_t)(0x4C1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst4_LockUnlock */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK ((uint32_t)(0x5000)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst4_LockStatus */ +#define IMXDPUV1_EXTDST4_LOCKSTATUS ((uint32_t)(0x5004)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst4_StaticControl */ +#define IMXDPUV1_EXTDST4_STATICCONTROL ((uint32_t)(0x5008)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst4_Control */ +#define IMXDPUV1_EXTDST4_CONTROL ((uint32_t)(0x500C)) +#define IMXDPUV1_EXTDST4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_SoftwareKick */ +#define IMXDPUV1_EXTDST4_SOFTWAREKICK ((uint32_t)(0x5010)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_Status */ +#define IMXDPUV1_EXTDST4_STATUS ((uint32_t)(0x5014)) +#define IMXDPUV1_EXTDST4_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_ControlWord */ +#define IMXDPUV1_EXTDST4_CONTROLWORD ((uint32_t)(0x5018)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_CurPixelCnt */ +#define IMXDPUV1_EXTDST4_CURPIXELCNT ((uint32_t)(0x501C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_LastPixelCnt */ +#define IMXDPUV1_EXTDST4_LASTPIXELCNT ((uint32_t)(0x5020)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_PerfCounter */ +#define IMXDPUV1_EXTDST4_PERFCOUNTER ((uint32_t)(0x5024)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_LockUnlock */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x5400)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe1_LockStatus */ +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x5404)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe1_StaticControl */ +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL ((uint32_t)(0x5408)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS ((uint32_t)(0x540C)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe1_ConstantColor */ +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR ((uint32_t)(0x5410)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe1_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER ((uint32_t)(0x5414)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Start */ +#define IMXDPUV1_CONSTFRAME1_START ((uint32_t)(0x5418)) +#define IMXDPUV1_CONSTFRAME1_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME1_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Status */ +#define IMXDPUV1_CONSTFRAME1_STATUS ((uint32_t)(0x541C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst1_LockUnlock */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK ((uint32_t)(0x5800)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst1_LockStatus */ +#define IMXDPUV1_EXTDST1_LOCKSTATUS ((uint32_t)(0x5804)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst1_StaticControl */ +#define IMXDPUV1_EXTDST1_STATICCONTROL ((uint32_t)(0x5808)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst1_Control */ +#define IMXDPUV1_EXTDST1_CONTROL ((uint32_t)(0x580C)) +#define IMXDPUV1_EXTDST1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_SoftwareKick */ +#define IMXDPUV1_EXTDST1_SOFTWAREKICK ((uint32_t)(0x5810)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_Status */ +#define IMXDPUV1_EXTDST1_STATUS ((uint32_t)(0x5814)) +#define IMXDPUV1_EXTDST1_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_ControlWord */ +#define IMXDPUV1_EXTDST1_CONTROLWORD ((uint32_t)(0x5818)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_CurPixelCnt */ +#define IMXDPUV1_EXTDST1_CURPIXELCNT ((uint32_t)(0x581C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_LastPixelCnt */ +#define IMXDPUV1_EXTDST1_LASTPIXELCNT ((uint32_t)(0x5820)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_PerfCounter */ +#define IMXDPUV1_EXTDST1_PERFCOUNTER ((uint32_t)(0x5824)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_LockUnlock */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0x5C00)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe5_LockStatus */ +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0x5C04)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe5_StaticControl */ +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL ((uint32_t)(0x5C08)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS ((uint32_t)(0x5C0C)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe5_ConstantColor */ +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR ((uint32_t)(0x5C10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe5_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER ((uint32_t)(0x5C14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Start */ +#define IMXDPUV1_CONSTFRAME5_START ((uint32_t)(0x5C18)) +#define IMXDPUV1_CONSTFRAME5_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME5_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Status */ +#define IMXDPUV1_CONSTFRAME5_STATUS ((uint32_t)(0x5C1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst5_LockUnlock */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK ((uint32_t)(0x6000)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst5_LockStatus */ +#define IMXDPUV1_EXTDST5_LOCKSTATUS ((uint32_t)(0x6004)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst5_StaticControl */ +#define IMXDPUV1_EXTDST5_STATICCONTROL ((uint32_t)(0x6008)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst5_Control */ +#define IMXDPUV1_EXTDST5_CONTROL ((uint32_t)(0x600C)) +#define IMXDPUV1_EXTDST5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_SoftwareKick */ +#define IMXDPUV1_EXTDST5_SOFTWAREKICK ((uint32_t)(0x6010)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_Status */ +#define IMXDPUV1_EXTDST5_STATUS ((uint32_t)(0x6014)) +#define IMXDPUV1_EXTDST5_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_ControlWord */ +#define IMXDPUV1_EXTDST5_CONTROLWORD ((uint32_t)(0x6018)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_CurPixelCnt */ +#define IMXDPUV1_EXTDST5_CURPIXELCNT ((uint32_t)(0x601C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_LastPixelCnt */ +#define IMXDPUV1_EXTDST5_LASTPIXELCNT ((uint32_t)(0x6020)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_PerfCounter */ +#define IMXDPUV1_EXTDST5_PERFCOUNTER ((uint32_t)(0x6024)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_LockUnlock */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0x6400)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp2_LockStatus */ +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS ((uint32_t)(0x6404)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_StaticControl */ +#define IMXDPUV1_FETCHWARP2_STATICCONTROL ((uint32_t)(0x6408)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x640C)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0 ((uint32_t)(0x6410)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6414)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6418)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0 ((uint32_t)(0x641C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6420)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0 ((uint32_t)(0x6424)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6428)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x642C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0 ((uint32_t)(0x6430)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0 ((uint32_t)(0x6434)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1 ((uint32_t)(0x6438)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x643C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x6440)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1 ((uint32_t)(0x6444)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1 ((uint32_t)(0x6448)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1 ((uint32_t)(0x644C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1 ((uint32_t)(0x6450)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x6454)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1 ((uint32_t)(0x6458)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1 ((uint32_t)(0x645C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2 ((uint32_t)(0x6460)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x6464)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x6468)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2 ((uint32_t)(0x646C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2 ((uint32_t)(0x6470)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2 ((uint32_t)(0x6474)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2 ((uint32_t)(0x6478)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x647C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2 ((uint32_t)(0x6480)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2 ((uint32_t)(0x6484)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3 ((uint32_t)(0x6488)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x648C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x6490)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3 ((uint32_t)(0x6494)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3 ((uint32_t)(0x6498)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3 ((uint32_t)(0x649C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3 ((uint32_t)(0x64A0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x64A4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3 ((uint32_t)(0x64A8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3 ((uint32_t)(0x64AC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4 ((uint32_t)(0x64B0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x64B4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x64B8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4 ((uint32_t)(0x64BC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4 ((uint32_t)(0x64C0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4 ((uint32_t)(0x64C4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4 ((uint32_t)(0x64C8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x64CC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4 ((uint32_t)(0x64D0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4 ((uint32_t)(0x64D4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5 ((uint32_t)(0x64D8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x64DC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x64E0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5 ((uint32_t)(0x64E4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5 ((uint32_t)(0x64E8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5 ((uint32_t)(0x64EC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5 ((uint32_t)(0x64F0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x64F4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5 ((uint32_t)(0x64F8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5 ((uint32_t)(0x64FC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6 ((uint32_t)(0x6500)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x6504)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x6508)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6 ((uint32_t)(0x650C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6 ((uint32_t)(0x6510)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6 ((uint32_t)(0x6514)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6 ((uint32_t)(0x6518)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x651C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6 ((uint32_t)(0x6520)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6 ((uint32_t)(0x6524)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7 ((uint32_t)(0x6528)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x652C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x6530)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7 ((uint32_t)(0x6534)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7 ((uint32_t)(0x6538)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7 ((uint32_t)(0x653C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7 ((uint32_t)(0x6540)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x6544)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7 ((uint32_t)(0x6548)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7 ((uint32_t)(0x654C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameDimensions */ +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS ((uint32_t)(0x6550)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameResampling */ +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING ((uint32_t)(0x6554)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_WarpControl */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL ((uint32_t)(0x6558)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartX */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTX ((uint32_t)(0x655C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartY */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTY ((uint32_t)(0x6560)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbDelta */ +#define IMXDPUV1_FETCHWARP2_ARBDELTA ((uint32_t)(0x6564)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_FIRPositions */ +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS ((uint32_t)(0x6568)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS ((uint32_t)(0x656C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_Control */ +#define IMXDPUV1_FETCHWARP2_CONTROL ((uint32_t)(0x6570)) +#define IMXDPUV1_FETCHWARP2_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp2_TriggerEnable */ +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE ((uint32_t)(0x6574)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ControlTrigger */ +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER ((uint32_t)(0x6578)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_Start */ +#define IMXDPUV1_FETCHWARP2_START ((uint32_t)(0x657C)) +#define IMXDPUV1_FETCHWARP2_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_FetchType */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE ((uint32_t)(0x6580)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6584)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_Status */ +#define IMXDPUV1_FETCHWARP2_STATUS ((uint32_t)(0x6588)) +#define IMXDPUV1_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp2_HiddenStatus */ +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS ((uint32_t)(0x658C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_LockUnlock */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK ((uint32_t)(0x6800)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco2_LockStatus */ +#define IMXDPUV1_FETCHECO2_LOCKSTATUS ((uint32_t)(0x6804)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_StaticControl */ +#define IMXDPUV1_FETCHECO2_STATICCONTROL ((uint32_t)(0x6808)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x680C)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco2_BaseAddress0 */ +#define IMXDPUV1_FETCHECO2_BASEADDRESS0 ((uint32_t)(0x6810)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6814)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6818)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0 ((uint32_t)(0x681C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6820)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerOffset0 */ +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0 ((uint32_t)(0x6824)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6828)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x682C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ConstantColor0 */ +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0 ((uint32_t)(0x6830)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerProperty0 */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0 ((uint32_t)(0x6834)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameDimensions */ +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS ((uint32_t)(0x6838)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameResampling */ +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING ((uint32_t)(0x683C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_Control */ +#define IMXDPUV1_FETCHECO2_CONTROL ((uint32_t)(0x6840)) +#define IMXDPUV1_FETCHECO2_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco2_ControlTrigger */ +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER ((uint32_t)(0x6844)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_Start */ +#define IMXDPUV1_FETCHECO2_START ((uint32_t)(0x6848)) +#define IMXDPUV1_FETCHECO2_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_FetchType */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE ((uint32_t)(0x684C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6850)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_HiddenStatus */ +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS ((uint32_t)(0x6854)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_LockUnlock */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0x6C00)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode0_LockStatus */ +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0x6C04)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_StaticControl */ +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL ((uint32_t)(0x6C08)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x6C0C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode0_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0 ((uint32_t)(0x6C10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0 ((uint32_t)(0x6C14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0 ((uint32_t)(0x6C18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0 ((uint32_t)(0x6C1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6C20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6C24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0 ((uint32_t)(0x6C28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6C2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0 ((uint32_t)(0x6C30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0 ((uint32_t)(0x6C34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x6C38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0 ((uint32_t)(0x6C3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0 ((uint32_t)(0x6C40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS ((uint32_t)(0x6C44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameResampling */ +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING ((uint32_t)(0x6C48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_DecodeControl */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL ((uint32_t)(0x6C4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH ((uint32_t)(0x6C50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Control */ +#define IMXDPUV1_FETCHDECODE0_CONTROL ((uint32_t)(0x6C54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode0_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER ((uint32_t)(0x6C58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Start */ +#define IMXDPUV1_FETCHDECODE0_START ((uint32_t)(0x6C5C)) +#define IMXDPUV1_FETCHDECODE0_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FetchType */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE ((uint32_t)(0x6C60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode0_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS ((uint32_t)(0x6C64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode0_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE0_READADDRESS0 ((uint32_t)(0x6C68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES ((uint32_t)(0x6C6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_Status */ +#define IMXDPUV1_FETCHDECODE0_STATUS ((uint32_t)(0x6C70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode0_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS ((uint32_t)(0x6C74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_ColorPalette */ +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE ((uint32_t)(0x7000)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_LockUnlock */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK ((uint32_t)(0x7400)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco0_LockStatus */ +#define IMXDPUV1_FETCHECO0_LOCKSTATUS ((uint32_t)(0x7404)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_StaticControl */ +#define IMXDPUV1_FETCHECO0_STATICCONTROL ((uint32_t)(0x7408)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x740C)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco0_BaseAddress0 */ +#define IMXDPUV1_FETCHECO0_BASEADDRESS0 ((uint32_t)(0x7410)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7414)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7418)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0 ((uint32_t)(0x741C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x7420)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerOffset0 */ +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0 ((uint32_t)(0x7424)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0 ((uint32_t)(0x7428)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x742C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ConstantColor0 */ +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0 ((uint32_t)(0x7430)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerProperty0 */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0 ((uint32_t)(0x7434)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameDimensions */ +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS ((uint32_t)(0x7438)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameResampling */ +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING ((uint32_t)(0x743C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_Control */ +#define IMXDPUV1_FETCHECO0_CONTROL ((uint32_t)(0x7440)) +#define IMXDPUV1_FETCHECO0_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco0_ControlTrigger */ +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER ((uint32_t)(0x7444)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_Start */ +#define IMXDPUV1_FETCHECO0_START ((uint32_t)(0x7448)) +#define IMXDPUV1_FETCHECO0_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_FetchType */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE ((uint32_t)(0x744C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES ((uint32_t)(0x7450)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_HiddenStatus */ +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS ((uint32_t)(0x7454)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_LockUnlock */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0x7800)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode1_LockStatus */ +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0x7804)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_StaticControl */ +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL ((uint32_t)(0x7808)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x780C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode1_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0 ((uint32_t)(0x7810)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0 ((uint32_t)(0x7814)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0 ((uint32_t)(0x7818)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0 ((uint32_t)(0x781C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7820)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7824)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0 ((uint32_t)(0x7828)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x782C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0 ((uint32_t)(0x7830)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0 ((uint32_t)(0x7834)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x7838)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0 ((uint32_t)(0x783C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0 ((uint32_t)(0x7840)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS ((uint32_t)(0x7844)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameResampling */ +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING ((uint32_t)(0x7848)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_DecodeControl */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL ((uint32_t)(0x784C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH ((uint32_t)(0x7850)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Control */ +#define IMXDPUV1_FETCHDECODE1_CONTROL ((uint32_t)(0x7854)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode1_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER ((uint32_t)(0x7858)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Start */ +#define IMXDPUV1_FETCHDECODE1_START ((uint32_t)(0x785C)) +#define IMXDPUV1_FETCHDECODE1_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FetchType */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE ((uint32_t)(0x7860)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode1_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS ((uint32_t)(0x7864)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode1_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE1_READADDRESS0 ((uint32_t)(0x7868)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES ((uint32_t)(0x786C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_Status */ +#define IMXDPUV1_FETCHDECODE1_STATUS ((uint32_t)(0x7870)) +#define IMXDPUV1_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode1_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS ((uint32_t)(0x7874)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_ColorPalette */ +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE ((uint32_t)(0x7C00)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_LockUnlock */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK ((uint32_t)(0x8000)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco1_LockStatus */ +#define IMXDPUV1_FETCHECO1_LOCKSTATUS ((uint32_t)(0x8004)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_StaticControl */ +#define IMXDPUV1_FETCHECO1_STATICCONTROL ((uint32_t)(0x8008)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x800C)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco1_BaseAddress0 */ +#define IMXDPUV1_FETCHECO1_BASEADDRESS0 ((uint32_t)(0x8010)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8014)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8018)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0 ((uint32_t)(0x801C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8020)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerOffset0 */ +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0 ((uint32_t)(0x8024)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0 ((uint32_t)(0x8028)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x802C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ConstantColor0 */ +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0 ((uint32_t)(0x8030)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerProperty0 */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0 ((uint32_t)(0x8034)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameDimensions */ +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS ((uint32_t)(0x8038)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameResampling */ +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING ((uint32_t)(0x803C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_Control */ +#define IMXDPUV1_FETCHECO1_CONTROL ((uint32_t)(0x8040)) +#define IMXDPUV1_FETCHECO1_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco1_ControlTrigger */ +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER ((uint32_t)(0x8044)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_Start */ +#define IMXDPUV1_FETCHECO1_START ((uint32_t)(0x8048)) +#define IMXDPUV1_FETCHECO1_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_FetchType */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE ((uint32_t)(0x804C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES ((uint32_t)(0x8050)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_HiddenStatus */ +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS ((uint32_t)(0x8054)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_LockUnlock */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0x8400)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchlayer0_LockStatus */ +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0x8404)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_StaticControl */ +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL ((uint32_t)(0x8408)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferManagement */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x840C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress0 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0 ((uint32_t)(0x8410)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8414)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8418)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0 ((uint32_t)(0x841C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8420)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset0 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0 ((uint32_t)(0x8424)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0 ((uint32_t)(0x8428)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x842C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor0 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0 ((uint32_t)(0x8430)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty0 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0 ((uint32_t)(0x8434)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress1 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1 ((uint32_t)(0x8438)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x843C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x8440)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1 ((uint32_t)(0x8444)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1 ((uint32_t)(0x8448)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset1 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1 ((uint32_t)(0x844C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1 ((uint32_t)(0x8450)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x8454)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor1 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1 ((uint32_t)(0x8458)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty1 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1 ((uint32_t)(0x845C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress2 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2 ((uint32_t)(0x8460)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x8464)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x8468)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2 ((uint32_t)(0x846C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2 ((uint32_t)(0x8470)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset2 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2 ((uint32_t)(0x8474)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2 ((uint32_t)(0x8478)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x847C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor2 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2 ((uint32_t)(0x8480)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty2 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2 ((uint32_t)(0x8484)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress3 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3 ((uint32_t)(0x8488)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x848C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x8490)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3 ((uint32_t)(0x8494)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3 ((uint32_t)(0x8498)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset3 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3 ((uint32_t)(0x849C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3 ((uint32_t)(0x84A0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x84A4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor3 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3 ((uint32_t)(0x84A8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty3 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3 ((uint32_t)(0x84AC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress4 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4 ((uint32_t)(0x84B0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x84B4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x84B8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4 ((uint32_t)(0x84BC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4 ((uint32_t)(0x84C0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset4 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4 ((uint32_t)(0x84C4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4 ((uint32_t)(0x84C8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x84CC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor4 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4 ((uint32_t)(0x84D0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty4 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4 ((uint32_t)(0x84D4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress5 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5 ((uint32_t)(0x84D8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x84DC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x84E0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5 ((uint32_t)(0x84E4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5 ((uint32_t)(0x84E8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset5 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5 ((uint32_t)(0x84EC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5 ((uint32_t)(0x84F0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x84F4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor5 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5 ((uint32_t)(0x84F8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty5 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5 ((uint32_t)(0x84FC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress6 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6 ((uint32_t)(0x8500)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x8504)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x8508)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6 ((uint32_t)(0x850C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6 ((uint32_t)(0x8510)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset6 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6 ((uint32_t)(0x8514)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6 ((uint32_t)(0x8518)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x851C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor6 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6 ((uint32_t)(0x8520)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty6 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6 ((uint32_t)(0x8524)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress7 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7 ((uint32_t)(0x8528)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x852C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x8530)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7 ((uint32_t)(0x8534)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7 ((uint32_t)(0x8538)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset7 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7 ((uint32_t)(0x853C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7 ((uint32_t)(0x8540)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x8544)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor7 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7 ((uint32_t)(0x8548)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty7 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7 ((uint32_t)(0x854C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameDimensions */ +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS ((uint32_t)(0x8550)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameResampling */ +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING ((uint32_t)(0x8554)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_Control */ +#define IMXDPUV1_FETCHLAYER0_CONTROL ((uint32_t)(0x8558)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_SHIFT 17U + +/* Register: IMXDPUV1_fetchlayer0_TriggerEnable */ +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE ((uint32_t)(0x855C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_ControlTrigger */ +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER ((uint32_t)(0x8560)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_Start */ +#define IMXDPUV1_FETCHLAYER0_START ((uint32_t)(0x8564)) +#define IMXDPUV1_FETCHLAYER0_START_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHLAYER0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_FetchType */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE ((uint32_t)(0x8568)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferProperties */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES ((uint32_t)(0x856C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_Status */ +#define IMXDPUV1_FETCHLAYER0_STATUS ((uint32_t)(0x8570)) +#define IMXDPUV1_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchlayer0_HiddenStatus */ +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS ((uint32_t)(0x8574)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_ColorPalette */ +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE ((uint32_t)(0x8800)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_LockUnlock */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK ((uint32_t)(0x8C00)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix4_LockStatus */ +#define IMXDPUV1_MATRIX4_LOCKSTATUS ((uint32_t)(0x8C04)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix4_StaticControl */ +#define IMXDPUV1_MATRIX4_STATICCONTROL ((uint32_t)(0x8C08)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_Control */ +#define IMXDPUV1_MATRIX4_CONTROL ((uint32_t)(0x8C0C)) +#define IMXDPUV1_MATRIX4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix4_Red0 */ +#define IMXDPUV1_MATRIX4_RED0 ((uint32_t)(0x8C10)) +#define IMXDPUV1_MATRIX4_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX4_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Red1 */ +#define IMXDPUV1_MATRIX4_RED1 ((uint32_t)(0x8C14)) +#define IMXDPUV1_MATRIX4_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX4_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green0 */ +#define IMXDPUV1_MATRIX4_GREEN0 ((uint32_t)(0x8C18)) +#define IMXDPUV1_MATRIX4_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX4_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green1 */ +#define IMXDPUV1_MATRIX4_GREEN1 ((uint32_t)(0x8C1C)) +#define IMXDPUV1_MATRIX4_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX4_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue0 */ +#define IMXDPUV1_MATRIX4_BLUE0 ((uint32_t)(0x8C20)) +#define IMXDPUV1_MATRIX4_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX4_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue1 */ +#define IMXDPUV1_MATRIX4_BLUE1 ((uint32_t)(0x8C24)) +#define IMXDPUV1_MATRIX4_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX4_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha0 */ +#define IMXDPUV1_MATRIX4_ALPHA0 ((uint32_t)(0x8C28)) +#define IMXDPUV1_MATRIX4_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha1 */ +#define IMXDPUV1_MATRIX4_ALPHA1 ((uint32_t)(0x8C2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector0 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0 ((uint32_t)(0x8C30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector1 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1 ((uint32_t)(0x8C34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_LastControlWord */ +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD ((uint32_t)(0x8C38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_LockUnlock */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK ((uint32_t)(0x9000)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler4_LockStatus */ +#define IMXDPUV1_HSCALER4_LOCKSTATUS ((uint32_t)(0x9004)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler4_StaticControl */ +#define IMXDPUV1_HSCALER4_STATICCONTROL ((uint32_t)(0x9008)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup1 */ +#define IMXDPUV1_HSCALER4_SETUP1 ((uint32_t)(0x900C)) +#define IMXDPUV1_HSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup2 */ +#define IMXDPUV1_HSCALER4_SETUP2 ((uint32_t)(0x9010)) +#define IMXDPUV1_HSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Control */ +#define IMXDPUV1_HSCALER4_CONTROL ((uint32_t)(0x9014)) +#define IMXDPUV1_HSCALER4_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler4_LockUnlock */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK ((uint32_t)(0x9400)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler4_LockStatus */ +#define IMXDPUV1_VSCALER4_LOCKSTATUS ((uint32_t)(0x9404)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler4_StaticControl */ +#define IMXDPUV1_VSCALER4_STATICCONTROL ((uint32_t)(0x9408)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup1 */ +#define IMXDPUV1_VSCALER4_SETUP1 ((uint32_t)(0x940C)) +#define IMXDPUV1_VSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup2 */ +#define IMXDPUV1_VSCALER4_SETUP2 ((uint32_t)(0x9410)) +#define IMXDPUV1_VSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup3 */ +#define IMXDPUV1_VSCALER4_SETUP3 ((uint32_t)(0x9414)) +#define IMXDPUV1_VSCALER4_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER4_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup4 */ +#define IMXDPUV1_VSCALER4_SETUP4 ((uint32_t)(0x9418)) +#define IMXDPUV1_VSCALER4_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER4_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup5 */ +#define IMXDPUV1_VSCALER4_SETUP5 ((uint32_t)(0x941C)) +#define IMXDPUV1_VSCALER4_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER4_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Control */ +#define IMXDPUV1_VSCALER4_CONTROL ((uint32_t)(0x9420)) +#define IMXDPUV1_VSCALER4_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER4_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LockUnlock */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK ((uint32_t)(0x9800)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix5_LockStatus */ +#define IMXDPUV1_MATRIX5_LOCKSTATUS ((uint32_t)(0x9804)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix5_StaticControl */ +#define IMXDPUV1_MATRIX5_STATICCONTROL ((uint32_t)(0x9808)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix5_Control */ +#define IMXDPUV1_MATRIX5_CONTROL ((uint32_t)(0x980C)) +#define IMXDPUV1_MATRIX5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix5_Red0 */ +#define IMXDPUV1_MATRIX5_RED0 ((uint32_t)(0x9810)) +#define IMXDPUV1_MATRIX5_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX5_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Red1 */ +#define IMXDPUV1_MATRIX5_RED1 ((uint32_t)(0x9814)) +#define IMXDPUV1_MATRIX5_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX5_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green0 */ +#define IMXDPUV1_MATRIX5_GREEN0 ((uint32_t)(0x9818)) +#define IMXDPUV1_MATRIX5_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX5_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green1 */ +#define IMXDPUV1_MATRIX5_GREEN1 ((uint32_t)(0x981C)) +#define IMXDPUV1_MATRIX5_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX5_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue0 */ +#define IMXDPUV1_MATRIX5_BLUE0 ((uint32_t)(0x9820)) +#define IMXDPUV1_MATRIX5_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX5_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue1 */ +#define IMXDPUV1_MATRIX5_BLUE1 ((uint32_t)(0x9824)) +#define IMXDPUV1_MATRIX5_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX5_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha0 */ +#define IMXDPUV1_MATRIX5_ALPHA0 ((uint32_t)(0x9828)) +#define IMXDPUV1_MATRIX5_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha1 */ +#define IMXDPUV1_MATRIX5_ALPHA1 ((uint32_t)(0x982C)) +#define IMXDPUV1_MATRIX5_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector0 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0 ((uint32_t)(0x9830)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector1 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1 ((uint32_t)(0x9834)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LastControlWord */ +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD ((uint32_t)(0x9838)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_LockUnlock */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK ((uint32_t)(0x9C00)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler5_LockStatus */ +#define IMXDPUV1_HSCALER5_LOCKSTATUS ((uint32_t)(0x9C04)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler5_StaticControl */ +#define IMXDPUV1_HSCALER5_STATICCONTROL ((uint32_t)(0x9C08)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup1 */ +#define IMXDPUV1_HSCALER5_SETUP1 ((uint32_t)(0x9C0C)) +#define IMXDPUV1_HSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup2 */ +#define IMXDPUV1_HSCALER5_SETUP2 ((uint32_t)(0x9C10)) +#define IMXDPUV1_HSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Control */ +#define IMXDPUV1_HSCALER5_CONTROL ((uint32_t)(0x9C14)) +#define IMXDPUV1_HSCALER5_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler5_LockUnlock */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK ((uint32_t)(0xA000)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler5_LockStatus */ +#define IMXDPUV1_VSCALER5_LOCKSTATUS ((uint32_t)(0xA004)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler5_StaticControl */ +#define IMXDPUV1_VSCALER5_STATICCONTROL ((uint32_t)(0xA008)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup1 */ +#define IMXDPUV1_VSCALER5_SETUP1 ((uint32_t)(0xA00C)) +#define IMXDPUV1_VSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup2 */ +#define IMXDPUV1_VSCALER5_SETUP2 ((uint32_t)(0xA010)) +#define IMXDPUV1_VSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup3 */ +#define IMXDPUV1_VSCALER5_SETUP3 ((uint32_t)(0xA014)) +#define IMXDPUV1_VSCALER5_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER5_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup4 */ +#define IMXDPUV1_VSCALER5_SETUP4 ((uint32_t)(0xA018)) +#define IMXDPUV1_VSCALER5_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER5_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup5 */ +#define IMXDPUV1_VSCALER5_SETUP5 ((uint32_t)(0xA01C)) +#define IMXDPUV1_VSCALER5_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER5_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Control */ +#define IMXDPUV1_VSCALER5_CONTROL ((uint32_t)(0xA020)) +#define IMXDPUV1_VSCALER5_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER5_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_LockUnlock */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xA400)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend0_LockStatus */ +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xA404)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend0_StaticControl */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL ((uint32_t)(0xA408)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend0_Control */ +#define IMXDPUV1_LAYERBLEND0_CONTROL ((uint32_t)(0xA40C)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend0_BlendControl */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL ((uint32_t)(0xA410)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_Position */ +#define IMXDPUV1_LAYERBLEND0_POSITION ((uint32_t)(0xA414)) +#define IMXDPUV1_LAYERBLEND0_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD ((uint32_t)(0xA418)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend0_SecControlWord */ +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD ((uint32_t)(0xA41C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_LockUnlock */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xA800)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend1_LockStatus */ +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xA804)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend1_StaticControl */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL ((uint32_t)(0xA808)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend1_Control */ +#define IMXDPUV1_LAYERBLEND1_CONTROL ((uint32_t)(0xA80C)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend1_BlendControl */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL ((uint32_t)(0xA810)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_Position */ +#define IMXDPUV1_LAYERBLEND1_POSITION ((uint32_t)(0xA814)) +#define IMXDPUV1_LAYERBLEND1_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD ((uint32_t)(0xA818)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_SecControlWord */ +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD ((uint32_t)(0xA81C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_LockUnlock */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xAC00)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend2_LockStatus */ +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xAC04)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend2_StaticControl */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL ((uint32_t)(0xAC08)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend2_Control */ +#define IMXDPUV1_LAYERBLEND2_CONTROL ((uint32_t)(0xAC0C)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend2_BlendControl */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL ((uint32_t)(0xAC10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_Position */ +#define IMXDPUV1_LAYERBLEND2_POSITION ((uint32_t)(0xAC14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD ((uint32_t)(0xAC18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_SecControlWord */ +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD ((uint32_t)(0xAC1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_LockUnlock */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xB000)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend3_LockStatus */ +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xB004)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend3_StaticControl */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL ((uint32_t)(0xB008)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend3_Control */ +#define IMXDPUV1_LAYERBLEND3_CONTROL ((uint32_t)(0xB00C)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend3_BlendControl */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL ((uint32_t)(0xB010)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_Position */ +#define IMXDPUV1_LAYERBLEND3_POSITION ((uint32_t)(0xB014)) +#define IMXDPUV1_LAYERBLEND3_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD ((uint32_t)(0xB018)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_SecControlWord */ +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD ((uint32_t)(0xB01C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_disengcfg_LockUnlock0 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0 ((uint32_t)(0xB400)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_SHIFT 0U +/* Field Value: LOCKUNLOCK0__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK0__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK0__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK0__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK0__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus0 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0 ((uint32_t)(0xB404)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl0 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0 ((uint32_t)(0xB408)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_SHIFT 0U +/* Field Value: DSPCLKDIVIDE0__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV1 0U +/* Field Value: DSPCLKDIVIDE0__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl0 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0 ((uint32_t)(0xB40C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_SHIFT 0U +/* Field Value: POLHS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW 0U +/* Field Value: POLHS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_SHIFT 1U +/* Field Value: POLVS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW 0U +/* Field Value: POLVS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_SHIFT 2U +/* Field Value: POLEN0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW 0U +/* Field Value: POLEN0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_SHIFT 3U +/* Field Value: PIXINV0__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__NONINV 0U +/* Field Value: PIXINV0__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect0 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0 ((uint32_t)(0xB410)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_SHIFT 0U +/* Field Value: SIG_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__FRAMEGEN 0U +/* Field Value: SIG_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__GAMMACOR 0x1U +/* Field Value: SIG_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__MATRIX 0x2U +/* Field Value: SIG_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_SHIFT 4U +/* Field Value: PATH_SELECT0__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT0__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_SHIFT 8U +/* Field Value: DUMP0_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__MATRIX 0x2U +/* Field Value: DUMP0_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_SHIFT 10U +/* Field Value: DUMP1_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__MATRIX 0x2U +/* Field Value: DUMP1_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__DITHER 0x3U + +/* Register: IMXDPUV1_disengcfg_LockUnlock1 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1 ((uint32_t)(0xB420)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_SHIFT 0U +/* Field Value: LOCKUNLOCK1__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK1__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK1__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK1__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK1__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus1 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1 ((uint32_t)(0xB424)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl1 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1 ((uint32_t)(0xB428)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_SHIFT 0U +/* Field Value: DSPCLKDIVIDE1__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV1 0U +/* Field Value: DSPCLKDIVIDE1__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl1 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1 ((uint32_t)(0xB42C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_SHIFT 0U +/* Field Value: POLHS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW 0U +/* Field Value: POLHS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_SHIFT 1U +/* Field Value: POLVS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW 0U +/* Field Value: POLVS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_SHIFT 2U +/* Field Value: POLEN1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW 0U +/* Field Value: POLEN1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_SHIFT 3U +/* Field Value: PIXINV1__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__NONINV 0U +/* Field Value: PIXINV1__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect1 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1 ((uint32_t)(0xB430)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_SHIFT 0U +/* Field Value: SIG_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__FRAMEGEN 0U +/* Field Value: SIG_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__GAMMACOR 0x1U +/* Field Value: SIG_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__MATRIX 0x2U +/* Field Value: SIG_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_SHIFT 4U +/* Field Value: PATH_SELECT1__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT1__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_SHIFT 8U +/* Field Value: DUMP0_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__MATRIX 0x2U +/* Field Value: DUMP0_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_SHIFT 10U +/* Field Value: DUMP1_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__MATRIX 0x2U +/* Field Value: DUMP1_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__DITHER 0x3U + +/* Register: IMXDPUV1_framegen0_LockUnlock */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK ((uint32_t)(0xB800)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen0_LockStatus */ +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS ((uint32_t)(0xB804)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL ((uint32_t)(0xB808)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen0_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG1 ((uint32_t)(0xB80C)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG2 ((uint32_t)(0xB810)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG1 ((uint32_t)(0xB814)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG2 ((uint32_t)(0xB818)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int0Config */ +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG ((uint32_t)(0xB81C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int1Config */ +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG ((uint32_t)(0xB820)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int2Config */ +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG ((uint32_t)(0xB824)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int3Config */ +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG ((uint32_t)(0xB828)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_PKickConfig */ +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG ((uint32_t)(0xB82C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SKickConfig */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG ((uint32_t)(0xB830)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG ((uint32_t)(0xB834)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1 ((uint32_t)(0xB838)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen0_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR2 ((uint32_t)(0xB83C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR3 ((uint32_t)(0xB840)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR4 ((uint32_t)(0xB844)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR5 ((uint32_t)(0xB848)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR6 ((uint32_t)(0xB84C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgKSDR */ +#define IMXDPUV1_FRAMEGEN0_FGKSDR ((uint32_t)(0xB850)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_PaCfg */ +#define IMXDPUV1_FRAMEGEN0_PACFG ((uint32_t)(0xB854)) +#define IMXDPUV1_FRAMEGEN0_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_SaCfg */ +#define IMXDPUV1_FRAMEGEN0_SACFG ((uint32_t)(0xB858)) +#define IMXDPUV1_FRAMEGEN0_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL ((uint32_t)(0xB85C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC ((uint32_t)(0xB860)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgCCR */ +#define IMXDPUV1_FRAMEGEN0_FGCCR ((uint32_t)(0xB864)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen0_FgEnable */ +#define IMXDPUV1_FRAMEGEN0_FGENABLE ((uint32_t)(0xB868)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSlr */ +#define IMXDPUV1_FRAMEGEN0_FGSLR ((uint32_t)(0xB86C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgEnSts */ +#define IMXDPUV1_FRAMEGEN0_FGENSTS ((uint32_t)(0xB870)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen0_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP ((uint32_t)(0xB874)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen0_FgChStat */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT ((uint32_t)(0xB878)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen0_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR ((uint32_t)(0xB87C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON ((uint32_t)(0xB880)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN ((uint32_t)(0xB884)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX ((uint32_t)(0xB888)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR ((uint32_t)(0xB88C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN0_FGSREPD ((uint32_t)(0xB890)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN0_FGSRFTD ((uint32_t)(0xB894)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_LockUnlock */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK ((uint32_t)(0xBC00)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix0_LockStatus */ +#define IMXDPUV1_MATRIX0_LOCKSTATUS ((uint32_t)(0xBC04)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix0_StaticControl */ +#define IMXDPUV1_MATRIX0_STATICCONTROL ((uint32_t)(0xBC08)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_Control */ +#define IMXDPUV1_MATRIX0_CONTROL ((uint32_t)(0xBC0C)) +#define IMXDPUV1_MATRIX0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix0_Red0 */ +#define IMXDPUV1_MATRIX0_RED0 ((uint32_t)(0xBC10)) +#define IMXDPUV1_MATRIX0_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX0_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Red1 */ +#define IMXDPUV1_MATRIX0_RED1 ((uint32_t)(0xBC14)) +#define IMXDPUV1_MATRIX0_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX0_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green0 */ +#define IMXDPUV1_MATRIX0_GREEN0 ((uint32_t)(0xBC18)) +#define IMXDPUV1_MATRIX0_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX0_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green1 */ +#define IMXDPUV1_MATRIX0_GREEN1 ((uint32_t)(0xBC1C)) +#define IMXDPUV1_MATRIX0_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX0_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue0 */ +#define IMXDPUV1_MATRIX0_BLUE0 ((uint32_t)(0xBC20)) +#define IMXDPUV1_MATRIX0_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX0_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue1 */ +#define IMXDPUV1_MATRIX0_BLUE1 ((uint32_t)(0xBC24)) +#define IMXDPUV1_MATRIX0_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX0_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha0 */ +#define IMXDPUV1_MATRIX0_ALPHA0 ((uint32_t)(0xBC28)) +#define IMXDPUV1_MATRIX0_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha1 */ +#define IMXDPUV1_MATRIX0_ALPHA1 ((uint32_t)(0xBC2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector0 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0 ((uint32_t)(0xBC30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector1 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1 ((uint32_t)(0xBC34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_LastControlWord */ +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD ((uint32_t)(0xBC38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LockUnlock */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK ((uint32_t)(0xC000)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor0_LockStatus */ +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS ((uint32_t)(0xC004)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor0_StaticControl */ +#define IMXDPUV1_GAMMACOR0_STATICCONTROL ((uint32_t)(0xC008)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor0_LutStart */ +#define IMXDPUV1_GAMMACOR0_LUTSTART ((uint32_t)(0xC00C)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_LutDeltas */ +#define IMXDPUV1_GAMMACOR0_LUTDELTAS ((uint32_t)(0xC010)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_Control */ +#define IMXDPUV1_GAMMACOR0_CONTROL ((uint32_t)(0xC014)) +#define IMXDPUV1_GAMMACOR0_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor0_Status */ +#define IMXDPUV1_GAMMACOR0_STATUS ((uint32_t)(0xC018)) +#define IMXDPUV1_GAMMACOR0_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LastControlWord */ +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD ((uint32_t)(0xC01C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither0_LockUnlock */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK ((uint32_t)(0xC400)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither0_LockStatus */ +#define IMXDPUV1_DITHER0_LOCKSTATUS ((uint32_t)(0xC404)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither0_Control */ +#define IMXDPUV1_DITHER0_CONTROL ((uint32_t)(0xC408)) +#define IMXDPUV1_DITHER0_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither0_DitherControl */ +#define IMXDPUV1_DITHER0_DITHERCONTROL ((uint32_t)(0xC40C)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither0_Release */ +#define IMXDPUV1_DITHER0_RELEASE ((uint32_t)(0xC410)) +#define IMXDPUV1_DITHER0_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER0_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCnts */ +#define IMXDPUV1_TCON0_SSQCNTS ((uint32_t)(0xC800)) +#define IMXDPUV1_TCON0_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_LockUnlock */ +#define IMXDPUV1_TCON0_LOCKUNLOCK ((uint32_t)(0xCC00)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon0_LockStatus */ +#define IMXDPUV1_TCON0_LOCKSTATUS ((uint32_t)(0xCC04)) +#define IMXDPUV1_TCON0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCycle */ +#define IMXDPUV1_TCON0_SSQCYCLE ((uint32_t)(0xCC08)) +#define IMXDPUV1_TCON0_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SWreset */ +#define IMXDPUV1_TCON0_SWRESET ((uint32_t)(0xCC0C)) +#define IMXDPUV1_TCON0_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON0_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON0_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON0_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_TCON_CTRL */ +#define IMXDPUV1_TCON0_TCON_CTRL ((uint32_t)(0xCC10)) +#define IMXDPUV1_TCON0_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_RSDSInvCtrl */ +#define IMXDPUV1_TCON0_RSDSINVCTRL ((uint32_t)(0xCC14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0 */ +#define IMXDPUV1_TCON0_MAPBIT3_0 ((uint32_t)(0xCC18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4 */ +#define IMXDPUV1_TCON0_MAPBIT7_4 ((uint32_t)(0xCC1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8 */ +#define IMXDPUV1_TCON0_MAPBIT11_8 ((uint32_t)(0xCC20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12 */ +#define IMXDPUV1_TCON0_MAPBIT15_12 ((uint32_t)(0xCC24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16 */ +#define IMXDPUV1_TCON0_MAPBIT19_16 ((uint32_t)(0xCC28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20 */ +#define IMXDPUV1_TCON0_MAPBIT23_20 ((uint32_t)(0xCC2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24 */ +#define IMXDPUV1_TCON0_MAPBIT27_24 ((uint32_t)(0xCC30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28 */ +#define IMXDPUV1_TCON0_MAPBIT31_28 ((uint32_t)(0xCC34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32 */ +#define IMXDPUV1_TCON0_MAPBIT34_32 ((uint32_t)(0xCC38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0_Dual */ +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL ((uint32_t)(0xCC3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4_Dual */ +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL ((uint32_t)(0xCC40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8_Dual */ +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL ((uint32_t)(0xCC44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12_Dual */ +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL ((uint32_t)(0xCC48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16_Dual */ +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL ((uint32_t)(0xCC4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20_Dual */ +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL ((uint32_t)(0xCC50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24_Dual */ +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL ((uint32_t)(0xCC54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28_Dual */ +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL ((uint32_t)(0xCC58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32_Dual */ +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL ((uint32_t)(0xCC5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_SPG0PosOn */ +#define IMXDPUV1_TCON0_SPG0POSON ((uint32_t)(0xCC60)) +#define IMXDPUV1_TCON0_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON0_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON0_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOn */ +#define IMXDPUV1_TCON0_SPG0MASKON ((uint32_t)(0xCC64)) +#define IMXDPUV1_TCON0_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG0PosOff */ +#define IMXDPUV1_TCON0_SPG0POSOFF ((uint32_t)(0xCC68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOff */ +#define IMXDPUV1_TCON0_SPG0MASKOFF ((uint32_t)(0xCC6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOn */ +#define IMXDPUV1_TCON0_SPG1POSON ((uint32_t)(0xCC70)) +#define IMXDPUV1_TCON0_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON0_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON0_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOn */ +#define IMXDPUV1_TCON0_SPG1MASKON ((uint32_t)(0xCC74)) +#define IMXDPUV1_TCON0_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOff */ +#define IMXDPUV1_TCON0_SPG1POSOFF ((uint32_t)(0xCC78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOff */ +#define IMXDPUV1_TCON0_SPG1MASKOFF ((uint32_t)(0xCC7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOn */ +#define IMXDPUV1_TCON0_SPG2POSON ((uint32_t)(0xCC80)) +#define IMXDPUV1_TCON0_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON0_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOn */ +#define IMXDPUV1_TCON0_SPG2MASKON ((uint32_t)(0xCC84)) +#define IMXDPUV1_TCON0_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOff */ +#define IMXDPUV1_TCON0_SPG2POSOFF ((uint32_t)(0xCC88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOff */ +#define IMXDPUV1_TCON0_SPG2MASKOFF ((uint32_t)(0xCC8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOn */ +#define IMXDPUV1_TCON0_SPG3POSON ((uint32_t)(0xCC90)) +#define IMXDPUV1_TCON0_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON0_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOn */ +#define IMXDPUV1_TCON0_SPG3MASKON ((uint32_t)(0xCC94)) +#define IMXDPUV1_TCON0_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOff */ +#define IMXDPUV1_TCON0_SPG3POSOFF ((uint32_t)(0xCC98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOff */ +#define IMXDPUV1_TCON0_SPG3MASKOFF ((uint32_t)(0xCC9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOn */ +#define IMXDPUV1_TCON0_SPG4POSON ((uint32_t)(0xCCA0)) +#define IMXDPUV1_TCON0_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON0_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOn */ +#define IMXDPUV1_TCON0_SPG4MASKON ((uint32_t)(0xCCA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOff */ +#define IMXDPUV1_TCON0_SPG4POSOFF ((uint32_t)(0xCCA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOff */ +#define IMXDPUV1_TCON0_SPG4MASKOFF ((uint32_t)(0xCCAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOn */ +#define IMXDPUV1_TCON0_SPG5POSON ((uint32_t)(0xCCB0)) +#define IMXDPUV1_TCON0_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON0_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOn */ +#define IMXDPUV1_TCON0_SPG5MASKON ((uint32_t)(0xCCB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOff */ +#define IMXDPUV1_TCON0_SPG5POSOFF ((uint32_t)(0xCCB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOff */ +#define IMXDPUV1_TCON0_SPG5MASKOFF ((uint32_t)(0xCCBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOn */ +#define IMXDPUV1_TCON0_SPG6POSON ((uint32_t)(0xCCC0)) +#define IMXDPUV1_TCON0_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON0_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOn */ +#define IMXDPUV1_TCON0_SPG6MASKON ((uint32_t)(0xCCC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOff */ +#define IMXDPUV1_TCON0_SPG6POSOFF ((uint32_t)(0xCCC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOff */ +#define IMXDPUV1_TCON0_SPG6MASKOFF ((uint32_t)(0xCCCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOn */ +#define IMXDPUV1_TCON0_SPG7POSON ((uint32_t)(0xCCD0)) +#define IMXDPUV1_TCON0_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON0_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOn */ +#define IMXDPUV1_TCON0_SPG7MASKON ((uint32_t)(0xCCD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOff */ +#define IMXDPUV1_TCON0_SPG7POSOFF ((uint32_t)(0xCCD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOff */ +#define IMXDPUV1_TCON0_SPG7MASKOFF ((uint32_t)(0xCCDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOn */ +#define IMXDPUV1_TCON0_SPG8POSON ((uint32_t)(0xCCE0)) +#define IMXDPUV1_TCON0_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON0_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOn */ +#define IMXDPUV1_TCON0_SPG8MASKON ((uint32_t)(0xCCE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOff */ +#define IMXDPUV1_TCON0_SPG8POSOFF ((uint32_t)(0xCCE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOff */ +#define IMXDPUV1_TCON0_SPG8MASKOFF ((uint32_t)(0xCCEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOn */ +#define IMXDPUV1_TCON0_SPG9POSON ((uint32_t)(0xCCF0)) +#define IMXDPUV1_TCON0_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON0_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOn */ +#define IMXDPUV1_TCON0_SPG9MASKON ((uint32_t)(0xCCF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOff */ +#define IMXDPUV1_TCON0_SPG9POSOFF ((uint32_t)(0xCCF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOff */ +#define IMXDPUV1_TCON0_SPG9MASKOFF ((uint32_t)(0xCCFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOn */ +#define IMXDPUV1_TCON0_SPG10POSON ((uint32_t)(0xCD00)) +#define IMXDPUV1_TCON0_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON0_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOn */ +#define IMXDPUV1_TCON0_SPG10MASKON ((uint32_t)(0xCD04)) +#define IMXDPUV1_TCON0_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOff */ +#define IMXDPUV1_TCON0_SPG10POSOFF ((uint32_t)(0xCD08)) +#define IMXDPUV1_TCON0_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOff */ +#define IMXDPUV1_TCON0_SPG10MASKOFF ((uint32_t)(0xCD0C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOn */ +#define IMXDPUV1_TCON0_SPG11POSON ((uint32_t)(0xCD10)) +#define IMXDPUV1_TCON0_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON0_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOn */ +#define IMXDPUV1_TCON0_SPG11MASKON ((uint32_t)(0xCD14)) +#define IMXDPUV1_TCON0_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOff */ +#define IMXDPUV1_TCON0_SPG11POSOFF ((uint32_t)(0xCD18)) +#define IMXDPUV1_TCON0_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOff */ +#define IMXDPUV1_TCON0_SPG11MASKOFF ((uint32_t)(0xCD1C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx0Sigs */ +#define IMXDPUV1_TCON0_SMX0SIGS ((uint32_t)(0xCD20)) +#define IMXDPUV1_TCON0_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx0FctTable */ +#define IMXDPUV1_TCON0_SMX0FCTTABLE ((uint32_t)(0xCD24)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx1Sigs */ +#define IMXDPUV1_TCON0_SMX1SIGS ((uint32_t)(0xCD28)) +#define IMXDPUV1_TCON0_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx1FctTable */ +#define IMXDPUV1_TCON0_SMX1FCTTABLE ((uint32_t)(0xCD2C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx2Sigs */ +#define IMXDPUV1_TCON0_SMX2SIGS ((uint32_t)(0xCD30)) +#define IMXDPUV1_TCON0_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx2FctTable */ +#define IMXDPUV1_TCON0_SMX2FCTTABLE ((uint32_t)(0xCD34)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx3Sigs */ +#define IMXDPUV1_TCON0_SMX3SIGS ((uint32_t)(0xCD38)) +#define IMXDPUV1_TCON0_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx3FctTable */ +#define IMXDPUV1_TCON0_SMX3FCTTABLE ((uint32_t)(0xCD3C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx4Sigs */ +#define IMXDPUV1_TCON0_SMX4SIGS ((uint32_t)(0xCD40)) +#define IMXDPUV1_TCON0_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx4FctTable */ +#define IMXDPUV1_TCON0_SMX4FCTTABLE ((uint32_t)(0xCD44)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx5Sigs */ +#define IMXDPUV1_TCON0_SMX5SIGS ((uint32_t)(0xCD48)) +#define IMXDPUV1_TCON0_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx5FctTable */ +#define IMXDPUV1_TCON0_SMX5FCTTABLE ((uint32_t)(0xCD4C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx6Sigs */ +#define IMXDPUV1_TCON0_SMX6SIGS ((uint32_t)(0xCD50)) +#define IMXDPUV1_TCON0_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx6FctTable */ +#define IMXDPUV1_TCON0_SMX6FCTTABLE ((uint32_t)(0xCD54)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx7Sigs */ +#define IMXDPUV1_TCON0_SMX7SIGS ((uint32_t)(0xCD58)) +#define IMXDPUV1_TCON0_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx7FctTable */ +#define IMXDPUV1_TCON0_SMX7FCTTABLE ((uint32_t)(0xCD5C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx8Sigs */ +#define IMXDPUV1_TCON0_SMX8SIGS ((uint32_t)(0xCD60)) +#define IMXDPUV1_TCON0_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx8FctTable */ +#define IMXDPUV1_TCON0_SMX8FCTTABLE ((uint32_t)(0xCD64)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx9Sigs */ +#define IMXDPUV1_TCON0_SMX9SIGS ((uint32_t)(0xCD68)) +#define IMXDPUV1_TCON0_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx9FctTable */ +#define IMXDPUV1_TCON0_SMX9FCTTABLE ((uint32_t)(0xCD6C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx10Sigs */ +#define IMXDPUV1_TCON0_SMX10SIGS ((uint32_t)(0xCD70)) +#define IMXDPUV1_TCON0_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx10FctTable */ +#define IMXDPUV1_TCON0_SMX10FCTTABLE ((uint32_t)(0xCD74)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx11Sigs */ +#define IMXDPUV1_TCON0_SMX11SIGS ((uint32_t)(0xCD78)) +#define IMXDPUV1_TCON0_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx11FctTable */ +#define IMXDPUV1_TCON0_SMX11FCTTABLE ((uint32_t)(0xCD7C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW ((uint32_t)(0xCD80)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Dual_Debug */ +#define IMXDPUV1_TCON0_DUAL_DEBUG ((uint32_t)(0xCD84)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig0_LockUnlock */ +#define IMXDPUV1_SIG0_LOCKUNLOCK ((uint32_t)(0xD000)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig0_LockStatus */ +#define IMXDPUV1_SIG0_LOCKSTATUS ((uint32_t)(0xD004)) +#define IMXDPUV1_SIG0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig0_StaticControl */ +#define IMXDPUV1_SIG0_STATICCONTROL ((uint32_t)(0xD008)) +#define IMXDPUV1_SIG0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig0_PanicColor */ +#define IMXDPUV1_SIG0_PANICCOLOR ((uint32_t)(0xD00C)) +#define IMXDPUV1_SIG0_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig0_EvalControl0 */ +#define IMXDPUV1_SIG0_EVALCONTROL0 ((uint32_t)(0xD010)) +#define IMXDPUV1_SIG0_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft0 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT0 ((uint32_t)(0xD014)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight0 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0 ((uint32_t)(0xD018)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef0 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF0 ((uint32_t)(0xD01C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF0 ((uint32_t)(0xD020)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0 ((uint32_t)(0xD024)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed0 */ +#define IMXDPUV1_SIG0_SIGCRCRED0 ((uint32_t)(0xD028)) +#define IMXDPUV1_SIG0_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen0 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN0 ((uint32_t)(0xD02C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE0 ((uint32_t)(0xD030)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl1 */ +#define IMXDPUV1_SIG0_EVALCONTROL1 ((uint32_t)(0xD034)) +#define IMXDPUV1_SIG0_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft1 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT1 ((uint32_t)(0xD038)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight1 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1 ((uint32_t)(0xD03C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef1 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF1 ((uint32_t)(0xD040)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF1 ((uint32_t)(0xD044)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1 ((uint32_t)(0xD048)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed1 */ +#define IMXDPUV1_SIG0_SIGCRCRED1 ((uint32_t)(0xD04C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen1 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN1 ((uint32_t)(0xD050)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE1 ((uint32_t)(0xD054)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl2 */ +#define IMXDPUV1_SIG0_EVALCONTROL2 ((uint32_t)(0xD058)) +#define IMXDPUV1_SIG0_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft2 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT2 ((uint32_t)(0xD05C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight2 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2 ((uint32_t)(0xD060)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef2 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF2 ((uint32_t)(0xD064)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF2 ((uint32_t)(0xD068)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2 ((uint32_t)(0xD06C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed2 */ +#define IMXDPUV1_SIG0_SIGCRCRED2 ((uint32_t)(0xD070)) +#define IMXDPUV1_SIG0_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen2 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN2 ((uint32_t)(0xD074)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE2 ((uint32_t)(0xD078)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl3 */ +#define IMXDPUV1_SIG0_EVALCONTROL3 ((uint32_t)(0xD07C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft3 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT3 ((uint32_t)(0xD080)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight3 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3 ((uint32_t)(0xD084)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef3 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF3 ((uint32_t)(0xD088)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF3 ((uint32_t)(0xD08C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3 ((uint32_t)(0xD090)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed3 */ +#define IMXDPUV1_SIG0_SIGCRCRED3 ((uint32_t)(0xD094)) +#define IMXDPUV1_SIG0_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen3 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN3 ((uint32_t)(0xD098)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE3 ((uint32_t)(0xD09C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl4 */ +#define IMXDPUV1_SIG0_EVALCONTROL4 ((uint32_t)(0xD0A0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft4 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT4 ((uint32_t)(0xD0A4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight4 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4 ((uint32_t)(0xD0A8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef4 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF4 ((uint32_t)(0xD0AC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF4 ((uint32_t)(0xD0B0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4 ((uint32_t)(0xD0B4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed4 */ +#define IMXDPUV1_SIG0_SIGCRCRED4 ((uint32_t)(0xD0B8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen4 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN4 ((uint32_t)(0xD0BC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE4 ((uint32_t)(0xD0C0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl5 */ +#define IMXDPUV1_SIG0_EVALCONTROL5 ((uint32_t)(0xD0C4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft5 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT5 ((uint32_t)(0xD0C8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight5 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5 ((uint32_t)(0xD0CC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef5 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF5 ((uint32_t)(0xD0D0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF5 ((uint32_t)(0xD0D4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5 ((uint32_t)(0xD0D8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed5 */ +#define IMXDPUV1_SIG0_SIGCRCRED5 ((uint32_t)(0xD0DC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen5 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN5 ((uint32_t)(0xD0E0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE5 ((uint32_t)(0xD0E4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl6 */ +#define IMXDPUV1_SIG0_EVALCONTROL6 ((uint32_t)(0xD0E8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft6 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT6 ((uint32_t)(0xD0EC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight6 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6 ((uint32_t)(0xD0F0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef6 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF6 ((uint32_t)(0xD0F4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF6 ((uint32_t)(0xD0F8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6 ((uint32_t)(0xD0FC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed6 */ +#define IMXDPUV1_SIG0_SIGCRCRED6 ((uint32_t)(0xD100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen6 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN6 ((uint32_t)(0xD104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE6 ((uint32_t)(0xD108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl7 */ +#define IMXDPUV1_SIG0_EVALCONTROL7 ((uint32_t)(0xD10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft7 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT7 ((uint32_t)(0xD110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight7 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7 ((uint32_t)(0xD114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef7 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF7 ((uint32_t)(0xD118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF7 ((uint32_t)(0xD11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7 ((uint32_t)(0xD120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed7 */ +#define IMXDPUV1_SIG0_SIGCRCRED7 ((uint32_t)(0xD124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen7 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN7 ((uint32_t)(0xD128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE7 ((uint32_t)(0xD12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ShadowLoad */ +#define IMXDPUV1_SIG0_SHADOWLOAD ((uint32_t)(0xD130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ContinuousMode */ +#define IMXDPUV1_SIG0_CONTINUOUSMODE ((uint32_t)(0xD134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SoftwareKick */ +#define IMXDPUV1_SIG0_SOFTWAREKICK ((uint32_t)(0xD138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig0_Status */ +#define IMXDPUV1_SIG0_STATUS ((uint32_t)(0xD13C)) +#define IMXDPUV1_SIG0_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG0_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_framegen1_LockUnlock */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK ((uint32_t)(0xD400)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen1_LockStatus */ +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS ((uint32_t)(0xD404)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL ((uint32_t)(0xD408)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen1_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG1 ((uint32_t)(0xD40C)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG2 ((uint32_t)(0xD410)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG1 ((uint32_t)(0xD414)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG2 ((uint32_t)(0xD418)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int0Config */ +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG ((uint32_t)(0xD41C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int1Config */ +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG ((uint32_t)(0xD420)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int2Config */ +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG ((uint32_t)(0xD424)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int3Config */ +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG ((uint32_t)(0xD428)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_PKickConfig */ +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG ((uint32_t)(0xD42C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SKickConfig */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG ((uint32_t)(0xD430)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG ((uint32_t)(0xD434)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1 ((uint32_t)(0xD438)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen1_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR2 ((uint32_t)(0xD43C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR3 ((uint32_t)(0xD440)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR4 ((uint32_t)(0xD444)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR5 ((uint32_t)(0xD448)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR6 ((uint32_t)(0xD44C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgKSDR */ +#define IMXDPUV1_FRAMEGEN1_FGKSDR ((uint32_t)(0xD450)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_PaCfg */ +#define IMXDPUV1_FRAMEGEN1_PACFG ((uint32_t)(0xD454)) +#define IMXDPUV1_FRAMEGEN1_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_SaCfg */ +#define IMXDPUV1_FRAMEGEN1_SACFG ((uint32_t)(0xD458)) +#define IMXDPUV1_FRAMEGEN1_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL ((uint32_t)(0xD45C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC ((uint32_t)(0xD460)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgCCR */ +#define IMXDPUV1_FRAMEGEN1_FGCCR ((uint32_t)(0xD464)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen1_FgEnable */ +#define IMXDPUV1_FRAMEGEN1_FGENABLE ((uint32_t)(0xD468)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSlr */ +#define IMXDPUV1_FRAMEGEN1_FGSLR ((uint32_t)(0xD46C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgEnSts */ +#define IMXDPUV1_FRAMEGEN1_FGENSTS ((uint32_t)(0xD470)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen1_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP ((uint32_t)(0xD474)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen1_FgChStat */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT ((uint32_t)(0xD478)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen1_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR ((uint32_t)(0xD47C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON ((uint32_t)(0xD480)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN ((uint32_t)(0xD484)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX ((uint32_t)(0xD488)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR ((uint32_t)(0xD48C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN1_FGSREPD ((uint32_t)(0xD490)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN1_FGSRFTD ((uint32_t)(0xD494)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_LockUnlock */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK ((uint32_t)(0xD800)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix1_LockStatus */ +#define IMXDPUV1_MATRIX1_LOCKSTATUS ((uint32_t)(0xD804)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix1_StaticControl */ +#define IMXDPUV1_MATRIX1_STATICCONTROL ((uint32_t)(0xD808)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_Control */ +#define IMXDPUV1_MATRIX1_CONTROL ((uint32_t)(0xD80C)) +#define IMXDPUV1_MATRIX1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix1_Red0 */ +#define IMXDPUV1_MATRIX1_RED0 ((uint32_t)(0xD810)) +#define IMXDPUV1_MATRIX1_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX1_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Red1 */ +#define IMXDPUV1_MATRIX1_RED1 ((uint32_t)(0xD814)) +#define IMXDPUV1_MATRIX1_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX1_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green0 */ +#define IMXDPUV1_MATRIX1_GREEN0 ((uint32_t)(0xD818)) +#define IMXDPUV1_MATRIX1_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX1_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green1 */ +#define IMXDPUV1_MATRIX1_GREEN1 ((uint32_t)(0xD81C)) +#define IMXDPUV1_MATRIX1_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX1_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue0 */ +#define IMXDPUV1_MATRIX1_BLUE0 ((uint32_t)(0xD820)) +#define IMXDPUV1_MATRIX1_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX1_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue1 */ +#define IMXDPUV1_MATRIX1_BLUE1 ((uint32_t)(0xD824)) +#define IMXDPUV1_MATRIX1_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX1_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha0 */ +#define IMXDPUV1_MATRIX1_ALPHA0 ((uint32_t)(0xD828)) +#define IMXDPUV1_MATRIX1_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha1 */ +#define IMXDPUV1_MATRIX1_ALPHA1 ((uint32_t)(0xD82C)) +#define IMXDPUV1_MATRIX1_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector0 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0 ((uint32_t)(0xD830)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector1 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1 ((uint32_t)(0xD834)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_LastControlWord */ +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD ((uint32_t)(0xD838)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LockUnlock */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK ((uint32_t)(0xDC00)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor1_LockStatus */ +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS ((uint32_t)(0xDC04)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor1_StaticControl */ +#define IMXDPUV1_GAMMACOR1_STATICCONTROL ((uint32_t)(0xDC08)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor1_LutStart */ +#define IMXDPUV1_GAMMACOR1_LUTSTART ((uint32_t)(0xDC0C)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_LutDeltas */ +#define IMXDPUV1_GAMMACOR1_LUTDELTAS ((uint32_t)(0xDC10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_Control */ +#define IMXDPUV1_GAMMACOR1_CONTROL ((uint32_t)(0xDC14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor1_Status */ +#define IMXDPUV1_GAMMACOR1_STATUS ((uint32_t)(0xDC18)) +#define IMXDPUV1_GAMMACOR1_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LastControlWord */ +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD ((uint32_t)(0xDC1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither1_LockUnlock */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK ((uint32_t)(0xE000)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither1_LockStatus */ +#define IMXDPUV1_DITHER1_LOCKSTATUS ((uint32_t)(0xE004)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither1_Control */ +#define IMXDPUV1_DITHER1_CONTROL ((uint32_t)(0xE008)) +#define IMXDPUV1_DITHER1_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither1_DitherControl */ +#define IMXDPUV1_DITHER1_DITHERCONTROL ((uint32_t)(0xE00C)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither1_Release */ +#define IMXDPUV1_DITHER1_RELEASE ((uint32_t)(0xE010)) +#define IMXDPUV1_DITHER1_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER1_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCnts */ +#define IMXDPUV1_TCON1_SSQCNTS ((uint32_t)(0xE400)) +#define IMXDPUV1_TCON1_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_LockUnlock */ +#define IMXDPUV1_TCON1_LOCKUNLOCK ((uint32_t)(0xE800)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon1_LockStatus */ +#define IMXDPUV1_TCON1_LOCKSTATUS ((uint32_t)(0xE804)) +#define IMXDPUV1_TCON1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCycle */ +#define IMXDPUV1_TCON1_SSQCYCLE ((uint32_t)(0xE808)) +#define IMXDPUV1_TCON1_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SWreset */ +#define IMXDPUV1_TCON1_SWRESET ((uint32_t)(0xE80C)) +#define IMXDPUV1_TCON1_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON1_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON1_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON1_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_TCON_CTRL */ +#define IMXDPUV1_TCON1_TCON_CTRL ((uint32_t)(0xE810)) +#define IMXDPUV1_TCON1_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_RSDSInvCtrl */ +#define IMXDPUV1_TCON1_RSDSINVCTRL ((uint32_t)(0xE814)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0 */ +#define IMXDPUV1_TCON1_MAPBIT3_0 ((uint32_t)(0xE818)) +#define IMXDPUV1_TCON1_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4 */ +#define IMXDPUV1_TCON1_MAPBIT7_4 ((uint32_t)(0xE81C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8 */ +#define IMXDPUV1_TCON1_MAPBIT11_8 ((uint32_t)(0xE820)) +#define IMXDPUV1_TCON1_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12 */ +#define IMXDPUV1_TCON1_MAPBIT15_12 ((uint32_t)(0xE824)) +#define IMXDPUV1_TCON1_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16 */ +#define IMXDPUV1_TCON1_MAPBIT19_16 ((uint32_t)(0xE828)) +#define IMXDPUV1_TCON1_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20 */ +#define IMXDPUV1_TCON1_MAPBIT23_20 ((uint32_t)(0xE82C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24 */ +#define IMXDPUV1_TCON1_MAPBIT27_24 ((uint32_t)(0xE830)) +#define IMXDPUV1_TCON1_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28 */ +#define IMXDPUV1_TCON1_MAPBIT31_28 ((uint32_t)(0xE834)) +#define IMXDPUV1_TCON1_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32 */ +#define IMXDPUV1_TCON1_MAPBIT34_32 ((uint32_t)(0xE838)) +#define IMXDPUV1_TCON1_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0_Dual */ +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL ((uint32_t)(0xE83C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4_Dual */ +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL ((uint32_t)(0xE840)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8_Dual */ +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL ((uint32_t)(0xE844)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12_Dual */ +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL ((uint32_t)(0xE848)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16_Dual */ +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL ((uint32_t)(0xE84C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20_Dual */ +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL ((uint32_t)(0xE850)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24_Dual */ +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL ((uint32_t)(0xE854)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28_Dual */ +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL ((uint32_t)(0xE858)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32_Dual */ +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL ((uint32_t)(0xE85C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_SPG0PosOn */ +#define IMXDPUV1_TCON1_SPG0POSON ((uint32_t)(0xE860)) +#define IMXDPUV1_TCON1_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON1_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON1_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOn */ +#define IMXDPUV1_TCON1_SPG0MASKON ((uint32_t)(0xE864)) +#define IMXDPUV1_TCON1_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG0PosOff */ +#define IMXDPUV1_TCON1_SPG0POSOFF ((uint32_t)(0xE868)) +#define IMXDPUV1_TCON1_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOff */ +#define IMXDPUV1_TCON1_SPG0MASKOFF ((uint32_t)(0xE86C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOn */ +#define IMXDPUV1_TCON1_SPG1POSON ((uint32_t)(0xE870)) +#define IMXDPUV1_TCON1_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON1_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON1_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOn */ +#define IMXDPUV1_TCON1_SPG1MASKON ((uint32_t)(0xE874)) +#define IMXDPUV1_TCON1_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOff */ +#define IMXDPUV1_TCON1_SPG1POSOFF ((uint32_t)(0xE878)) +#define IMXDPUV1_TCON1_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOff */ +#define IMXDPUV1_TCON1_SPG1MASKOFF ((uint32_t)(0xE87C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOn */ +#define IMXDPUV1_TCON1_SPG2POSON ((uint32_t)(0xE880)) +#define IMXDPUV1_TCON1_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON1_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOn */ +#define IMXDPUV1_TCON1_SPG2MASKON ((uint32_t)(0xE884)) +#define IMXDPUV1_TCON1_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOff */ +#define IMXDPUV1_TCON1_SPG2POSOFF ((uint32_t)(0xE888)) +#define IMXDPUV1_TCON1_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOff */ +#define IMXDPUV1_TCON1_SPG2MASKOFF ((uint32_t)(0xE88C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOn */ +#define IMXDPUV1_TCON1_SPG3POSON ((uint32_t)(0xE890)) +#define IMXDPUV1_TCON1_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON1_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOn */ +#define IMXDPUV1_TCON1_SPG3MASKON ((uint32_t)(0xE894)) +#define IMXDPUV1_TCON1_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOff */ +#define IMXDPUV1_TCON1_SPG3POSOFF ((uint32_t)(0xE898)) +#define IMXDPUV1_TCON1_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOff */ +#define IMXDPUV1_TCON1_SPG3MASKOFF ((uint32_t)(0xE89C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOn */ +#define IMXDPUV1_TCON1_SPG4POSON ((uint32_t)(0xE8A0)) +#define IMXDPUV1_TCON1_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON1_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOn */ +#define IMXDPUV1_TCON1_SPG4MASKON ((uint32_t)(0xE8A4)) +#define IMXDPUV1_TCON1_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOff */ +#define IMXDPUV1_TCON1_SPG4POSOFF ((uint32_t)(0xE8A8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOff */ +#define IMXDPUV1_TCON1_SPG4MASKOFF ((uint32_t)(0xE8AC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOn */ +#define IMXDPUV1_TCON1_SPG5POSON ((uint32_t)(0xE8B0)) +#define IMXDPUV1_TCON1_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON1_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOn */ +#define IMXDPUV1_TCON1_SPG5MASKON ((uint32_t)(0xE8B4)) +#define IMXDPUV1_TCON1_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOff */ +#define IMXDPUV1_TCON1_SPG5POSOFF ((uint32_t)(0xE8B8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOff */ +#define IMXDPUV1_TCON1_SPG5MASKOFF ((uint32_t)(0xE8BC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOn */ +#define IMXDPUV1_TCON1_SPG6POSON ((uint32_t)(0xE8C0)) +#define IMXDPUV1_TCON1_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON1_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOn */ +#define IMXDPUV1_TCON1_SPG6MASKON ((uint32_t)(0xE8C4)) +#define IMXDPUV1_TCON1_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOff */ +#define IMXDPUV1_TCON1_SPG6POSOFF ((uint32_t)(0xE8C8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOff */ +#define IMXDPUV1_TCON1_SPG6MASKOFF ((uint32_t)(0xE8CC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOn */ +#define IMXDPUV1_TCON1_SPG7POSON ((uint32_t)(0xE8D0)) +#define IMXDPUV1_TCON1_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON1_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOn */ +#define IMXDPUV1_TCON1_SPG7MASKON ((uint32_t)(0xE8D4)) +#define IMXDPUV1_TCON1_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOff */ +#define IMXDPUV1_TCON1_SPG7POSOFF ((uint32_t)(0xE8D8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOff */ +#define IMXDPUV1_TCON1_SPG7MASKOFF ((uint32_t)(0xE8DC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOn */ +#define IMXDPUV1_TCON1_SPG8POSON ((uint32_t)(0xE8E0)) +#define IMXDPUV1_TCON1_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON1_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOn */ +#define IMXDPUV1_TCON1_SPG8MASKON ((uint32_t)(0xE8E4)) +#define IMXDPUV1_TCON1_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOff */ +#define IMXDPUV1_TCON1_SPG8POSOFF ((uint32_t)(0xE8E8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOff */ +#define IMXDPUV1_TCON1_SPG8MASKOFF ((uint32_t)(0xE8EC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOn */ +#define IMXDPUV1_TCON1_SPG9POSON ((uint32_t)(0xE8F0)) +#define IMXDPUV1_TCON1_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON1_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOn */ +#define IMXDPUV1_TCON1_SPG9MASKON ((uint32_t)(0xE8F4)) +#define IMXDPUV1_TCON1_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOff */ +#define IMXDPUV1_TCON1_SPG9POSOFF ((uint32_t)(0xE8F8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOff */ +#define IMXDPUV1_TCON1_SPG9MASKOFF ((uint32_t)(0xE8FC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOn */ +#define IMXDPUV1_TCON1_SPG10POSON ((uint32_t)(0xE900)) +#define IMXDPUV1_TCON1_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON1_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOn */ +#define IMXDPUV1_TCON1_SPG10MASKON ((uint32_t)(0xE904)) +#define IMXDPUV1_TCON1_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOff */ +#define IMXDPUV1_TCON1_SPG10POSOFF ((uint32_t)(0xE908)) +#define IMXDPUV1_TCON1_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOff */ +#define IMXDPUV1_TCON1_SPG10MASKOFF ((uint32_t)(0xE90C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOn */ +#define IMXDPUV1_TCON1_SPG11POSON ((uint32_t)(0xE910)) +#define IMXDPUV1_TCON1_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON1_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOn */ +#define IMXDPUV1_TCON1_SPG11MASKON ((uint32_t)(0xE914)) +#define IMXDPUV1_TCON1_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOff */ +#define IMXDPUV1_TCON1_SPG11POSOFF ((uint32_t)(0xE918)) +#define IMXDPUV1_TCON1_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOff */ +#define IMXDPUV1_TCON1_SPG11MASKOFF ((uint32_t)(0xE91C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx0Sigs */ +#define IMXDPUV1_TCON1_SMX0SIGS ((uint32_t)(0xE920)) +#define IMXDPUV1_TCON1_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx0FctTable */ +#define IMXDPUV1_TCON1_SMX0FCTTABLE ((uint32_t)(0xE924)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx1Sigs */ +#define IMXDPUV1_TCON1_SMX1SIGS ((uint32_t)(0xE928)) +#define IMXDPUV1_TCON1_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx1FctTable */ +#define IMXDPUV1_TCON1_SMX1FCTTABLE ((uint32_t)(0xE92C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx2Sigs */ +#define IMXDPUV1_TCON1_SMX2SIGS ((uint32_t)(0xE930)) +#define IMXDPUV1_TCON1_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx2FctTable */ +#define IMXDPUV1_TCON1_SMX2FCTTABLE ((uint32_t)(0xE934)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx3Sigs */ +#define IMXDPUV1_TCON1_SMX3SIGS ((uint32_t)(0xE938)) +#define IMXDPUV1_TCON1_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx3FctTable */ +#define IMXDPUV1_TCON1_SMX3FCTTABLE ((uint32_t)(0xE93C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx4Sigs */ +#define IMXDPUV1_TCON1_SMX4SIGS ((uint32_t)(0xE940)) +#define IMXDPUV1_TCON1_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx4FctTable */ +#define IMXDPUV1_TCON1_SMX4FCTTABLE ((uint32_t)(0xE944)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx5Sigs */ +#define IMXDPUV1_TCON1_SMX5SIGS ((uint32_t)(0xE948)) +#define IMXDPUV1_TCON1_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx5FctTable */ +#define IMXDPUV1_TCON1_SMX5FCTTABLE ((uint32_t)(0xE94C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx6Sigs */ +#define IMXDPUV1_TCON1_SMX6SIGS ((uint32_t)(0xE950)) +#define IMXDPUV1_TCON1_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx6FctTable */ +#define IMXDPUV1_TCON1_SMX6FCTTABLE ((uint32_t)(0xE954)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx7Sigs */ +#define IMXDPUV1_TCON1_SMX7SIGS ((uint32_t)(0xE958)) +#define IMXDPUV1_TCON1_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx7FctTable */ +#define IMXDPUV1_TCON1_SMX7FCTTABLE ((uint32_t)(0xE95C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx8Sigs */ +#define IMXDPUV1_TCON1_SMX8SIGS ((uint32_t)(0xE960)) +#define IMXDPUV1_TCON1_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx8FctTable */ +#define IMXDPUV1_TCON1_SMX8FCTTABLE ((uint32_t)(0xE964)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx9Sigs */ +#define IMXDPUV1_TCON1_SMX9SIGS ((uint32_t)(0xE968)) +#define IMXDPUV1_TCON1_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx9FctTable */ +#define IMXDPUV1_TCON1_SMX9FCTTABLE ((uint32_t)(0xE96C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx10Sigs */ +#define IMXDPUV1_TCON1_SMX10SIGS ((uint32_t)(0xE970)) +#define IMXDPUV1_TCON1_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx10FctTable */ +#define IMXDPUV1_TCON1_SMX10FCTTABLE ((uint32_t)(0xE974)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx11Sigs */ +#define IMXDPUV1_TCON1_SMX11SIGS ((uint32_t)(0xE978)) +#define IMXDPUV1_TCON1_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx11FctTable */ +#define IMXDPUV1_TCON1_SMX11FCTTABLE ((uint32_t)(0xE97C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW ((uint32_t)(0xE980)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Dual_Debug */ +#define IMXDPUV1_TCON1_DUAL_DEBUG ((uint32_t)(0xE984)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig1_LockUnlock */ +#define IMXDPUV1_SIG1_LOCKUNLOCK ((uint32_t)(0xEC00)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig1_LockStatus */ +#define IMXDPUV1_SIG1_LOCKSTATUS ((uint32_t)(0xEC04)) +#define IMXDPUV1_SIG1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig1_StaticControl */ +#define IMXDPUV1_SIG1_STATICCONTROL ((uint32_t)(0xEC08)) +#define IMXDPUV1_SIG1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig1_PanicColor */ +#define IMXDPUV1_SIG1_PANICCOLOR ((uint32_t)(0xEC0C)) +#define IMXDPUV1_SIG1_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig1_EvalControl0 */ +#define IMXDPUV1_SIG1_EVALCONTROL0 ((uint32_t)(0xEC10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft0 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT0 ((uint32_t)(0xEC14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight0 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0 ((uint32_t)(0xEC18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef0 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF0 ((uint32_t)(0xEC1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF0 ((uint32_t)(0xEC20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0 ((uint32_t)(0xEC24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed0 */ +#define IMXDPUV1_SIG1_SIGCRCRED0 ((uint32_t)(0xEC28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen0 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN0 ((uint32_t)(0xEC2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE0 ((uint32_t)(0xEC30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl1 */ +#define IMXDPUV1_SIG1_EVALCONTROL1 ((uint32_t)(0xEC34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft1 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT1 ((uint32_t)(0xEC38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight1 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1 ((uint32_t)(0xEC3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef1 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF1 ((uint32_t)(0xEC40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF1 ((uint32_t)(0xEC44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1 ((uint32_t)(0xEC48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed1 */ +#define IMXDPUV1_SIG1_SIGCRCRED1 ((uint32_t)(0xEC4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen1 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN1 ((uint32_t)(0xEC50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE1 ((uint32_t)(0xEC54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl2 */ +#define IMXDPUV1_SIG1_EVALCONTROL2 ((uint32_t)(0xEC58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft2 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT2 ((uint32_t)(0xEC5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight2 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2 ((uint32_t)(0xEC60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef2 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF2 ((uint32_t)(0xEC64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF2 ((uint32_t)(0xEC68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2 ((uint32_t)(0xEC6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed2 */ +#define IMXDPUV1_SIG1_SIGCRCRED2 ((uint32_t)(0xEC70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen2 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN2 ((uint32_t)(0xEC74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE2 ((uint32_t)(0xEC78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl3 */ +#define IMXDPUV1_SIG1_EVALCONTROL3 ((uint32_t)(0xEC7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft3 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT3 ((uint32_t)(0xEC80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight3 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3 ((uint32_t)(0xEC84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef3 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF3 ((uint32_t)(0xEC88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF3 ((uint32_t)(0xEC8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3 ((uint32_t)(0xEC90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed3 */ +#define IMXDPUV1_SIG1_SIGCRCRED3 ((uint32_t)(0xEC94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen3 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN3 ((uint32_t)(0xEC98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE3 ((uint32_t)(0xEC9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl4 */ +#define IMXDPUV1_SIG1_EVALCONTROL4 ((uint32_t)(0xECA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft4 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT4 ((uint32_t)(0xECA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight4 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4 ((uint32_t)(0xECA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef4 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF4 ((uint32_t)(0xECAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF4 ((uint32_t)(0xECB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4 ((uint32_t)(0xECB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed4 */ +#define IMXDPUV1_SIG1_SIGCRCRED4 ((uint32_t)(0xECB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen4 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN4 ((uint32_t)(0xECBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE4 ((uint32_t)(0xECC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl5 */ +#define IMXDPUV1_SIG1_EVALCONTROL5 ((uint32_t)(0xECC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft5 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT5 ((uint32_t)(0xECC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight5 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5 ((uint32_t)(0xECCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef5 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF5 ((uint32_t)(0xECD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF5 ((uint32_t)(0xECD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5 ((uint32_t)(0xECD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed5 */ +#define IMXDPUV1_SIG1_SIGCRCRED5 ((uint32_t)(0xECDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen5 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN5 ((uint32_t)(0xECE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE5 ((uint32_t)(0xECE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl6 */ +#define IMXDPUV1_SIG1_EVALCONTROL6 ((uint32_t)(0xECE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft6 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT6 ((uint32_t)(0xECEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight6 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6 ((uint32_t)(0xECF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef6 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF6 ((uint32_t)(0xECF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF6 ((uint32_t)(0xECF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6 ((uint32_t)(0xECFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed6 */ +#define IMXDPUV1_SIG1_SIGCRCRED6 ((uint32_t)(0xED00)) +#define IMXDPUV1_SIG1_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen6 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN6 ((uint32_t)(0xED04)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE6 ((uint32_t)(0xED08)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl7 */ +#define IMXDPUV1_SIG1_EVALCONTROL7 ((uint32_t)(0xED0C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft7 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT7 ((uint32_t)(0xED10)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight7 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7 ((uint32_t)(0xED14)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef7 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF7 ((uint32_t)(0xED18)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF7 ((uint32_t)(0xED1C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7 ((uint32_t)(0xED20)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed7 */ +#define IMXDPUV1_SIG1_SIGCRCRED7 ((uint32_t)(0xED24)) +#define IMXDPUV1_SIG1_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen7 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN7 ((uint32_t)(0xED28)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE7 ((uint32_t)(0xED2C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ShadowLoad */ +#define IMXDPUV1_SIG1_SHADOWLOAD ((uint32_t)(0xED30)) +#define IMXDPUV1_SIG1_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ContinuousMode */ +#define IMXDPUV1_SIG1_CONTINUOUSMODE ((uint32_t)(0xED34)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SoftwareKick */ +#define IMXDPUV1_SIG1_SOFTWAREKICK ((uint32_t)(0xED38)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig1_Status */ +#define IMXDPUV1_SIG1_STATUS ((uint32_t)(0xED3C)) +#define IMXDPUV1_SIG1_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG1_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_DPUXPC_Control */ +#define IMXDPUV1_DPUXPC_CONTROL ((uint32_t)(0xF000)) +#define IMXDPUV1_DPUXPC_CONTROL_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DPUXPC_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_MASK 0x1U +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_SHIFT 0U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_MASK 0x6U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_SHIFT 1U +/* Field Value: MODE__XPC_MODE_MANUAL, Manual measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_MANUAL 0U +/* Field Value: MODE__XPC_MODE_TIMER, Timer controlled measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_TIMER 0x1U +/* Field Value: MODE__XPC_MODE_CONTINUOUS, Continuous measurement; retriggered + * by reading SW_Tag register */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_CONTINUOUS 0x2U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_MASK 0x40000000U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_SHIFT 30U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_Timer */ +#define IMXDPUV1_DPUXPC_TIMER ((uint32_t)(0xF004)) +#define IMXDPUV1_DPUXPC_TIMER_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DPUXPC_TIMER_RESET_VALUE 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_MASK 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_SHIFT 0U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_MASK 0xF0000000U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_SHIFT 28U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTimeControl */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL ((uint32_t)(0xF008)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_MASK 0xFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_SHIFT 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_SW_Tag */ +#define IMXDPUV1_DPUXPC_SW_TAG ((uint32_t)(0xF00C)) +#define IMXDPUV1_DPUXPC_SW_TAG_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTime */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME ((uint32_t)(0xF010)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_Global_Counter */ +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER ((uint32_t)(0xF014)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Switch */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH ((uint32_t)(0xF018)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_SHIFT 0U +/* Field Value: MU00_SELECT__MU00_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC00 0U +/* Field Value: MU00_SELECT__MU00_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC01 0x1U +/* Field Value: MU00_SELECT__MU00_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC02 0x2U +/* Field Value: MU00_SELECT__MU00_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC03 0x3U +/* Field Value: MU00_SELECT__MU00_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC04 0x4U +/* Field Value: MU00_SELECT__MU00_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC05 0x5U +/* Field Value: MU00_SELECT__MU00_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC06 0x6U +/* Field Value: MU00_SELECT__MU00_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC07 0x7U +/* Field Value: MU00_SELECT__MU00_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC08 0x8U +/* Field Value: MU00_SELECT__MU00_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC09 0x9U +/* Field Value: MU00_SELECT__MU00_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC10 0xAU +/* Field Value: MU00_SELECT__MU00_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC11 0xBU +/* Field Value: MU00_SELECT__MU00_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC12 0xCU +/* Field Value: MU00_SELECT__MU00_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC13 0xDU +/* Field Value: MU00_SELECT__MU00_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC14 0xEU +/* Field Value: MU00_SELECT__MU00_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC15 0xFU +/* Field Value: MU00_SELECT__MU00_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC16 0x10U +/* Field Value: MU00_SELECT__MU00_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU00_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER ((uint32_t)(0xF01C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER ((uint32_t)(0xF020)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER ((uint32_t)(0xF024)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER ((uint32_t)(0xF028)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER ((uint32_t)(0xF02C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Switch */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH ((uint32_t)(0xF030)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_VALUE 0x1U +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_SHIFT 0U +/* Field Value: MU01_SELECT__MU01_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC00 0U +/* Field Value: MU01_SELECT__MU01_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC01 0x1U +/* Field Value: MU01_SELECT__MU01_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC02 0x2U +/* Field Value: MU01_SELECT__MU01_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC03 0x3U +/* Field Value: MU01_SELECT__MU01_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC04 0x4U +/* Field Value: MU01_SELECT__MU01_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC05 0x5U +/* Field Value: MU01_SELECT__MU01_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC06 0x6U +/* Field Value: MU01_SELECT__MU01_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC07 0x7U +/* Field Value: MU01_SELECT__MU01_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC08 0x8U +/* Field Value: MU01_SELECT__MU01_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC09 0x9U +/* Field Value: MU01_SELECT__MU01_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC10 0xAU +/* Field Value: MU01_SELECT__MU01_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC11 0xBU +/* Field Value: MU01_SELECT__MU01_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC12 0xCU +/* Field Value: MU01_SELECT__MU01_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC13 0xDU +/* Field Value: MU01_SELECT__MU01_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC14 0xEU +/* Field Value: MU01_SELECT__MU01_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC15 0xFU +/* Field Value: MU01_SELECT__MU01_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC16 0x10U +/* Field Value: MU01_SELECT__MU01_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU01_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER ((uint32_t)(0xF034)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER ((uint32_t)(0xF038)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER ((uint32_t)(0xF03C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER ((uint32_t)(0xF040)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER ((uint32_t)(0xF044)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Switch */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH ((uint32_t)(0xF048)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_VALUE 0x2U +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_SHIFT 0U +/* Field Value: MU02_SELECT__MU02_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC00 0U +/* Field Value: MU02_SELECT__MU02_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC01 0x1U +/* Field Value: MU02_SELECT__MU02_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC02 0x2U +/* Field Value: MU02_SELECT__MU02_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC03 0x3U +/* Field Value: MU02_SELECT__MU02_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC04 0x4U +/* Field Value: MU02_SELECT__MU02_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC05 0x5U +/* Field Value: MU02_SELECT__MU02_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC06 0x6U +/* Field Value: MU02_SELECT__MU02_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC07 0x7U +/* Field Value: MU02_SELECT__MU02_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC08 0x8U +/* Field Value: MU02_SELECT__MU02_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC09 0x9U +/* Field Value: MU02_SELECT__MU02_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC10 0xAU +/* Field Value: MU02_SELECT__MU02_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC11 0xBU +/* Field Value: MU02_SELECT__MU02_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC12 0xCU +/* Field Value: MU02_SELECT__MU02_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC13 0xDU +/* Field Value: MU02_SELECT__MU02_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC14 0xEU +/* Field Value: MU02_SELECT__MU02_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC15 0xFU +/* Field Value: MU02_SELECT__MU02_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC16 0x10U +/* Field Value: MU02_SELECT__MU02_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU02_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER ((uint32_t)(0xF04C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER ((uint32_t)(0xF050)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER ((uint32_t)(0xF054)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER ((uint32_t)(0xF058)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER ((uint32_t)(0xF05C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Switch */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH ((uint32_t)(0xF060)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_VALUE 0x3U +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_SHIFT 0U +/* Field Value: MU03_SELECT__MU03_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC00 0U +/* Field Value: MU03_SELECT__MU03_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC01 0x1U +/* Field Value: MU03_SELECT__MU03_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC02 0x2U +/* Field Value: MU03_SELECT__MU03_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC03 0x3U +/* Field Value: MU03_SELECT__MU03_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC04 0x4U +/* Field Value: MU03_SELECT__MU03_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC05 0x5U +/* Field Value: MU03_SELECT__MU03_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC06 0x6U +/* Field Value: MU03_SELECT__MU03_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC07 0x7U +/* Field Value: MU03_SELECT__MU03_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC08 0x8U +/* Field Value: MU03_SELECT__MU03_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC09 0x9U +/* Field Value: MU03_SELECT__MU03_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC10 0xAU +/* Field Value: MU03_SELECT__MU03_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC11 0xBU +/* Field Value: MU03_SELECT__MU03_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC12 0xCU +/* Field Value: MU03_SELECT__MU03_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC13 0xDU +/* Field Value: MU03_SELECT__MU03_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC14 0xEU +/* Field Value: MU03_SELECT__MU03_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC15 0xFU +/* Field Value: MU03_SELECT__MU03_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC16 0x10U +/* Field Value: MU03_SELECT__MU03_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU03_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER ((uint32_t)(0xF064)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER ((uint32_t)(0xF068)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER ((uint32_t)(0xF06C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER ((uint32_t)(0xF070)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER ((uint32_t)(0xF074)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Switch */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH ((uint32_t)(0xF078)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_VALUE 0x4U +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_SHIFT 0U +/* Field Value: MU04_SELECT__MU04_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC00 0U +/* Field Value: MU04_SELECT__MU04_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC01 0x1U +/* Field Value: MU04_SELECT__MU04_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC02 0x2U +/* Field Value: MU04_SELECT__MU04_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC03 0x3U +/* Field Value: MU04_SELECT__MU04_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC04 0x4U +/* Field Value: MU04_SELECT__MU04_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC05 0x5U +/* Field Value: MU04_SELECT__MU04_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC06 0x6U +/* Field Value: MU04_SELECT__MU04_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC07 0x7U +/* Field Value: MU04_SELECT__MU04_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC08 0x8U +/* Field Value: MU04_SELECT__MU04_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC09 0x9U +/* Field Value: MU04_SELECT__MU04_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC10 0xAU +/* Field Value: MU04_SELECT__MU04_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC11 0xBU +/* Field Value: MU04_SELECT__MU04_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC12 0xCU +/* Field Value: MU04_SELECT__MU04_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC13 0xDU +/* Field Value: MU04_SELECT__MU04_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC14 0xEU +/* Field Value: MU04_SELECT__MU04_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC15 0xFU +/* Field Value: MU04_SELECT__MU04_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC16 0x10U +/* Field Value: MU04_SELECT__MU04_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU04_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER ((uint32_t)(0xF07C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER ((uint32_t)(0xF080)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER ((uint32_t)(0xF084)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER ((uint32_t)(0xF088)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER ((uint32_t)(0xF08C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_SHIFT 0U + +#endif /* IMXDPUV1_REGISTERS_H */