[MIPS] MIPS 4K core: Coding style cleanups
No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi
parent
f5e429d386
commit
03c031d566
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@ -22,7 +22,6 @@
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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@ -30,13 +29,11 @@
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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/* 16KB is the maximum size of instruction and data caches on
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* MIPS 4K.
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*/
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#define MIPS_MAX_CACHE_SIZE 0x4000
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/*
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* cacheop macro to automate cache operations
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* first some helpers...
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@ -131,7 +128,6 @@ mips_cache_reset:
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li t4, CFG_CACHELINE_SIZE
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move t5, t4
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li v0, MIPS_MAX_CACHE_SIZE
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/* Now clear that much memory starting from zero.
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@ -139,8 +135,8 @@ mips_cache_reset:
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li a0, KSEG1
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addu a1, a0, v0
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2: sw zero, 0(a0)
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2:
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sw zero, 0(a0)
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sw zero, 4(a0)
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sw zero, 8(a0)
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sw zero, 12(a0)
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@ -156,11 +152,11 @@ mips_cache_reset:
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mtc0 zero, CP0_TAGLO
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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/* Assume bottom of RAM will generate good parity for the cache.
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*/
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@ -201,9 +197,9 @@ mips_cache_reset:
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move a1, a2
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icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
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j ra
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.end mips_cache_reset
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j ra
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.end mips_cache_reset
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/*******************************************************************************
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*
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@ -220,7 +216,7 @@ dcache_status:
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andi v0, v0, 1
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j ra
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.end dcache_status
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.end dcache_status
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/*******************************************************************************
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*
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@ -237,11 +233,10 @@ dcache_disable:
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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mtc0 t0, CP0_CONFIG
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j ra
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.end dcache_disable
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.end dcache_disable
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/*******************************************************************************
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*
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@ -266,4 +261,5 @@ mips_cache_lock:
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icacheop(a0,a1,a2,a3,0x1d)
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j ra
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.end mips_cache_lock
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@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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return 0;
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}
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void flush_cache (ulong start_addr, ulong size)
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void flush_cache(ulong start_addr, ulong size)
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{
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}
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void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_32bit_cp0_register(CP0_ENTRYLO0, low0);
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write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
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write_32bit_cp0_register(CP0_ENTRYLO1, low1);
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@ -22,13 +22,11 @@
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#define RVECENT(f,n) \
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b f; nop
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#define XVECENT(f,bev) \
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@ -192,7 +190,7 @@ _start:
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.word 0x00000000
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.word 0x03e00008
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.word 0x00000000
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.word 0x00000000
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.word 0x00000000
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/* 0xbfc00428 */
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.word 0xdc870000
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.word 0xfca70000
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@ -203,7 +201,7 @@ _start:
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.word 0x00000000
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.word 0x03e00008
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.word 0x00000000
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.word 0x00000000
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.word 0x00000000
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#endif /* CONFIG_PURPLE */
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.align 4
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reset:
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@ -235,33 +233,33 @@ reset:
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mtc0 t0, CP0_CONFIG
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/* Initialize $gp.
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*/
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bal 1f
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*/
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bal 1f
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nop
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.word _gp
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1:
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move gp, ra
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lw t1, 0(ra)
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1:
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move gp, ra
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lw t1, 0(ra)
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move gp, t1
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#ifdef CONFIG_INCA_IP
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/* Disable INCA-IP Watchdog.
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*/
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la t9, disable_incaip_wdt
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jalr t9
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la t9, disable_incaip_wdt
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jalr t9
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nop
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#endif
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/* Initialize any external memory.
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*/
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la t9, lowlevel_init
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jalr t9
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la t9, lowlevel_init
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jalr t9
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nop
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/* Initialize caches...
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*/
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la t9, mips_cache_reset
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jalr t9
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la t9, mips_cache_reset
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jalr t9
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nop
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/* ... and enable them.
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@ -269,12 +267,11 @@ reset:
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li t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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/* Set up temporary stack.
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*/
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li a0, CFG_INIT_SP_OFFSET
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la t9, mips_cache_lock
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jalr t9
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la t9, mips_cache_lock
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jalr t9
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nop
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li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
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@ -284,7 +281,6 @@ reset:
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j t9
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nop
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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@ -298,7 +294,7 @@ reset:
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.globl relocate_code
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.ent relocate_code
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relocate_code:
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move sp, a0 /* Set new stack pointer */
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move sp, a0 /* Set new stack pointer */
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li t0, CFG_MONITOR_BASE
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la t3, in_ram
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@ -312,8 +308,8 @@ relocate_code:
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*/
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move t6, gp
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sub gp, CFG_MONITOR_BASE
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add gp, a2 /* gp now adjusted */
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sub t6, gp, t6 /* t6 <-- relocation offset */
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add gp, a2 /* gp now adjusted */
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sub t6, gp, t6 /* t6 <-- relocation offset */
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/*
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* t0 = source address
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@ -329,7 +325,7 @@ relocate_code:
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sw t3, 0(t1)
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addu t0, 4
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ble t0, t2, 1b
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addu t1, 4 /* delay slot */
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addu t1, 4 /* delay slot */
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#endif
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/* If caches were enabled, we would have to flush them here.
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@ -376,7 +372,8 @@ in_ram:
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add t2, t6
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sub t1, 4
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1: addi t1, 4
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1:
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addi t1, 4
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bltl t1, t2, 1b
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sw zero, 0(t1) /* delay slot */
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@ -387,11 +384,10 @@ in_ram:
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.end relocate_code
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/* Exception handlers.
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*/
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romReserved:
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b romReserved
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b romReserved
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romExcHandle:
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b romExcHandle
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b romExcHandle
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