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arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig 

Enable ELBC from Kconfig.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Prabhakar Kushwaha 2017-02-02 15:01:48 +05:30 committed by York Sun
parent 8e63ed518d
commit 068789773d
16 changed files with 20 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -455,6 +455,7 @@ config ARCH_MPC8536
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_MPC8540 config ARCH_MPC8540
bool bool
@ -478,6 +479,7 @@ config ARCH_MPC8544
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_MPC8548 config ARCH_MPC8548
bool bool
@ -524,6 +526,7 @@ config ARCH_MPC8569
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select FSL_ELBC
config ARCH_MPC8572 config ARCH_MPC8572
bool bool
@ -538,6 +541,7 @@ config ARCH_MPC8572
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1010 config ARCH_P1010
bool bool
@ -572,6 +576,7 @@ config ARCH_P1011
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1020 config ARCH_P1020
bool bool
@ -585,6 +590,7 @@ config ARCH_P1020
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1021 config ARCH_P1021
bool bool
@ -598,6 +604,7 @@ config ARCH_P1021
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1022 config ARCH_P1022
bool bool
@ -613,6 +620,7 @@ config ARCH_P1022
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1023 config ARCH_P1023
bool bool
@ -624,6 +632,7 @@ config ARCH_P1023
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
config ARCH_P1024 config ARCH_P1024
bool bool
@ -637,6 +646,7 @@ config ARCH_P1024
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P1025 config ARCH_P1025
bool bool
@ -650,6 +660,7 @@ config ARCH_P1025
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P2020 config ARCH_P2020
bool bool
@ -664,6 +675,7 @@ config ARCH_P2020
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2 select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
config ARCH_P2041 config ARCH_P2041
bool bool
@ -685,6 +697,7 @@ config ARCH_P2041
select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
config ARCH_P3041 config ARCH_P3041
bool bool
@ -708,6 +721,7 @@ config ARCH_P3041
select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
config ARCH_P4080 config ARCH_P4080
bool bool
@ -742,6 +756,7 @@ config ARCH_P4080
select SYS_FSL_QORIQ_CHASSIS1 select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
config ARCH_P5020 config ARCH_P5020
bool bool
@ -762,6 +777,7 @@ config ARCH_P5020
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64 select SYS_PPC64
select FSL_ELBC
config ARCH_P5040 config ARCH_P5040
bool bool
@ -782,6 +798,7 @@ config ARCH_P5040
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64 select SYS_PPC64
select FSL_ELBC
config ARCH_QEMU_E500 config ARCH_QEMU_E500
bool bool
@ -1277,6 +1294,9 @@ config SYS_PPC_E500_USE_DEBUG_TLB
config FSL_IFC config FSL_IFC
bool bool
config FSL_ELBC
bool
config SYS_PPC_E500_DEBUG_TLB config SYS_PPC_E500_DEBUG_TLB
int "Temporary TLB entry for external debugger" int "Temporary TLB entry for external debugger"
depends on SYS_PPC_E500_USE_DEBUG_TLB depends on SYS_PPC_E500_USE_DEBUG_TLB

1
include/configs/MPC8536DS.h
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@ -37,7 +37,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif #endif
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */

2
include/configs/MPC8569MDS.h
View File

@ -10,8 +10,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */

1
include/configs/MPC8572DS.h
View File

@ -28,7 +28,6 @@
/* High Level Configuration Options */ /* High Level Configuration Options */
#define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */

1
include/configs/P1022DS.h
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@ -96,7 +96,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif #endif
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */

1
include/configs/P1023RDB.h
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@ -25,7 +25,6 @@
/* High Level Configuration Options */ /* High Level Configuration Options */
#define CONFIG_MP /* support multiple processors */ #define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */

1
include/configs/P2041RDB.h
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@ -41,7 +41,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */

1
include/configs/UCP1020.h
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@ -14,7 +14,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/controlcenterd.h
View File

@ -137,7 +137,6 @@
/* /*
* Local Bus Definitions * Local Bus Definitions
*/ */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_SYS_ELBC_BASE 0xe0000000 #define CONFIG_SYS_ELBC_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT

1
include/configs/corenet_ds.h
View File

@ -59,7 +59,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */

1
include/configs/cyrus.h
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@ -49,7 +49,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/km/kmp204x-common.h
View File

@ -35,7 +35,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/p1_p2_rdb_pc.h
View File

@ -260,7 +260,6 @@
#define CONFIG_MP #define CONFIG_MP
#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/p1_twr.h
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@ -40,7 +40,6 @@
#define CONFIG_MP #define CONFIG_MP
#define CONFIG_FSL_ELBC
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/xpedite537x.h
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@ -29,7 +29,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_ELBC 1
/* /*
* Multicore config * Multicore config

1
include/configs/xpedite550x.h
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@ -30,7 +30,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_ELBC 1
/* /*
* Multicore config * Multicore config