video: add support of panel RM68200
Support for Raydium RM68200 720p dsi 2dl video mode panel. This rm68200 panel driver is based on the Linux Kernel driver from drivers/gpu/drm/panel/panel-raydium-rm68200.c. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
This commit is contained in:
Yannick Fertré
Anatolij Gustschin
parent
78157b2fa5
commit
06ef131d30
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@ -337,6 +337,15 @@ config VIDEO_LCD_ORISETECH_OTM8009A
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Say Y here if you want to enable support for Orise Technology
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Say Y here if you want to enable support for Orise Technology
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otm8009a 480x800 dsi 2dl panel.
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otm8009a 480x800 dsi 2dl panel.
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config VIDEO_LCD_RAYDIUM_RM68200
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bool "RM68200 DSI LCD panel support"
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depends on DM_VIDEO
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select VIDEO_MIPI_DSI
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default n
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help
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Say Y here if you want to enable support for Raydium RM68200
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720x1280 DSI video mode panel.
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config VIDEO_LCD_SSD2828
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config VIDEO_LCD_SSD2828
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bool "SSD2828 bridge chip"
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bool "SSD2828 bridge chip"
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default n
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default n
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@ -53,6 +53,7 @@ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
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obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
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obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
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obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
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obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
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obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
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obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
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obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
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obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
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obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
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obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
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obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
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obj-${CONFIG_VIDEO_MESON} += meson/
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obj-${CONFIG_VIDEO_MESON} += meson/
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@ -0,0 +1,351 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 STMicroelectronics - All Rights Reserved
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* Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
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* Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
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*
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* This rm68200 panel driver is inspired from the Linux Kernel driver
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* drivers/gpu/drm/panel/panel-raydium-rm68200.c.
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*/
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#include <common.h>
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#include <backlight.h>
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#include <dm.h>
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#include <mipi_dsi.h>
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#include <panel.h>
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#include <asm/gpio.h>
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#include <power/regulator.h>
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/*** Manufacturer Command Set ***/
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#define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
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#define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
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#define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
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#define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
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#define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
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#define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
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/* CMD2 P0 commands (Display Options and Power) */
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#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
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#define MCS_SGOPCTR 0x16 /* Source Bias Current */
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#define MCS_SDCTR 0x1A /* Source Output Delay Time */
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#define MCS_INVCTR 0x1B /* Inversion Type */
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#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
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#define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
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#define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
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#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
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#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
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#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
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#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
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#define MCS_SETVGN 0x52 /* VG M/S N Control */
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#define MCS_SETVGP 0x54 /* VG M/S P Control */
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#define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
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/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
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#define GOA_VSTV1 0x00
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#define GOA_VSTV2 0x07
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#define GOA_VCLK1 0x0E
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#define GOA_VCLK2 0x17
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#define GOA_VCLK_OPT1 0x20
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#define GOA_BICLK1 0x2A
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#define GOA_BICLK2 0x37
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#define GOA_BICLK3 0x44
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#define GOA_BICLK4 0x4F
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#define GOA_BICLK_OPT1 0x5B
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#define GOA_BICLK_OPT2 0x60
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#define MCS_GOA_GPO1 0x6D
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#define MCS_GOA_GPO2 0x71
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#define MCS_GOA_EQ 0x74
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#define MCS_GOA_CLK_GALLON 0x7C
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#define MCS_GOA_FS_SEL0 0x7E
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#define MCS_GOA_FS_SEL1 0x87
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#define MCS_GOA_FS_SEL2 0x91
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#define MCS_GOA_FS_SEL3 0x9B
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#define MCS_GOA_BS_SEL0 0xAC
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#define MCS_GOA_BS_SEL1 0xB5
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#define MCS_GOA_BS_SEL2 0xBF
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#define MCS_GOA_BS_SEL3 0xC9
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#define MCS_GOA_BS_SEL4 0xD3
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/* CMD2 P3 commands (Gamma) */
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#define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
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#define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
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struct rm68200_panel_priv {
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struct udevice *reg;
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struct udevice *backlight;
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struct gpio_desc reset;
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unsigned int lanes;
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enum mipi_dsi_pixel_format format;
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unsigned long mode_flags;
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};
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static const struct display_timing default_timing = {
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.pixelclock.typ = 54000000,
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.hactive.typ = 720,
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.hfront_porch.typ = 48,
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.hback_porch.typ = 48,
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.hsync_len.typ = 9,
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.vactive.typ = 1280,
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.vfront_porch.typ = 12,
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.vback_porch.typ = 12,
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.vsync_len.typ = 5,
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};
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static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
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size_t len)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
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struct mipi_dsi_device *device = plat->device;
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int err;
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err = mipi_dsi_dcs_write_buffer(device, data, len);
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if (err < 0)
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dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
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}
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static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
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struct mipi_dsi_device *device = plat->device;
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int err;
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err = mipi_dsi_dcs_write(device, cmd, &value, 1);
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if (err < 0)
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dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
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}
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#define dcs_write_seq(ctx, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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\
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rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
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})
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/*
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* This panel is not able to auto-increment all cmd addresses so for some of
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* them, we need to send them one by one...
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*/
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#define dcs_write_cmd_seq(ctx, cmd, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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unsigned int i; \
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\
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for (i = 0; i < ARRAY_SIZE(d) ; i++) \
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rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
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})
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static void rm68200_init_sequence(struct udevice *dev)
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{
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/* Enter CMD2 with page 0 */
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dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
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dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
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dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
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dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
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dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
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dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
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dcs_write_seq(dev, MCS_BT3CTR, 0x53);
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dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
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dcs_write_seq(dev, MCS_INVCTR, 0x00);
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dcs_write_seq(dev, MCS_STBCTR, 0x0A);
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dcs_write_seq(dev, MCS_SDCTR, 0x06);
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dcs_write_seq(dev, MCS_VCMCTR, 0x56);
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dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
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dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
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dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
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dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
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dcs_write_seq(dev, GOA_VSTV1, 0x05);
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dcs_write_seq(dev, 0x02, 0x0B);
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dcs_write_seq(dev, 0x03, 0x0F);
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dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
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dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
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0x50);
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dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
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0x00, 0x85, 0x08);
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dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
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0x00, 0x85, 0x08);
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dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
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dcs_write_seq(dev, 0x2D, 0x01);
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dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
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0x00);
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dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
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dcs_write_seq(dev, 0x3D, 0x40);
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dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
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dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00);
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dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
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dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
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dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
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dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
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0x00, 0x00);
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dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
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dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
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0x16, 0x12, 0x08, 0x3F);
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dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
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0x0A, 0x0E, 0x3F, 0x3F, 0x00);
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dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
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0x05, 0x01, 0x3F, 0x3F, 0x0F);
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dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
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0x3F);
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dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
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dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
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dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
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0x15, 0x11, 0x0F, 0x3F);
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dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
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0x0D, 0x09, 0x3F, 0x3F, 0x07);
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dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
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0x02, 0x06, 0x3F, 0x3F, 0x08);
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dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
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0x3F, 0x3F, 0x0E, 0x10, 0x14);
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dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
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dcs_write_seq(dev, 0xDC, 0x02);
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dcs_write_seq(dev, 0xDE, 0x12);
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dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
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dcs_write_seq(dev, 0x01, 0x75);
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dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
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dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
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0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
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0x12, 0x0C, 0x00);
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dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
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0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
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0x12, 0x0C, 0x00);
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/* Exit CMD2 */
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dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
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}
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static int rm68200_panel_enable_backlight(struct udevice *dev)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
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struct mipi_dsi_device *device = plat->device;
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struct rm68200_panel_priv *priv = dev_get_priv(dev);
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int ret;
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ret = mipi_dsi_attach(device);
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if (ret < 0)
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return ret;
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rm68200_init_sequence(dev);
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ret = mipi_dsi_dcs_exit_sleep_mode(device);
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if (ret)
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return ret;
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|
mdelay(125);
|
||||||
|
|
||||||
|
ret = mipi_dsi_dcs_set_display_on(device);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
mdelay(20);
|
||||||
|
|
||||||
|
ret = backlight_enable(priv->backlight);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rm68200_panel_get_display_timing(struct udevice *dev,
|
||||||
|
struct display_timing *timings)
|
||||||
|
{
|
||||||
|
struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
|
||||||
|
struct mipi_dsi_device *device = plat->device;
|
||||||
|
struct rm68200_panel_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
|
memcpy(timings, &default_timing, sizeof(*timings));
|
||||||
|
|
||||||
|
/* fill characteristics of DSI data link */
|
||||||
|
device->lanes = priv->lanes;
|
||||||
|
device->format = priv->format;
|
||||||
|
device->mode_flags = priv->mode_flags;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct rm68200_panel_priv *priv = dev_get_priv(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
|
||||||
|
ret = device_get_supply_regulator(dev, "power-supply",
|
||||||
|
&priv->reg);
|
||||||
|
if (ret && ret != -ENOENT) {
|
||||||
|
dev_err(dev, "Warning: cannot get power supply\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
|
||||||
|
GPIOD_IS_OUT);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "Warning: cannot get reset GPIO\n");
|
||||||
|
if (ret != -ENOENT)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
|
||||||
|
"backlight", &priv->backlight);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rm68200_panel_probe(struct udevice *dev)
|
||||||
|
{
|
||||||
|
struct rm68200_panel_priv *priv = dev_get_priv(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
|
||||||
|
ret = regulator_set_enable(priv->reg, true);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* reset panel */
|
||||||
|
dm_gpio_set_value(&priv->reset, true);
|
||||||
|
mdelay(1);
|
||||||
|
dm_gpio_set_value(&priv->reset, false);
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
|
priv->lanes = 2;
|
||||||
|
priv->format = MIPI_DSI_FMT_RGB888;
|
||||||
|
priv->mode_flags = MIPI_DSI_MODE_VIDEO |
|
||||||
|
MIPI_DSI_MODE_VIDEO_BURST |
|
||||||
|
MIPI_DSI_MODE_LPM;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct panel_ops rm68200_panel_ops = {
|
||||||
|
.enable_backlight = rm68200_panel_enable_backlight,
|
||||||
|
.get_display_timing = rm68200_panel_get_display_timing,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id rm68200_panel_ids[] = {
|
||||||
|
{ .compatible = "raydium,rm68200" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(rm68200_panel) = {
|
||||||
|
.name = "rm68200_panel",
|
||||||
|
.id = UCLASS_PANEL,
|
||||||
|
.of_match = rm68200_panel_ids,
|
||||||
|
.ops = &rm68200_panel_ops,
|
||||||
|
.ofdata_to_platdata = rm68200_panel_ofdata_to_platdata,
|
||||||
|
.probe = rm68200_panel_probe,
|
||||||
|
.platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
|
||||||
|
.priv_auto_alloc_size = sizeof(struct rm68200_panel_priv),
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue