ENGR00315894-81 gis: Add gis module
Add gis module, current gis is support vadc input. Add power down function to lcdif driver. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit a007b00dd8ef9f773dfdebef0b1deb0990281793) (cherry picked from commit a31dcdafb0963381e7213c59f79a340ef27ec2e2) (cherry picked from commit 02dfe2e4af5f51d39a51542fb0e81f93faf505bc) (cherry picked from commit a8e94954d8ccc44c41d77a5e356d6a99b3d45649)
This commit is contained in:
Ye.Li
Ye Li
parent
40c2e2c216
commit
0864a17afb
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@ -2,7 +2,7 @@
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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* (C) Copyright 2009-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -22,6 +22,10 @@
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#include <thermal.h>
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#include <sata.h>
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#ifdef CONFIG_VIDEO_GIS
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#include <gis.h>
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#endif
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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@ -299,6 +303,10 @@ void arch_preboot_os(void)
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/* disable video before launching O/S */
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ipuv3_fb_shutdown();
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#endif
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#ifdef CONFIG_VIDEO_GIS
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/* Entry for GIS */
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mxc_disable_gis();
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#endif
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#if defined(CONFIG_VIDEO_MXS)
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lcdif_power_down();
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#endif
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@ -58,6 +58,10 @@ obj-${CONFIG_EXYNOS_FB} += exynos/
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obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
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obj-${CONFIG_VIDEO_STM32} += stm32/
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obj-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o
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obj-$(CONFIG_VIDEO_VADC) += mxc_vadc.o
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obj-$(CONFIG_VIDEO_CSI) += mxc_csi.o
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obj-$(CONFIG_VIDEO_PXP) += mxc_pxp.o
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obj-$(CONFIG_VIDEO_GIS) += mxc_gis.o
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obj-y += bridge/
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obj-y += sunxi/
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@ -0,0 +1,392 @@
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/string.h>
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#include <linux/list.h>
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#include <linux/fb.h>
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#include <gis.h>
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#include <mxsfb.h>
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#include "mxc_gis.h"
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#include "mxc_csi.h"
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#include "mxc_pxp.h"
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#include "mxc_vadc.h"
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#define CHANNEL_OFFSET 36
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#define COMMAND_OFFSET 8
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#define REG_OFFSET 4
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#define COMMAND_OPCODE_SHIFT 8
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enum {
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CMD_SET_ACC = 0,
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CMD_WR_DATA,
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CMD_WR_ACC,
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CMD_WR_ALU,
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CMD_MOV_ACC,
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CMD_RD_DATA,
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CMD_RD_ALU,
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CMD_WR_FB_CSI,
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CMD_WR_FB_PXP_IN,
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CMD_WR_FB_PXP_OUT,
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CMD_WR_FB_LCDIF,
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};
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enum {
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ALU_AND = 0,
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ALU_OR,
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ALU_XOR,
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ALU_ADD,
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ALU_SUB,
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};
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enum {
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CH_MAPPING_CSI_ISR = 0,
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CH_MAPPING_CSI_FB_UPDATE,
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CH_MAPPING_PXP_ISR,
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CH_MAPPING_LCDIF_FB_UPDATE,
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CH_MAPPING_PXP_KICK,
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CH_MAPPING_CHANNEL_UNUSED = 0xf,
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};
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enum {
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LCDIF1_SEL = 0x10,
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LCDIF0_SEL = 0x8,
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PXP_SEL = 0x4,
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CSI1_SEL = 0x2,
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CSI0_SEL = 0x1,
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};
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struct command_opcode {
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unsigned opcode:4;
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unsigned alu:3;
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unsigned acc_neg:1;
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};
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struct command_param {
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union {
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struct command_opcode cmd_bits;
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u8 cmd_opc;
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};
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u32 addr;
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u32 data;
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};
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struct channel_param {
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u32 ch_num;
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u32 ch_map;
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u32 cmd_num;
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struct command_param cmd_data[4];
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};
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static void *csibuf0, *csibuf1, *fb0, *fb1;
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static struct mxs_gis_regs *gis_regs;
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static struct mxs_pxp_regs *pxp_regs;
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static struct mxs_csi_regs *csi_regs;
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static struct mxs_lcdif_regs *lcdif_regs;
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static u32 lcdif_sel;
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static bool gis_running;
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static void config_channel(struct channel_param *ch)
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{
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u32 val, i;
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u32 reg_offset;
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/* Config channel map and command */
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switch (ch->ch_num) {
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case 0:
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val = readl(&gis_regs->hw_gis_config0);
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val &= ~(GIS_CONFIG0_CH0_MAPPING_MASK | GIS_CONFIG0_CH0_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG0_CH0_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG0_CH0_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config0);
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break;
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case 1:
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val = readl(&gis_regs->hw_gis_config0);
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val &= ~(GIS_CONFIG0_CH1_MAPPING_MASK | GIS_CONFIG0_CH1_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG0_CH1_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG0_CH1_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config0);
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break;
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case 2:
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val = readl(&gis_regs->hw_gis_config0);
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val &= ~(GIS_CONFIG0_CH2_MAPPING_MASK | GIS_CONFIG0_CH2_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG0_CH2_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG0_CH2_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config0);
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break;
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case 3:
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val = readl(&gis_regs->hw_gis_config0);
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val &= ~(GIS_CONFIG0_CH3_MAPPING_MASK | GIS_CONFIG0_CH3_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG0_CH3_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG0_CH3_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config0);
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break;
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case 4:
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val = readl(&gis_regs->hw_gis_config1);
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val &= ~(GIS_CONFIG1_CH4_MAPPING_MASK | GIS_CONFIG1_CH4_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG1_CH4_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG1_CH4_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config1);
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break;
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case 5:
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val = readl(&gis_regs->hw_gis_config1);
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val &= ~(GIS_CONFIG1_CH5_MAPPING_MASK | GIS_CONFIG1_CH5_NUM_MASK);
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val |= ch->ch_map << GIS_CONFIG1_CH5_MAPPING_SHIFT;
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val |= ch->cmd_num << GIS_CONFIG1_CH5_NUM_SHIFT;
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writel(val, &gis_regs->hw_gis_config1);
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break;
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default:
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printf("Error channel num\n");
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}
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/* Config command */
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for (i = 0; i < ch->cmd_num; i++) {
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val = readl(&gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
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val &= ~(0xFF << (COMMAND_OPCODE_SHIFT * i));
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val |= ch->cmd_data[i].cmd_opc << (COMMAND_OPCODE_SHIFT * i);
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writel(val, &gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
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reg_offset = ch->ch_num * CHANNEL_OFFSET + i * COMMAND_OFFSET;
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writel(ch->cmd_data[i].addr, &gis_regs->hw_gis_ch0_addr0 + reg_offset);
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writel(ch->cmd_data[i].data, &gis_regs->hw_gis_ch0_data0 + reg_offset);
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}
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}
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static void gis_channel_init(void)
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{
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struct channel_param ch;
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int ret;
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u32 addr0, data0, addr1, data1;
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u32 val;
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/* Restart the GIS block */
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ret = mxs_reset_block(&gis_regs->hw_gis_ctrl_reg);
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if (ret) {
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debug("MXS GIS: Block reset timeout\n");
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return;
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}
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writel((u32)csibuf0, &gis_regs->hw_gis_fb0);
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writel((u32)csibuf1, &gis_regs->hw_gis_fb1);
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writel((u32)fb0, &gis_regs->hw_gis_pxp_fb0);
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writel((u32)fb1, &gis_regs->hw_gis_pxp_fb1);
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/* Config channel 0 -- CSI clean interrupt */
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addr0 = (u32)&csi_regs->csi_csisr;
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data0 = BIT_DMA_TSF_DONE_FB1 | BIT_DMA_TSF_DONE_FB2 | BIT_SOF_INT;
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ch.ch_num = 0;
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ch.ch_map = CH_MAPPING_CSI_ISR;
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ch.cmd_num = 1;
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ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
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ch.cmd_data[0].cmd_bits.alu = ALU_AND;
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ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
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ch.cmd_data[0].data = data0;
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config_channel(&ch);
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/* Config channel 1 -- CSI set next framebuffer addr */
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addr0 = (u32)&csi_regs->csi_csidmasa_fb1;
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data0 = (u32)&csi_regs->csi_csidmasa_fb2;
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ch.ch_num = 1;
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ch.ch_map = CH_MAPPING_CSI_FB_UPDATE;
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ch.cmd_num = 1;
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ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_CSI;
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ch.cmd_data[0].cmd_bits.alu = ALU_AND;
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ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
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ch.cmd_data[0].data = data0;
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config_channel(&ch);
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/* Config channel 2 -- PXP clear interrupt and set framebuffer */
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addr0 = (u32)&pxp_regs->pxp_stat_clr;
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data0 = BM_PXP_STAT_IRQ;
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addr1 = (u32)&pxp_regs->pxp_out_buf;
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data1 = 0;
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ch.ch_num = 2;
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ch.ch_map = CH_MAPPING_PXP_ISR;
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ch.cmd_num = 2;
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ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
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ch.cmd_data[0].cmd_bits.alu = ALU_AND;
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ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
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ch.cmd_data[0].data = data0;
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ch.cmd_data[1].cmd_bits.opcode = CMD_WR_FB_PXP_OUT;
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ch.cmd_data[1].cmd_bits.alu = ALU_AND;
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ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
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ch.cmd_data[1].data = data1;
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config_channel(&ch);
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/* Config channel 3 -- LCDIF set framebuffer to display */
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addr0 = (u32)&lcdif_regs->hw_lcdif_next_buf;
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data0 = 0;
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ch.ch_num = 3;
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ch.ch_map = CH_MAPPING_LCDIF_FB_UPDATE;
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ch.cmd_num = 1;
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ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_LCDIF;
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ch.cmd_data[0].cmd_bits.alu = ALU_AND;
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ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[0].addr = ((lcdif_sel == 0) ? LCDIF0_SEL : LCDIF1_SEL) << GIS_CH_ADDR_SEL_SHIFT | addr0;
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ch.cmd_data[0].data = data0;
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config_channel(&ch);
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/* Config channel 4 -- PXP kick to process next framebuffer */
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addr0 = (u32)&pxp_regs->pxp_ps_buf;
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data0 = 0;
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addr1 = (u32)&pxp_regs->pxp_ctrl;
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data1 = BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE;
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ch.ch_num = 4;
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ch.ch_map = CH_MAPPING_PXP_KICK;
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ch.cmd_num = 2;
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ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_PXP_IN;
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ch.cmd_data[0].cmd_bits.alu = ALU_AND;
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ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
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ch.cmd_data[0].data = data0;
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ch.cmd_data[1].cmd_bits.opcode = CMD_WR_DATA;
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ch.cmd_data[1].cmd_bits.alu = ALU_AND;
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ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
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ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
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ch.cmd_data[1].data = data1;
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config_channel(&ch);
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/* start gis */
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val = readl(&gis_regs->hw_gis_ctrl);
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if (lcdif_sel == 1)
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val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF1;
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else
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val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF0;
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writel(val, &gis_regs->hw_gis_ctrl);
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}
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void mxc_disable_gis(void)
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{
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u32 val;
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if (!gis_running)
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return;
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/* Stop gis */
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val = GIS_CTRL_SFTRST_SET | GIS_CTRL_CLK_GATE_SET;
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writel(val, &gis_regs->hw_gis_ctrl);
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/* Stop pxp */
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mxs_reset_block(&pxp_regs->pxp_ctrl_reg);
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val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE;
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writel(val , &pxp_regs->pxp_ctrl);
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csi_disable();
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vadc_power_down();
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}
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void mxc_enable_gis(void)
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{
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struct sensor_data sensor;
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struct csi_conf_param csi_conf;
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struct pxp_config_data pxp_conf;
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struct display_panel panel;
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u32 csimemsize, pxpmemsize;
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char const *gis_input = env_get("gis");
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gis_regs = (struct mxs_gis_regs *)GIS_BASE_ADDR;
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pxp_regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
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csi_regs = (struct mxs_csi_regs *)CSI1_BASE_ADDR;
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gis_running = false;
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if (!strcmp(gis_input, "vadc")) {
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printf("gis input --- vadc\n");
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/* vadc_in 0 */
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vadc_config(0);
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/* Get vadc mode */
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vadc_get_std(&sensor);
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} else {
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printf("gis input --- No input\n");
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return;
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}
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/* Get display mode */
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mxs_lcd_get_panel(&panel);
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lcdif_regs = (struct mxs_lcdif_regs *)panel.reg_base;
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if (panel.reg_base == LCDIF2_BASE_ADDR)
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lcdif_sel = 1;
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else
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lcdif_sel = 0;
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/* Allocate csi buffer */
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if (sensor.pixel_fmt == FMT_YUV444) {
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csimemsize = sensor.width * sensor.height * 4;
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csi_conf.bpp = 32;
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} else {
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csimemsize = sensor.width * sensor.height * 2;
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csi_conf.bpp = 16;
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}
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pxpmemsize = panel.width * panel.height * panel.gdfbytespp;
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csibuf0 = malloc(csimemsize);
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csibuf1 = malloc(csimemsize);
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fb0 = malloc(pxpmemsize);
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fb1 = malloc(pxpmemsize);
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if (!csibuf0 || !csibuf1 || !fb0 || !fb1) {
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printf("MXSGIS: Error allocating csibuffer!\n");
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return;
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}
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/* Wipe framebuffer */
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memset(csibuf0, 0, csimemsize);
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memset(csibuf1, 0, csimemsize);
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memset(fb0, 0, pxpmemsize);
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memset(fb1, 0, pxpmemsize);
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/*config csi */
|
||||
csi_conf.width = sensor.width;
|
||||
csi_conf.height = sensor.height;
|
||||
csi_conf.btvmode = true;
|
||||
csi_conf.std = sensor.std_id;
|
||||
csi_conf.fb0addr = csibuf0;
|
||||
csi_conf.fb1addr = csibuf1;
|
||||
csi_config(&csi_conf);
|
||||
|
||||
/* config pxp */
|
||||
pxp_conf.s0_param.pixel_fmt = sensor.pixel_fmt;
|
||||
pxp_conf.s0_param.width = sensor.width;
|
||||
pxp_conf.s0_param.height = sensor.height;
|
||||
pxp_conf.s0_param.stride = sensor.width * csi_conf.bpp/8;
|
||||
pxp_conf.s0_param.paddr = csibuf0;
|
||||
|
||||
switch (panel.gdfindex) {
|
||||
case GDF_32BIT_X888RGB:
|
||||
pxp_conf.out_param.pixel_fmt = FMT_RGB888;
|
||||
break;
|
||||
case GDF_16BIT_565RGB:
|
||||
pxp_conf.out_param.pixel_fmt = FMT_RGB565;
|
||||
break;
|
||||
default:
|
||||
printf("GIS unsupported format!");
|
||||
}
|
||||
|
||||
pxp_conf.out_param.width = panel.width;
|
||||
pxp_conf.out_param.height = panel.height;
|
||||
pxp_conf.out_param.stride = pxp_conf.out_param.width * panel.gdfbytespp;
|
||||
pxp_conf.out_param.paddr = fb0;
|
||||
pxp_config(&pxp_conf);
|
||||
|
||||
gis_running = true;
|
||||
|
||||
/* Config gis */
|
||||
gis_channel_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef MXC_GIS_H
|
||||
#define MXC_GIS_H
|
||||
|
||||
#include <asm/mach-imx/regs-common.h>
|
||||
|
||||
struct mxs_gis_regs {
|
||||
mxs_reg_32(hw_gis_ctrl) /* 0x00 */
|
||||
mxs_reg_32(hw_gis_config0) /* 0x10 */
|
||||
mxs_reg_32(hw_gis_config1) /* 0x20 */
|
||||
mxs_reg_32(hw_gis_fb0) /* 0x30 */
|
||||
mxs_reg_32(hw_gis_fb1) /* 0x40 */
|
||||
mxs_reg_32(hw_gis_pxp_fb0) /* 0x50 */
|
||||
mxs_reg_32(hw_gis_pxp_fb1) /* 0x60 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch0_ctrl) /* 0x70 */
|
||||
mxs_reg_32(hw_gis_ch0_addr0) /* 0x80 */
|
||||
mxs_reg_32(hw_gis_ch0_data0) /* 0x90 */
|
||||
mxs_reg_32(hw_gis_ch0_addr1) /* 0xa0 */
|
||||
mxs_reg_32(hw_gis_ch0_data1) /* 0xb0 */
|
||||
mxs_reg_32(hw_gis_ch0_addr2) /* 0xc0 */
|
||||
mxs_reg_32(hw_gis_ch0_data2) /* 0xd0 */
|
||||
mxs_reg_32(hw_gis_ch0_addr3) /* 0xe0 */
|
||||
mxs_reg_32(hw_gis_ch0_data3) /* 0xf0 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch1_ctrl) /* 0x100 */
|
||||
mxs_reg_32(hw_gis_ch1_addr0) /* 0x110 */
|
||||
mxs_reg_32(hw_gis_ch1_data0) /* 0x120 */
|
||||
mxs_reg_32(hw_gis_ch1_addr1) /* 0x130 */
|
||||
mxs_reg_32(hw_gis_ch1_data1) /* 0x140 */
|
||||
mxs_reg_32(hw_gis_ch1_addr2) /* 0x150 */
|
||||
mxs_reg_32(hw_gis_ch1_data2) /* 0x160 */
|
||||
mxs_reg_32(hw_gis_ch1_addr3) /* 0x170 */
|
||||
mxs_reg_32(hw_gis_ch1_data3) /* 0x180 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch2_ctrl) /* 0x190 */
|
||||
mxs_reg_32(hw_gis_ch2_addr0) /* 0x1a0 */
|
||||
mxs_reg_32(hw_gis_ch2_data0) /* 0x1b0 */
|
||||
mxs_reg_32(hw_gis_ch2_addr1) /* 0x1c0 */
|
||||
mxs_reg_32(hw_gis_ch2_data1) /* 0x1d0 */
|
||||
mxs_reg_32(hw_gis_ch2_addr2) /* 0x1e0 */
|
||||
mxs_reg_32(hw_gis_ch2_data2) /* 0x1f0 */
|
||||
mxs_reg_32(hw_gis_ch2_addr3) /* 0x200 */
|
||||
mxs_reg_32(hw_gis_ch2_data3) /* 0x210 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch3_ctrl) /* 0x220 */
|
||||
mxs_reg_32(hw_gis_ch3_addr0) /* 0x230 */
|
||||
mxs_reg_32(hw_gis_ch3_data0) /* 0x240 */
|
||||
mxs_reg_32(hw_gis_ch3_addr1) /* 0x250 */
|
||||
mxs_reg_32(hw_gis_ch3_data1) /* 0x260 */
|
||||
mxs_reg_32(hw_gis_ch3_addr2) /* 0x270 */
|
||||
mxs_reg_32(hw_gis_ch3_data2) /* 0x280 */
|
||||
mxs_reg_32(hw_gis_ch3_addr3) /* 0x290 */
|
||||
mxs_reg_32(hw_gis_ch3_data3) /* 0x2a0 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch4_ctrl) /* 0x2b0 */
|
||||
mxs_reg_32(hw_gis_ch4_addr0) /* 0x2c0 */
|
||||
mxs_reg_32(hw_gis_ch4_data0) /* 0x2d0 */
|
||||
mxs_reg_32(hw_gis_ch4_addr1) /* 0x2e0 */
|
||||
mxs_reg_32(hw_gis_ch4_data1) /* 0x2f0 */
|
||||
mxs_reg_32(hw_gis_ch4_addr2) /* 0x300 */
|
||||
mxs_reg_32(hw_gis_ch4_data2) /* 0x310 */
|
||||
mxs_reg_32(hw_gis_ch4_addr3) /* 0x320 */
|
||||
mxs_reg_32(hw_gis_ch4_data3) /* 0x330 */
|
||||
|
||||
mxs_reg_32(hw_gis_ch5_ctrl) /* 0x340 */
|
||||
mxs_reg_32(hw_gis_ch5_addr0) /* 0x350 */
|
||||
mxs_reg_32(hw_gis_ch5_data0) /* 0x360 */
|
||||
mxs_reg_32(hw_gis_ch5_addr1) /* 0x370 */
|
||||
mxs_reg_32(hw_gis_ch5_data1) /* 0x380 */
|
||||
mxs_reg_32(hw_gis_ch5_addr2) /* 0x390 */
|
||||
mxs_reg_32(hw_gis_ch5_data2) /* 0x3a0 */
|
||||
mxs_reg_32(hw_gis_ch5_addr3) /* 0x3b0 */
|
||||
mxs_reg_32(hw_gis_ch5_data3) /* 0x3c0 */
|
||||
|
||||
mxs_reg_32(hw_gis_debug0) /* 0x3d0 */
|
||||
mxs_reg_32(hw_gis_debug1) /* 0x3e0 */
|
||||
mxs_reg_32(hw_gis_version) /* 0x3f0 */
|
||||
};
|
||||
|
||||
/* register bit */
|
||||
#define GIS_CTRL_SFTRST_CLR 0
|
||||
#define GIS_CTRL_SFTRST_SET (1 << 31)
|
||||
#define GIS_CTRL_CLK_GATE_CLR 0
|
||||
#define GIS_CTRL_CLK_GATE_SET (1 << 30)
|
||||
#define GIS_CTRL_LCDIF1_IRQ_POL_LOW 0
|
||||
#define GIS_CTRL_LCDIF1_IRQ_POL_HIGH (1 << 8)
|
||||
#define GIS_CTRL_LCDIF0_IRQ_POL_LOW 0
|
||||
#define GIS_CTRL_LCDIF0_IRQ_POL_HIGH (1 << 7)
|
||||
#define GIS_CTRL_PXP_IRQ_POL_LOW 0
|
||||
#define GIS_CTRL_PXP_IRQ_POL_HIGH (1 << 6)
|
||||
#define GIS_CTRL_CSI1_IRQ_POL_LOW 0
|
||||
#define GIS_CTRL_CSI1_IRQ_POL_HIGH (1 << 5)
|
||||
#define GIS_CTRL_CSI0_IRQ_POL_LOW 0
|
||||
#define GIS_CTRL_CSI0_IRQ_POL_HIGH (1 << 4)
|
||||
#define GIS_CTRL_CSI_SEL_CSI0 0
|
||||
#define GIS_CTRL_CSI_SEL_CSI1 (1 << 3)
|
||||
#define GIS_CTRL_LCDIF_SEL_LCDIF0 0
|
||||
#define GIS_CTRL_LCDIF_SEL_LCDIF1 (1 << 2)
|
||||
#define GIS_CTRL_FB_START_FB0 0
|
||||
#define GIS_CTRL_FB_START_FB1 (1 << 1)
|
||||
#define GIS_CTRL_ENABLE_CLR 0
|
||||
#define GIS_CTRL_ENABLE_SET (1 << 0)
|
||||
|
||||
#define GIS_CONFIG0_CH3_NUM_MASK (0x7 << 27)
|
||||
#define GIS_CONFIG0_CH3_NUM_SHIFT 27
|
||||
#define GIS_CONFIG0_CH3_MAPPING_MASK (0x7 << 24)
|
||||
#define GIS_CONFIG0_CH3_MAPPING_SHIFT 24
|
||||
#define GIS_CONFIG0_CH2_NUM_MASK (0x7 << 19)
|
||||
#define GIS_CONFIG0_CH2_NUM_SHIFT 19
|
||||
#define GIS_CONFIG0_CH2_MAPPING_MASK (0x7 << 16)
|
||||
#define GIS_CONFIG0_CH2_MAPPING_SHIFT 16
|
||||
#define GIS_CONFIG0_CH1_NUM_MASK (0x7 << 11)
|
||||
#define GIS_CONFIG0_CH1_NUM_SHIFT 11
|
||||
#define GIS_CONFIG0_CH1_MAPPING_MASK (0x7 << 8)
|
||||
#define GIS_CONFIG0_CH1_MAPPING_SHIFT 8
|
||||
#define GIS_CONFIG0_CH0_NUM_MASK (0x7 << 3)
|
||||
#define GIS_CONFIG0_CH0_NUM_SHIFT 3
|
||||
#define GIS_CONFIG0_CH0_MAPPING_MASK (0x7 << 0)
|
||||
#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0
|
||||
|
||||
#define GIS_CONFIG1_CH5_NUM_MASK (0x7 << 11)
|
||||
#define GIS_CONFIG1_CH5_NUM_SHIFT 11
|
||||
#define GIS_CONFIG1_CH5_MAPPING_MASK (0x7 << 8)
|
||||
#define GIS_CONFIG1_CH5_MAPPING_SHIFT 8
|
||||
#define GIS_CONFIG1_CH4_NUM_MASK (0x7 << 3)
|
||||
#define GIS_CONFIG1_CH4_NUM_SHIFT 3
|
||||
#define GIS_CONFIG1_CH4_MAPPING_MASK (0x7 << 0)
|
||||
#define GIS_CONFIG1_CH4_MAPPING_SHIFT 0
|
||||
|
||||
#define GIS_CH_CTRL_CMD3_ACC_MASK (0x1 << 31)
|
||||
#define GIS_CH_CTRL_CMD3_ACC_SHIFT 31
|
||||
#define GIS_CH_CTRL_CMD3_ALU_MASK (0x7 << 28)
|
||||
#define GIS_CH_CTRL_CMD3_ALU_SHIFT 28
|
||||
#define GIS_CH_CTRL_CMD3_OPCODE_MASK (0xF << 24)
|
||||
#define GIS_CH_CTRL_CMD3_OPCODE_SHIFT 24
|
||||
#define GIS_CH_CTRL_CMD2_ACC_MASK (0x1 << 23)
|
||||
#define GIS_CH_CTRL_CMD2_ACC_SHIFT 23
|
||||
#define GIS_CH_CTRL_CMD2_ALU_MASK (0xF << 20)
|
||||
#define GIS_CH_CTRL_CMD2_ALU_SHIFT 20
|
||||
#define GIS_CH_CTRL_CMD2_OPCODE_MASK (0xF << 16)
|
||||
#define GIS_CH_CTRL_CMD2_OPCODE_SHIFT 16
|
||||
#define GIS_CH_CTRL_CMD1_ACC_MASK (0x1 << 15)
|
||||
#define GIS_CH_CTRL_CMD1_ACC_SHIFT 15
|
||||
#define GIS_CH_CTRL_CMD1_ALU_MASK (0x7 << 12)
|
||||
#define GIS_CH_CTRL_CMD1_ALU_SHIFT 12
|
||||
#define GIS_CH_CTRL_CMD1_OPCODE_MASK (0xF << 8)
|
||||
#define GIS_CH_CTRL_CMD1_OPCODE_SHIFT 8
|
||||
#define GIS_CH_CTRL_CMD0_ACC_MASK (0x1 << 7)
|
||||
#define GIS_CH_CTRL_CMD0_ACC_SHIFT 7
|
||||
#define GIS_CH_CTRL_CMD0_ALU_MASK (0x7 << 4)
|
||||
#define GIS_CH_CTRL_CMD0_ALU_SHIFT 4
|
||||
#define GIS_CH_CTRL_CMD0_OPCODE_MASK (0xF << 0)
|
||||
#define GIS_CH_CTRL_CMD0_OPCODE_SHIFT 0
|
||||
|
||||
#define GIS_CH_CTRL_CMD_ACC_NO_NEGATE 0
|
||||
#define GIS_CH_CTRL_CMD_ACC_NEGATE 1
|
||||
|
||||
#define GIS_CH_ADDR_SEL_MASK (0xF8 << 27)
|
||||
#define GIS_CH_ADDR_SEL_LCDIF1 (0x1 << 31)
|
||||
#define GIS_CH_ADDR_SEL_LCDIF0 (0x1 << 30)
|
||||
#define GIS_CH_ADDR_SEL_PXP (0x1 << 29)
|
||||
#define GIS_CH_ADDR_SEL_CSI1 (0x1 << 28)
|
||||
#define GIS_CH_ADDR_SEL_CSI0 (0x1 << 27)
|
||||
#define GIS_CH_ADDR_SEL_SHIFT 27
|
||||
#define GIS_CH_ADDR_ADDR_MASK 0x7FFFFFF
|
||||
#define GIS_CH_ADDR_ADDR_SHIFT 0
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -25,6 +25,9 @@
|
|||
#include <linux/fb.h>
|
||||
#include <mxsfb.h>
|
||||
|
||||
#ifdef CONFIG_VIDEO_GIS
|
||||
#include <gis.h>
|
||||
#endif
|
||||
|
||||
#define PS2KHZ(ps) (1000000000UL / (ps))
|
||||
|
||||
|
|
@ -291,5 +294,10 @@ void *video_hw_init(void)
|
|||
mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_GIS
|
||||
/* Entry for GIS */
|
||||
mxc_enable_gis();
|
||||
#endif
|
||||
|
||||
return (void *)&panel;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef GIS_H
|
||||
#define GIS_H
|
||||
|
||||
#define FMT_YUV444 0
|
||||
#define FMT_YUYV 1
|
||||
#define FMT_UYVY 2
|
||||
#define FMT_RGB565 3
|
||||
#define FMT_RGB888 4
|
||||
|
||||
void mxc_enable_gis(void);
|
||||
void mxc_disable_gis(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -4788,8 +4788,10 @@ CONFIG_VIDEO_BMP_GZIP
|
|||
CONFIG_VIDEO_BMP_LOGO
|
||||
CONFIG_VIDEO_BMP_RLE8
|
||||
CONFIG_VIDEO_CORALP
|
||||
CONFIG_VIDEO_CSI
|
||||
CONFIG_VIDEO_DA8XX
|
||||
CONFIG_VIDEO_FONT_4X6
|
||||
CONFIG_VIDEO_GIS
|
||||
CONFIG_VIDEO_LCD_I2C_BUS
|
||||
CONFIG_VIDEO_LOGO
|
||||
CONFIG_VIDEO_MB862xx
|
||||
|
|
@ -4798,7 +4800,9 @@ CONFIG_VIDEO_MX3
|
|||
CONFIG_VIDEO_MXS
|
||||
CONFIG_VIDEO_MXS_MODE_SYSTEM
|
||||
CONFIG_VIDEO_OMAP3
|
||||
CONFIG_VIDEO_PXP
|
||||
CONFIG_VIDEO_STD_TIMINGS
|
||||
CONFIG_VIDEO_VADC
|
||||
CONFIG_VIDEO_VCXK
|
||||
CONFIG_VID_FLS_ENV
|
||||
CONFIG_VM86
|
||||
|
|
|
|||
Loading…
Reference in New Issue