rockchip: gru: Add extra device-tree settings
Add some U-Boot-specific settings. These should really go in the *u-boot.dtsi file, but it seems that rk3399 does not use that yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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			@ -7,6 +7,7 @@
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/dts-v1/;
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#include "rk3399-gru-chromebook.dtsi"
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#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
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/ {
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	model = "Google Bob";
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			@ -232,6 +232,7 @@
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&edp {
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	status = "okay";
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	rockchip,panel = <&edp_panel>;
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	ports {
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		edp_out: port@1 {
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			reg = <1>;
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			@ -11,7 +11,13 @@
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/ {
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	chosen {
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		u-boot,dm-pre-reloc;
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		stdout-path = "serial2:115200n8";
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		u-boot,spl-boot-order = &spi_flash;
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	};
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	config {
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		u-boot,spl-payload-offset = <0x40000>;
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	};
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	/*
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			@ -539,12 +545,14 @@ ap_i2c_audio: &i2c8 {
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&spi1 {
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	status = "okay";
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	u-boot,dm-pre-reloc;
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	pinctrl-names = "default", "sleep";
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	pinctrl-1 = <&spi1_sleep>;
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	spiflash@0 {
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		compatible = "jedec,spi-nor";
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	spi_flash: spiflash@0 {
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		u-boot,dm-pre-reloc;
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		compatible = "jedec,spi-nor", "spi-flash";
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		reg = <0>;
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		/* May run faster once verified. */
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			@ -558,12 +566,16 @@ ap_i2c_audio: &i2c8 {
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&spi5 {
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	status = "okay";
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	spi-activate-delay = <100>;
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	spi-max-frequency = <3000000>;
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	spi-deactivate-delay = <200>;
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	cros_ec: ec@0 {
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		compatible = "google,cros-ec-spi";
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		reg = <0>;
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		interrupt-parent = <&gpio0>;
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		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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		ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>;
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		pinctrl-names = "default";
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		pinctrl-0 = <&ec_ap_int_l>;
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		spi-max-frequency = <3000000>;
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			@ -618,6 +630,7 @@ ap_i2c_audio: &i2c8 {
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&uart2 {
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	status = "okay";
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	u-boot,dm-pre-reloc;
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};
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&usb_host0_ohci {
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			@ -650,8 +663,8 @@ ap_i2c_audio: &i2c8 {
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	status = "okay";
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};
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#include <arm/cros-ec-keyboard.dtsi>
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#include <arm/cros-ec-sbs.dtsi>
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#include <cros-ec-keyboard.dtsi>
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#include <cros-ec-sbs.dtsi>
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&pinctrl {
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	/*
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