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phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified 

commit 75b6cd97dd41b11c212fccf545e346c38248f8a2 upstream.

It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.

Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
This commit is contained in:
Sinthu Raja 2023-03-13 18:12:23 +05:30 committed by Praneeth Bajjuri
parent b18ebbe325
commit 0937ed1b00
1 changed files with 29 additions and 9 deletions
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38
drivers/phy/ti/phy-j721e-wiz.c
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@ -329,6 +329,7 @@ struct wiz {
u32 num_lanes; u32 num_lanes;
struct gpio_desc *gpio_typec_dir; struct gpio_desc *gpio_typec_dir;
u32 lane_phy_type[WIZ_MAX_LANES]; u32 lane_phy_type[WIZ_MAX_LANES];
u32 master_lane_num[WIZ_MAX_LANES];
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
unsigned int id; unsigned int id;
const struct wiz_data *data; const struct wiz_data *data;
@ -586,14 +587,31 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
return ret; return ret;
/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
if (id == 0 && wiz->gpio_typec_dir) { if (id == 0) {
if (dm_gpio_get_value(wiz->gpio_typec_dir)) { if (wiz->gpio_typec_dir) {
regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
WIZ_SERDES_TYPEC_LN10_SWAP, regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
WIZ_SERDES_TYPEC_LN10_SWAP); WIZ_SERDES_TYPEC_LN10_SWAP,
} else { WIZ_SERDES_TYPEC_LN10_SWAP);
regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC, } else {
WIZ_SERDES_TYPEC_LN10_SWAP, 0); regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
WIZ_SERDES_TYPEC_LN10_SWAP, 0);
}
}
} else {
/* if no typec-dir gpio was specified and PHY type is
* USB3 with master lane number is '0', set LN10 SWAP
* bit to '1'
*/
u32 num_lanes = wiz->num_lanes;
int i;
for (i = 0; i < num_lanes; i++) {
if (wiz->lane_phy_type[i] == PHY_TYPE_USB3)
if (wiz->master_lane_num[i] == 0)
regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
WIZ_SERDES_TYPEC_LN10_SWAP,
WIZ_SERDES_TYPEC_LN10_SWAP);
} }
} }
@ -1100,8 +1118,10 @@ static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
reg, reg + num_lanes - 1, phy_type); reg, reg + num_lanes - 1, phy_type);
for (i = reg; i < reg + num_lanes; i++) for (i = reg; i < reg + num_lanes; i++) {
wiz->lane_phy_type[i] = phy_type; wiz->lane_phy_type[i] = phy_type;
wiz->master_lane_num[i] = reg;
}
} }
return 0; return 0;