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stm32mp1: ram: increase the delay after reset to 128 cycles 

Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2019-04-10 14:09:22 +02:00 committed by Patrice Chotard
parent c3ec370aed
commit 0cb1aa9409
1 changed files with 3 additions and 5 deletions
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8
drivers/ram/stm32mp1/stm32mp1_ddr.c
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@ -401,11 +401,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
*/ */
clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
/* 1.4. wait 4 cycles for synchronization */ /* 1.4. wait 128 cycles to permit initialization of end logic */
asm(" nop"); udelay(2);
asm(" nop"); /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
asm(" nop");
asm(" nop");
/* 1.5. initialize registers ddr_umctl2 */ /* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */ /* Stop uMCTL2 before PHY is ready */