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arm: dra76: Add support for ES1.0 detection 

dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN

Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Praneeth Bajjuri 2017-08-21 12:50:52 +05:30 committed by Tom Rini
parent 0537e097c9
commit 0f9e6aee9d
4 changed files with 39 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -58,6 +58,7 @@
#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F

8
arch/arm/include/asm/omap_common.h
View File

@ -722,6 +722,7 @@ static inline u8 is_omap54xx(void)
#define DRA7XX 0x07000000
#define DRA72X 0x07200000
#define DRA76X 0x07600000
static inline u8 is_dra7xx(void)
{
@ -734,6 +735,12 @@ static inline u8 is_dra72x(void)
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA72X;
}
static inline u8 is_dra76x(void)
{
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA76X;
}
#endif
/*
@ -761,6 +768,7 @@ static inline u8 is_dra72x(void)
#define OMAP5432_ES2_0 0x54320200
/* DRA7XX */
#define DRA762_ES1_0 0x07620100
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200

27
arch/arm/mach-omap2/omap5/hw_data.c
View File

@ -113,6 +113,16 @@ static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
{96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@ -234,6 +244,17 @@ struct dplls omap5_dplls_es2 = {
.ddr = NULL
};
struct dplls dra76x_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
.per = per_dpll_params_768mhz_dra76x,
.abe = abe_dpll_params_sysclk2_361267khz,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2664mhz,
.gmac = gmac_dpll_params_2000mhz,
};
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
@ -709,6 +730,12 @@ void __weak hw_data_init(void)
*ctrl = &omap5_ctrl;
break;
case DRA762_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra76x_dplls;
*ctrl = &dra7xx_ctrl;
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:

3
arch/arm/mach-omap2/omap5/hwinit.c
View File

@ -362,6 +362,9 @@ void init_omap_revision(void)
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
case DRA762_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA762_ES1_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA752_ES1_0;
break;