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net: zynq: Add support for PHY configuration in SGMII mode 

SGMII configuration depends on proper GT setting that's why when node has
phys property call PSGTR driver to configure it properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/bbc8d7ed9d308199168e4455c7a3e3a5ac0890e7.1639562397.git.michal.simek@xilinx.com
This commit is contained in:
Michal Simek 2021-12-15 11:00:01 +01:00
parent b5ffc9f758
commit 10c50b1fac
1 changed files with 20 additions and 0 deletions
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20
drivers/net/zynq_gem.c
View File

@ -12,6 +12,7 @@
#include <common.h> #include <common.h>
#include <cpu_func.h> #include <cpu_func.h>
#include <dm.h> #include <dm.h>
#include <generic-phy.h>
#include <log.h> #include <log.h>
#include <net.h> #include <net.h>
#include <netdev.h> #include <netdev.h>
@ -713,6 +714,19 @@ static int zynq_gem_probe(struct udevice *dev)
void *bd_space; void *bd_space;
struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_priv *priv = dev_get_priv(dev);
int ret; int ret;
struct phy phy;
if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
ret = generic_phy_get_by_index(dev, 0, &phy);
if (!ret) {
ret = generic_phy_init(&phy);
if (ret)
return ret;
} else if (ret != -ENOENT) {
debug("could not get phy (err %d)\n", ret);
return ret;
}
}
ret = zynq_gem_reset_init(dev); ret = zynq_gem_reset_init(dev);
if (ret) if (ret)
@ -769,6 +783,12 @@ static int zynq_gem_probe(struct udevice *dev)
if (ret) if (ret)
goto err3; goto err3;
if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
ret = generic_phy_power_on(&phy);
if (ret)
return ret;
}
return ret; return ret;
err3: err3: