arm: dts: k3-j784s4: Enable WKUP_GPIO6 for SW3.1

SW3.1 is a physical switch muxing between OSPI NOR and OSPI NAND.
SW3.1 is connected to the wkup_gpio0_6 pin. Enable the support for
wkup_gpio0_6 for adding OSPI dual flash support.

Signed-off-by: Apurva Nandan <a-nandan@ti.com>
This commit is contained in:
Apurva Nandan 2023-10-07 04:31:29 +05:30 committed by Udit Kumar
parent 252c052e50
commit 12322dac6c
3 changed files with 32 additions and 0 deletions

View File

@ -192,6 +192,14 @@
bootph-pre-ram;
};
&wkup_gpio_pins_default {
bootph-pre-ram;
};
&wkup_gpio0 {
bootph-pre-ram;
};
&ospi0 {
bootph-pre-ram;

View File

@ -334,6 +334,11 @@
>;
};
wkup_gpio_pins_default: wkup_gpio_pins_default {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 7) /* (L37) WKUP_GPIO0_6 */
>;
};
};
&wkup_pmx0 {
@ -748,6 +753,12 @@
};
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

View File

@ -107,6 +107,14 @@
};
};
&wkup_pmx2 {
bootph-pre-ram;
wkup_gpio_pins_default: wkup_gpio_pins_default {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 7) /* (L37) WKUP_GPIO0_6 */
>;
};
};
&sms {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
@ -171,6 +179,11 @@
maximum-speed = "super-speed";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&ospi0 {
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;