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imx8m: lock id_swap_bypass bit in tzc380 enable 

According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
order to avoid AXI bus errors when GPU is enabled on the platform.
TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
derivatives, but is missing a lock settings to be applied.

Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
it implemented.

Since we're here, provide also names to bits from TRM instead of using
BIT() macro in the code.

Fixes: deca6cfbf5 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors")
Fixes: a07c718129 ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Andrey Zhizhikin 2022-01-24 21:48:09 +01:00 committed by Stefano Babic
parent 3113861beb
commit 1289ff7bd7
2 changed files with 18 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -81,7 +81,9 @@
#include <stdbool.h> #include <stdbool.h>
#define GPR_TZASC_EN BIT(0) #define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
#define GPR_TZASC_EN_LOCK BIT(16) #define GPR_TZASC_EN_LOCK BIT(16)
#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
#define SRC_SCR_M4_ENABLE_OFFSET 3 #define SRC_SCR_M4_ENABLE_OFFSET 3
#define SRC_SCR_M4_ENABLE_MASK BIT(3) #define SRC_SCR_M4_ENABLE_MASK BIT(3)

15
arch/arm/mach-imx/imx8m/soc.c
View File

@ -66,8 +66,21 @@ void enable_tzc380(void)
/* Enable TZASC and lock setting */ /* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
/*
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
if (is_imx8mm() || is_imx8mn() || is_imx8mp()) if (is_imx8mm() || is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], BIT(1)); setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
* imx8mn and imx8mp implements the lock bit for
* TZASC_ID_SWAP_BYPASS, enable it to lock settings
*/
if (is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
/* /*
* set Region 0 attribute to allow secure and non-secure * set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3 * read/write permission. Found some masters like usb dwc3