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arm64: zynqmp: Describe TI phy as ethernet-phy-id 

TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset. Reset description will be added in separate commit.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2022-09-09 13:05:48 +02:00
parent 0fb7fd865b
commit 13622c7a9d
6 changed files with 73 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -200,7 +200,12 @@
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@21 { phy0: ethernet-phy@21 {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <21>; reg = <21>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
@ -208,6 +213,7 @@
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
}; };
};
}; };
&gpio { &gpio {

6
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -109,13 +109,19 @@
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>; ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
}; };
};
}; };
&gpio { &gpio {

6
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -114,13 +114,19 @@
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>; ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
}; };
};
}; };
&gpio { &gpio {

6
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -172,13 +172,19 @@
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>; pinctrl-0 = <&pinctrl_gem3_default>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>; ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
}; };
};
}; };
&gpio { &gpio {

6
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -169,13 +169,19 @@
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>; ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
}; };
};
}; };
&gpio { &gpio {

7
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -176,15 +176,20 @@
status = "okay"; status = "okay";
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@c { phy0: ethernet-phy@c {
#phy-cells = <1>;
compatible = "ethernet-phy-id2000.a231";
reg = <0xc>; reg = <0xc>;
ti,rx-internal-delay = <0x8>; ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>; ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>; ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk; ti,dp83867-rxctrl-strap-quirk;
}; };
};
}; };
&gpio { &gpio {
status = "okay"; status = "okay";
gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */