MLK-18325 imx8mm_evk: add pmic BD71837/BD71840 support in spl

Since default values of some registers of pmic not match well our board
design, add BD71837/BD71840 pmic support in spl, for example, RESET key
(PWRON_B) pushing time, VDD_DRAM too low for 3Ghz DDR.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

arch/arm/include/asm/arch-imx8m/imx8mm_pins.h

@@ -607,11 +607,11 @@ enum {
          IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
          IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13                              =  IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
 
-         IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0, 0x0000, 0, 0),
+         IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
          IMX8MM_PAD_I2C1_SCL_ENET1_MDC                                 =  IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
          IMX8MM_PAD_I2C1_SCL_GPIO5_IO14                                =  IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
 
-         IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0, 0x0000, 0, 0),
+         IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
          IMX8MM_PAD_I2C1_SDA_ENET1_MDIO                                =  IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
          IMX8MM_PAD_I2C1_SDA_GPIO5_IO15                                =  IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
 

board/freescale/imx8mm_evk/imx8mm_evk.c

@@ -379,34 +379,3 @@ int board_late_init(void)
 
 	return 0;
 }
-
-#ifdef CONFIG_POWER
-#define I2C_PMIC	0
-int power_init_board(void)
-{
-	struct pmic *p;
-	int ret;
-	unsigned int reg;
-
-	return 0;
-
-	ret = power_bd71837_init(I2C_PMIC);
-	if (ret)
-		printf("power init failed");
-
-	p = pmic_get("BD71837");
-	pmic_probe(p);
-
-#if 0
-	/* unlock the PMIC regs */
-	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
-
-	/* Set BUCK5 output for DRAM to 1.0V */
-	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
-
-	/* lock the PMIC regs */
-	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
-#endif
-	return 0;
-}
-#endif

board/freescale/imx8mm_evk/spl.c

@@ -13,8 +13,7 @@
 #include <asm/arch/imx8mm_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
+#include <power/bd71837.h>
-#include "../common/pfuze.h"
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
@@ -30,6 +29,21 @@ void spl_dram_init(void)
 	ddr_init();
 }
 
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 18)
 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
 
@@ -143,12 +157,45 @@ int board_mmc_getcd(struct mmc *mmc)
 	return 1;
 }
 
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
+
+	/* increase VDD_DRAM to 0.9v for 3Ghz DDR */
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+
+	return 0;
+}
+#endif
 
 void spl_board_init(void)
 {
 	/* TODO */
 	/* enable_tzc380(); */
 
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
 	/* DDR initialization */
 	spl_dram_init();
 

include/configs/imx8mm_evk.h

@@ -46,6 +46,10 @@
 #undef CONFIG_DM_PMIC
 #undef CONFIG_DM_PMIC_PFUZE100
 
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_BD71837
+
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */