spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This commit is contained in:
Nobuhiro Iwamatsu
Jagannadha Sutradharudu Teki
parent
57af475389
commit
16f47c9c51
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@ -0,0 +1,38 @@
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-------------------------------------------------
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Simple steps used to test the SH-QSPI at U-Boot
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-------------------------------------------------
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#0, Currently, SH-QSPI is used by lager board (Renesas ARM SoC R8A7790)
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and koelsch board (Renesas ARM SoC R8A7791). These boot from SPI ROM
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basically. Thus, U-Boot start, SH-QSPI will is operating normally.
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#1, build U-Boot and load u-boot.bin
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=> tftpboot 40000000 u-boot.bin
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sh_eth Waiting for PHY auto negotiation to complete.. done
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sh_eth: 100Base/Half
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Using sh_eth device
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TFTP from server 192.168.169.1; our IP address is 192.168.169.79
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Filename 'u-boot.bin'.
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Load address: 0x40000000
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Loading: ############
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2.5 MiB/s
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done
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Bytes transferred = 175364 (2ad04 hex)
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#2, Commands to erase/write u-boot to flash device
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Note: This method is description of the lager board. If you want to use the
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other boards, please change the value according to each environment.
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=> sf probe 0
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SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 64 KiB, total 64 MiB
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=> sf erase 80000 40000
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SF: 262144 bytes @ 0x80000 Erased: OK
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=> sf write 40000000 80000 175364
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SF: 1528676 bytes @ 0x80000 Written: OK
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=>
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#3, Push reset button.
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If you're written correctly and driver works properly, U-Boot starts.
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@ -30,6 +30,7 @@ obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
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obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
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obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
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obj-$(CONFIG_SOFT_SPI) += soft_spi.o
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obj-$(CONFIG_SOFT_SPI) += soft_spi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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obj-$(CONFIG_FDT_SPI) += fdt_spi.o
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obj-$(CONFIG_FDT_SPI) += fdt_spi.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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@ -0,0 +1,277 @@
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/*
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* SH QSPI (Quad SPI) driver
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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/* SH QSPI register bit masks <REG>_<BIT> */
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#define SPCR_MSTR 0x08
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#define SPCR_SPE 0x40
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#define SPSR_SPRFF 0x80
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#define SPSR_SPTEF 0x20
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#define SPPCR_IO3FV 0x04
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#define SPPCR_IO2FV 0x02
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#define SPPCR_IO1FV 0x01
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#define SPBDCR_RXBC0 (1 << 0)
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#define SPCMD_SCKDEN (1 << 15)
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#define SPCMD_SLNDEN (1 << 14)
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#define SPCMD_SPNDEN (1 << 13)
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#define SPCMD_SSLKP (1 << 7)
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#define SPCMD_BRDV0 (1 << 2)
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#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
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SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPBFCR_TXRST (1 << 7)
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#define SPBFCR_RXRST (1 << 6)
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/* SH QSPI register set */
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struct sh_qspi_regs {
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unsigned char spcr;
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unsigned char sslp;
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unsigned char sppcr;
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unsigned char spsr;
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unsigned long spdr;
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unsigned char spscr;
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unsigned char spssr;
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unsigned char spbr;
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unsigned char spdcr;
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unsigned char spckd;
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unsigned char sslnd;
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unsigned char spnd;
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unsigned char dummy0;
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unsigned short spcmd0;
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unsigned short spcmd1;
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unsigned short spcmd2;
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unsigned short spcmd3;
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unsigned char spbfcr;
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unsigned char dummy1;
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unsigned short spbdcr;
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unsigned long spbmul0;
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unsigned long spbmul1;
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unsigned long spbmul2;
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unsigned long spbmul3;
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};
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struct sh_qspi_slave {
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struct spi_slave slave;
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struct sh_qspi_regs *regs;
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};
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static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
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{
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return container_of(slave, struct sh_qspi_slave, slave);
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}
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static void sh_qspi_init(struct sh_qspi_slave *ss)
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{
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/* QSPI initialize */
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/* Set master mode only */
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writeb(SPCR_MSTR, &ss->regs->spcr);
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/* Set SSL signal level */
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writeb(0x00, &ss->regs->sslp);
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/* Set MOSI signal value when transfer is in idle state */
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writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
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/* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
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writeb(0x01, &ss->regs->spbr);
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/* Disable Dummy Data Transmission */
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writeb(0x00, &ss->regs->spdcr);
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/* Set clock delay value */
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writeb(0x00, &ss->regs->spckd);
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/* Set SSL negation delay value */
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writeb(0x00, &ss->regs->sslnd);
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/* Set next-access delay value */
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writeb(0x00, &ss->regs->spnd);
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/* Set equence command */
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writew(SPCMD_INIT2, &ss->regs->spcmd0);
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/* Reset transfer and receive Buffer */
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setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Clear transfer and receive Buffer control bit */
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clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Set equence control method. Use equence0 only */
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writeb(0x00, &ss->regs->spscr);
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/* Enable SPI function */
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setbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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/* Set master mode only */
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writeb(SPCR_MSTR, &ss->regs->spcr);
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/* Set command */
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writew(SPCMD_INIT1, &ss->regs->spcmd0);
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/* Reset transfer and receive Buffer */
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setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Clear transfer and receive Buffer control bit */
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clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
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/* Set equence control method. Use equence0 only */
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writeb(0x00, &ss->regs->spscr);
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/* Enable SPI function */
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setbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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/* Disable SPI Function */
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clrbits_8(&ss->regs->spcr, SPCR_SPE);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct sh_qspi_slave *ss;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
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if (!ss) {
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printf("SPI_error: Fail to allocate sh_qspi_slave\n");
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return NULL;
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}
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ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
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/* Init SH QSPI */
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sh_qspi_init(ss);
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return &ss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct sh_qspi_slave *spi = to_sh_qspi(slave);
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free(spi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct sh_qspi_slave *ss = to_sh_qspi(slave);
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unsigned long nbyte;
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int ret = 0;
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unsigned char dtdata = 0, drdata;
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unsigned char *tdata = &dtdata, *rdata = &drdata;
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unsigned long *spbmul0 = &ss->regs->spbmul0;
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if (dout == NULL && din == NULL) {
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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if (bitlen % 8) {
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printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
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return 1;
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}
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nbyte = bitlen / 8;
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if (flags & SPI_XFER_BEGIN) {
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spi_cs_activate(slave);
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/* Set 1048576 byte */
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writel(0x100000, spbmul0);
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}
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if (flags & SPI_XFER_END)
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writel(nbyte, spbmul0);
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if (dout != NULL)
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tdata = (unsigned char *)dout;
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if (din != NULL)
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rdata = din;
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while (nbyte > 0) {
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while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) {
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if (ctrlc()) {
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puts("abort\n");
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return 1;
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}
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udelay(10);
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}
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writeb(*tdata, (unsigned char *)(&ss->regs->spdr));
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while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) {
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if (ctrlc()) {
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puts("abort\n");
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return 1;
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}
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udelay(1);
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}
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while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) {
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if (ctrlc()) {
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puts("abort\n");
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return 1;
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}
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udelay(10);
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}
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*rdata = readb((unsigned char *)(&ss->regs->spdr));
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if (dout != NULL)
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tdata++;
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if (din != NULL)
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rdata++;
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nbyte--;
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return ret;
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}
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