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Get MPC8641HPCN flash images working. 

Enable the CFI driver.
    Remove bogus LAWBAR7 cruft.
    Use correct TEXT_BASE, Fixup load script.
    Enable SPD EEPROM during DDR setup.
    Use generic RFC 1918 IP addresses by default.
This commit is contained in:
Jon Loeliger 2006-05-09 08:23:49 -05:00
parent 5c9efb36a6
commit 18b6c8cd8a
4 changed files with 17 additions and 37 deletions
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3
board/mpc8641hpcn/config.mk
View File

@ -25,8 +25,7 @@
# default CCSRBAR is at 0xff700000 # default CCSRBAR is at 0xff700000
# assume U-Boot is less than 0.5MB # assume U-Boot is less than 0.5MB
# #
#TEXT_BASE = 0xfff01000 TEXT_BASE = 0xfff01000
TEXT_BASE = 0x00400000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float

17
board/mpc8641hpcn/init.S
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@ -80,23 +80,6 @@
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
/*
* Rapid IO at 0xc000_0000 for 512 M
*/
/*
#ifdef CFG_INIT_RAM_LOCK
#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
#endif
*/
/*
* Stack at 0xfc00_0000 for 32M on LBC
*/
#if !defined(CFG_INIT_RAM_LOCK)
#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff)
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#endif
.section .bootpg, "ax" .section .bootpg, "ax"
.globl law_entry .globl law_entry
law_entry: law_entry:

4
board/mpc8641hpcn/u-boot.lds
View File

@ -28,7 +28,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
__DYNAMIC = 0; */ __DYNAMIC = 0; */
SECTIONS SECTIONS
{ {
/* .resetvec 0xFFF00100 : .resetvec 0xFFF00100 :
{ {
*(.resetvec) *(.resetvec)
} = 0xffff } = 0xffff
@ -38,7 +38,7 @@ SECTIONS
cpu/mpc86xx/start.o (.bootpg) cpu/mpc86xx/start.o (.bootpg)
board/mpc8641hpcn/init.o (.bootpg) board/mpc8641hpcn/init.o (.bootpg)
} = 0xffff } = 0xffff
*/
/* Read-only sections, merged into text segment: */ /* Read-only sections, merged into text segment: */
. = + 1024; . = + 1024;
.interp : { *(.interp) } .interp : { *(.interp) }

30
include/configs/MPC8641HPCN.h
View File

@ -51,6 +51,7 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC /* only for ECC DDR module */
@ -102,11 +103,9 @@
#else #else
/* /*
* Manually set up DDR parameters * Manually set up DDR1 parameters
*/ */
/* DDR I */
#if 1
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
#define CFG_DDR_CS0_BNDS 0x0000000F #define CFG_DDR_CS0_BNDS 0x0000000F
@ -125,15 +124,14 @@
#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
#define CFG_DDR_CONTROL2 0x04400000 #define CFG_DDR_CONTROL2 0x04400000
//Not used in fixed_sdram function /* Not used in fixed_sdram function */
#define CFG_DDR_MODE 0x00000022 #define CFG_DDR_MODE 0x00000022
#define CFG_DDR_CS1_BNDS 0x00000000 #define CFG_DDR_CS1_BNDS 0x00000000
#define CFG_DDR_CS2_BNDS 0x00000FFF //Not done #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS3_BNDS 0x00000FFF //Not done #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS4_BNDS 0x00000FFF //Not done #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS5_BNDS 0x00000FFF //Not done #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
#endif
#endif #endif
@ -190,6 +188,7 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI #define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_EMPTY_INFO
@ -199,14 +198,14 @@
#undef CFG_RAMBOOT #undef CFG_RAMBOOT
#endif #endif
#if !defined(CFG_RAMBOOT) #if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#endif #endif
#undef CONFIG_CLOCKS_IN_MHZ #undef CONFIG_CLOCKS_IN_MHZ
#define CONFIG_L1_INIT_RAM #define CONFIG_L1_INIT_RAM
#undef CFG_INIT_RAM_LOCK #define CFG_INIT_RAM_LOCK 1
#ifndef CFG_INIT_RAM_LOCK #ifndef CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
#else #else
@ -540,22 +539,21 @@
#define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH2 1
#define CONFIG_HAS_ETH3 1 #define CONFIG_HAS_ETH3 1
#define CONFIG_IPADDR 10.82.193.138 #define CONFIG_IPADDR 192.168.1.100
#define CONFIG_HOSTNAME unknown #define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage #define CONFIG_BOOTFILE uImage
#define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 10.82.193.104 #define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
/* default location for tftp and bootm */ /* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000 #define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200