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hw25: configure secondary pinmux for RMII2_CRS_DV 

BugzId: 66001
This commit is contained in:
Marcel Reichmuth 2020-10-30 13:38:07 +01:00
parent 511c34bec1
commit 18d916b414
1 changed files with 9 additions and 0 deletions
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9
board/nm/hw25/board.c
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@ -109,6 +109,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define DDR3_CLOCK_FREQUENCY (400)
#define REG_CONTROL_MODULE_SMA2 (CTRL_BASE + 0x000011320)
#define REG_CONTROL_MODULE_SMA2_RMII2_CRS_DV_MODE_SEL (0x00000001)
#if !defined(CONFIG_SPL_BUILD)
/* Hardware version information of mainboard, loaded by get_hw_version() */
@ -1021,6 +1023,13 @@ int board_eth_init(bd_t *bis)
cpsw_data.mdio_div = 0x3E;
/* The RMII2_CRS_DV on GPMC_A9 can also be used as MMC2_DAT7.
For both functions the pin must be in pinmux mode 3.
The default function is MMC2_DAT7, therefore we need to
change it to RMII2_CRS_DV using a secondary pinmux
that is controlled via control module register sma2. */
writel(REG_CONTROL_MODULE_SMA2_RMII2_CRS_DV_MODE_SEL, REG_CONTROL_MODULE_SMA2);
bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
set_mac_address(0, mac_addr0);