MLK-18459-2 mx6sll_arm2: Add LPDDR2/LPDDR3 ARM2 support
Porting the iMX6SLL LPDDR2/LPPDR3 ARM2 board codes from v2017.03. Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
parent
0879e6cbc0
commit
18fbe50f43
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@ -336,6 +336,13 @@ config TARGET_MX6SLLEVK
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select DM
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select DM_THERMAL
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config TARGET_MX6SLL_ARM2
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bool "mx6sll arm2"
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select BOARD_LATE_INIT
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select MX6SLL
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select DM
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select DM_THERMAL
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config TARGET_MX6SXSABRESD
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bool "mx6sxsabresd"
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select BOARD_LATE_INIT
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@ -586,6 +593,7 @@ source "board/freescale/mx6memcal/Kconfig"
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source "board/freescale/mx6sabreauto/Kconfig"
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source "board/freescale/mx6sabresd/Kconfig"
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source "board/freescale/mx6slevk/Kconfig"
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source "board/freescale/mx6sll_arm2/Kconfig"
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source "board/freescale/mx6sllevk/Kconfig"
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source "board/freescale/mx6sxsabresd/Kconfig"
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source "board/freescale/mx6sxsabreauto/Kconfig"
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@ -0,0 +1,18 @@
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if TARGET_MX6SLL_ARM2
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config SYS_BOARD
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default "mx6sll_arm2"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "mx6sll_arm2"
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config LPDDR2_BOARD
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bool "set if the board uses the LPDDR2 not default LPDDR3"
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config SYS_TEXT_BASE
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default 0x87800000
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endif
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@ -0,0 +1,6 @@
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# (C) Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6sll_arm2.o
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@ -0,0 +1,127 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E0550 0x00080000
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DATA 4 0x020E0534 0x00000000
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DATA 4 0x020E02AC 0x00000030
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DATA 4 0x020E0548 0x00000030
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DATA 4 0x020E052C 0x00000030
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DATA 4 0x020E0530 0x00020000
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DATA 4 0x020E02B0 0x00003030
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DATA 4 0x020E02B4 0x00003030
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DATA 4 0x020E02B8 0x00003030
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DATA 4 0x020E02BC 0x00003030
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DATA 4 0x020E0540 0x00020000
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DATA 4 0x020E0544 0x00000030
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DATA 4 0x020E054C 0x00000030
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DATA 4 0x020E0554 0x00000030
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DATA 4 0x020E0558 0x00000030
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DATA 4 0x020E0294 0x00000030
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DATA 4 0x020E0298 0x00000030
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DATA 4 0x020E029C 0x00000030
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DATA 4 0x020E02A0 0x00000030
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DATA 4 0x020E02C0 0x00082030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B085c 0x084700C7
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DATA 4 0x021B0890 0x00400000
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DATA 4 0x021B0848 0x3C3A3C3C
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DATA 4 0x021B0850 0x24293625
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B0824 0x33333333
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DATA 4 0x021B0828 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B0834 0xf3333333
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DATA 4 0x021B0838 0xf3333333
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DATA 4 0x021B08C0 0x24922492
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x00020052
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DATA 4 0x021B000C 0x53574333
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DATA 4 0x021B0010 0x00100B22
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DATA 4 0x021B0038 0x00170778
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DATA 4 0x021B0014 0x00C700DB
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DATA 4 0x021B0018 0x00201718
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DATA 4 0x021B002C 0x0F9F26D2
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DATA 4 0x021B0030 0x009F0E10
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DATA 4 0x021B0040 0x0000005F
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DATA 4 0x021B0000 0xC4190000
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DATA 4 0x021B001C 0x00008050
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DATA 4 0x021B001C 0x00008058
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DATA 4 0x021B001C 0x003F8030
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DATA 4 0x021B001C 0x003F8038
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DATA 4 0x021B001C 0xFF0A8030
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DATA 4 0x021B001C 0xFF0A8038
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DATA 4 0x021B001C 0x04028030
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DATA 4 0x021B001C 0x04028038
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DATA 4 0x021B001C 0x83018030
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DATA 4 0x021B001C 0x83018038
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DATA 4 0x021B001C 0x01038030
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DATA 4 0x021B001C 0x01038038
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DATA 4 0x021B083C 0x20000000
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DATA 4 0x021B0020 0x00001800
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B0004 0x00020052
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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#endif
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@ -0,0 +1,127 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx6sll_arm2/plugin.bin 0x00907000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E0550 0x00080000
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DATA 4 0x020E0534 0x00000000
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DATA 4 0x020E02AC 0x00000030
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DATA 4 0x020E0548 0x00000030
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DATA 4 0x020E052C 0x00000030
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DATA 4 0x020E0530 0x00020000
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DATA 4 0x020E02B0 0x00003030
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DATA 4 0x020E02B4 0x00003030
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DATA 4 0x020E02B8 0x00003030
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DATA 4 0x020E02BC 0x00003030
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DATA 4 0x020E0540 0x00020000
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DATA 4 0x020E0544 0x00000030
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DATA 4 0x020E054C 0x00000030
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DATA 4 0x020E0554 0x00000030
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DATA 4 0x020E0558 0x00000030
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DATA 4 0x020E0294 0x00000030
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DATA 4 0x020E0298 0x00000030
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DATA 4 0x020E029C 0x00000030
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DATA 4 0x020E02A0 0x00000030
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DATA 4 0x020E02C0 0x00082030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B085c 0x084700C7
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DATA 4 0x021B0890 0x00400000
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DATA 4 0x021B0848 0x3A383C40
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DATA 4 0x021B0850 0x242C3020
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B0824 0x33333333
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DATA 4 0x021B0828 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B0834 0xf3333333
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DATA 4 0x021B0838 0xf3333333
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DATA 4 0x021B08C0 0x24922492
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x00020052
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DATA 4 0x021B000C 0x53574333
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DATA 4 0x021B0010 0x00100A82
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DATA 4 0x021B0038 0x00170777
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DATA 4 0x021B0014 0x00C70093
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DATA 4 0x021B0018 0x00201708
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DATA 4 0x021B002C 0x0F9F26D2
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DATA 4 0x021B0030 0x009F0E10
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DATA 4 0x021B0040 0x0000004F
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DATA 4 0x021B0000 0xC3110000
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DATA 4 0x021B001C 0x00008050
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DATA 4 0x021B001C 0x00008058
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DATA 4 0x021B001C 0x003F8030
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DATA 4 0x021B001C 0x003F8038
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DATA 4 0x021B001C 0xFF0A8030
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DATA 4 0x021B001C 0xFF0A8038
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DATA 4 0x021B001C 0x04028030
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DATA 4 0x021B001C 0x04028038
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DATA 4 0x021B001C 0x82018030
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DATA 4 0x021B001C 0x82018038
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DATA 4 0x021B001C 0x01038030
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DATA 4 0x021B001C 0x01038038
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DATA 4 0x021B083C 0x20000000
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DATA 4 0x021B0020 0x00001800
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B0004 0x00020052
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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#endif
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@ -0,0 +1,755 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-mx6/clock.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <linux/sizes.h>
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#include <linux/fb.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <mxsfb.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#if defined(CONFIG_MXC_EPDC)
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#include <lcd.h>
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#include <mxc_epdc_fb.h>
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#endif
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#include <asm/mach-imx/video.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#ifdef CONFIG_SYS_I2C
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC and EPD */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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/* conflict with usb_otg2_pwr */
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.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC,
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.gp = IMX_GPIO_NR(3, 12),
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},
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.sda = {
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/* conflict with usb_otg2_oc */
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.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC,
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.gp = IMX_GPIO_NR(3, 13),
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},
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};
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/* I2C2 for LCD and ADV */
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC,
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.gp = IMX_GPIO_NR(3, 14),
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},
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.sda = {
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.i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC,
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.gp = IMX_GPIO_NR(3, 15),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const led_pads[] = {
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MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* 8bit SD1 */
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* CD */
|
||||
MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* WP */
|
||||
MX6_PAD_GPIO4_IO22__SD1_WP | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* EMMC */
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* DQS */
|
||||
MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* RST_B */
|
||||
MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE),
|
||||
};
|
||||
|
||||
/* Wifi SD */
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
/* CD */
|
||||
MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(uart1_pads);
|
||||
|
||||
SETUP_IOMUX_PADS(led_pads);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8, 1},
|
||||
{USDHC2_BASE_ADDR, 0, 8, 0, 1}, /* fixed 1.8v IO voltage for eMMC chip */
|
||||
{USDHC3_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 27)
|
||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
* mmc2 USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
SETUP_IOMUX_PADS(usdhc1_pads);
|
||||
gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
SETUP_IOMUX_PADS(usdhc2_pads);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
break;
|
||||
case 2:
|
||||
SETUP_IOMUX_PADS(usdhc3_pads);
|
||||
gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
static struct pmic *pfuze;
|
||||
int power_init_board(void)
|
||||
{
|
||||
int ret;
|
||||
u32 rev_id, value;
|
||||
|
||||
ret = power_pfuze100_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pfuze = pmic_get("PFUZE100");
|
||||
if (!pfuze)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pmic_probe(pfuze);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pfuze_mode_init(pfuze, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
|
||||
pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
|
||||
|
||||
/* set SW1AB standby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
|
||||
value &= ~0x3f;
|
||||
value |= PFUZE100_SW1ABC_SETP(9750);
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
|
||||
|
||||
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
|
||||
value &= ~0xc0;
|
||||
value |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
|
||||
|
||||
/* set SW1C staby volatage 0.975V */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
|
||||
value &= ~0x3f;
|
||||
value |= 0x1b;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
|
||||
|
||||
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
|
||||
pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
|
||||
value &= ~0xc0;
|
||||
value |= 0x40;
|
||||
pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_DM_PMIC_PFUZE100)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
dev = pfuze_common_init();
|
||||
if (!dev)
|
||||
return -ENODEV;
|
||||
|
||||
ret = pfuze_mode_init(dev, APS_PFM);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS0 */
|
||||
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(ecspi1_pads);
|
||||
gpio_request(IMX_GPIO_NR(4, 11), "escpi cs");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 11), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = enable_lcdif_clock(dev->bus, 1);
|
||||
if (ret) {
|
||||
printf("Enable LCDIF clock failed, %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
SETUP_IOMUX_PADS(lcd_pads);
|
||||
|
||||
/* Reset the LCD */
|
||||
gpio_request(IMX_GPIO_NR(2, 19), "lcd reset");
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 19) , 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 19) , 1);
|
||||
|
||||
gpio_request(IMX_GPIO_NR(4, 8), "lcd pwr en");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 8) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_request(IMX_GPIO_NR(3, 23), "backlight");
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 23) , 1);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = MX6SLL_LCDIF_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_EPDC
|
||||
static iomux_v3_cfg_t const epdc_enable_pads[] = {
|
||||
MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const epdc_disable_pads[] = {
|
||||
MX6_PAD_EPDC_DATA01__GPIO1_IO08,
|
||||
MX6_PAD_EPDC_DATA02__GPIO1_IO09,
|
||||
MX6_PAD_EPDC_DATA03__GPIO1_IO10,
|
||||
MX6_PAD_EPDC_DATA04__GPIO1_IO11,
|
||||
MX6_PAD_EPDC_DATA05__GPIO1_IO12,
|
||||
MX6_PAD_EPDC_DATA06__GPIO1_IO13,
|
||||
MX6_PAD_EPDC_DATA07__GPIO1_IO14,
|
||||
MX6_PAD_EPDC_DATA08__GPIO1_IO15,
|
||||
MX6_PAD_EPDC_DATA09__GPIO1_IO16,
|
||||
MX6_PAD_EPDC_DATA10__GPIO1_IO17,
|
||||
MX6_PAD_EPDC_DATA11__GPIO1_IO18,
|
||||
MX6_PAD_EPDC_DATA12__GPIO1_IO19,
|
||||
MX6_PAD_EPDC_DATA13__GPIO1_IO20,
|
||||
MX6_PAD_EPDC_DATA14__GPIO1_IO21,
|
||||
MX6_PAD_EPDC_DATA15__GPIO1_IO22,
|
||||
MX6_PAD_EPDC_SDCLK__GPIO1_IO23,
|
||||
MX6_PAD_EPDC_SDLE__GPIO1_IO24,
|
||||
MX6_PAD_EPDC_SDOE__GPIO1_IO25,
|
||||
MX6_PAD_EPDC_SDSHR__GPIO1_IO26,
|
||||
MX6_PAD_EPDC_SDCE0__GPIO1_IO27,
|
||||
MX6_PAD_EPDC_GDCLK__GPIO1_IO31,
|
||||
MX6_PAD_EPDC_GDOE__GPIO2_IO00,
|
||||
MX6_PAD_EPDC_GDRL__GPIO2_IO01,
|
||||
MX6_PAD_EPDC_GDSP__GPIO2_IO02,
|
||||
};
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_refresh = 85,
|
||||
.vl_col = 1024,
|
||||
.vl_row = 758,
|
||||
.vl_pixclock = 40000000,
|
||||
.vl_left_margin = 12,
|
||||
.vl_right_margin = 76,
|
||||
.vl_upper_margin = 4,
|
||||
.vl_lower_margin = 5,
|
||||
.vl_hsync = 12,
|
||||
.vl_vsync = 2,
|
||||
.vl_sync = 0,
|
||||
.vl_mode = 0,
|
||||
.vl_flag = 0,
|
||||
.vl_bpix = 3,
|
||||
.cmap = 0,
|
||||
};
|
||||
|
||||
struct epdc_timing_params panel_timings = {
|
||||
.vscan_holdoff = 4,
|
||||
.sdoed_width = 10,
|
||||
.sdoed_delay = 20,
|
||||
.sdoez_width = 10,
|
||||
.sdoez_delay = 20,
|
||||
.gdclk_hp_offs = 524,
|
||||
.gdsp_offs = 327,
|
||||
.gdoe_offs = 0,
|
||||
.gdclk_offs = 19,
|
||||
.num_ce = 1,
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
|
||||
IOMUX_PADS(PAD_EPDC_PWR_STAT__GPIO2_IO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EPDC_VCOM0__GPIO2_IO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EPDC_PWR_WAKE__GPIO2_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static void setup_epdc_power(void)
|
||||
{
|
||||
SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
|
||||
/* Setup epdc voltage */
|
||||
|
||||
/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
|
||||
gpio_request(IMX_GPIO_NR(2, 13), "EPDC_PWRSTAT");
|
||||
gpio_direction_input(IMX_GPIO_NR(2, 13));
|
||||
|
||||
/* EPDC_VCOM0 - GPIO2[03] for VCOM control */
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(2, 3), "EPDC_VCOM0");
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
|
||||
|
||||
/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(2, 14), "EPDC_PWRWAKEUP");
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
|
||||
|
||||
/* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(2, 7), "EPDC_PWRCTRL0");
|
||||
gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
|
||||
}
|
||||
|
||||
static void epdc_enable_pins(void)
|
||||
{
|
||||
/* epdc iomux settings */
|
||||
SETUP_IOMUX_PADS(epdc_enable_pads);
|
||||
}
|
||||
|
||||
static void epdc_disable_pins(void)
|
||||
{
|
||||
/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
|
||||
SETUP_IOMUX_PADS(epdc_disable_pads);
|
||||
}
|
||||
|
||||
static void setup_epdc(void)
|
||||
{
|
||||
/* Set pixel clock rates for EPDC in clock.c */
|
||||
|
||||
panel_info.epdc_data.wv_modes.mode_init = 0;
|
||||
panel_info.epdc_data.wv_modes.mode_du = 1;
|
||||
panel_info.epdc_data.wv_modes.mode_gc4 = 3;
|
||||
panel_info.epdc_data.wv_modes.mode_gc8 = 2;
|
||||
panel_info.epdc_data.wv_modes.mode_gc16 = 2;
|
||||
panel_info.epdc_data.wv_modes.mode_gc32 = 2;
|
||||
|
||||
panel_info.epdc_data.epdc_timings = panel_timings;
|
||||
|
||||
setup_epdc_power();
|
||||
}
|
||||
|
||||
void epdc_power_on(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
|
||||
|
||||
/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 7), 1);
|
||||
udelay(1000);
|
||||
|
||||
/* Enable epdc signal pin */
|
||||
epdc_enable_pins();
|
||||
|
||||
/* Set PMIC Wakeup to high - enable Display power */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
|
||||
|
||||
/* Wait for PWRGOOD == 1 */
|
||||
while (1) {
|
||||
reg = readl(&gpio_regs->gpio_psr);
|
||||
if (!(reg & (1 << 13)))
|
||||
break;
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* Enable VCOM */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 3), 1);
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
void epdc_power_off(void)
|
||||
{
|
||||
/* Set PMIC Wakeup to low - disable Display power */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 14), 0);
|
||||
|
||||
/* Disable VCOM */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 3), 0);
|
||||
|
||||
epdc_disable_pins();
|
||||
|
||||
/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
|
||||
gpio_set_value(IMX_GPIO_NR(2, 7), 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#ifndef CONFIG_DM_USB
|
||||
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_KEY_ROW4__USB_OTG1_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX6_PAD_KEY_COL5__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
switch (port) {
|
||||
case 0:
|
||||
SETUP_IOMUX_PADS(usb_otg1_pads);
|
||||
break;
|
||||
case 1:
|
||||
SETUP_IOMUX_PADS(usb_otg2_pads);
|
||||
break;
|
||||
default:
|
||||
printf("MXC USB port %d not yet supported\n", port);
|
||||
return 1;
|
||||
}
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
enable_uart_clk(true);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_EPDC
|
||||
enable_epdc_clock();
|
||||
setup_epdc();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
SETUP_IOMUX_PADS(wdog_pads);
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_LPDDR2_BOARD
|
||||
puts("Board: MX6SLL LPDDR2 ARM2\n");
|
||||
#else
|
||||
puts("Board: MX6SLL LPDDR3 ARM2\n");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx6sll_lpddr3_arm2_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x00080000
|
||||
str r1, [r0, #0x550]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x534]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x2AC]
|
||||
str r1, [r0, #0x548]
|
||||
str r1, [r0, #0x52C]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x530]
|
||||
ldr r1, =0x00003030
|
||||
str r1, [r0, #0x2B0]
|
||||
str r1, [r0, #0x2B4]
|
||||
str r1, [r0, #0x2B8]
|
||||
str r1, [r0, #0x2BC]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x540]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x544]
|
||||
str r1, [r0, #0x54C]
|
||||
str r1, [r0, #0x554]
|
||||
str r1, [r0, #0x558]
|
||||
str r1, [r0, #0x294]
|
||||
str r1, [r0, #0x298]
|
||||
str r1, [r0, #0x29C]
|
||||
str r1, [r0, #0x2A0]
|
||||
|
||||
ldr r1, =0x00082030
|
||||
str r1, [r0, #0x2C0]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x1C]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x084700C7
|
||||
str r1, [r0, #0x85C]
|
||||
ldr r1, =0x00400000
|
||||
str r1, [r0, #0x890]
|
||||
|
||||
ldr r1, =0x3C3A3C3C
|
||||
str r1, [r0, #0x848]
|
||||
ldr r1, =0x24293625
|
||||
str r1, [r0, #0x850]
|
||||
|
||||
ldr r1, =0x33333333
|
||||
str r1, [r0, #0x81C]
|
||||
str r1, [r0, #0x820]
|
||||
str r1, [r0, #0x824]
|
||||
str r1, [r0, #0x828]
|
||||
|
||||
ldr r1, =0xf3333333
|
||||
str r1, [r0, #0x82C]
|
||||
str r1, [r0, #0x830]
|
||||
str r1, [r0, #0x834]
|
||||
str r1, [r0, #0x838]
|
||||
|
||||
ldr r1, =0x24922492
|
||||
str r1, [r0, #0x8C0]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8B8]
|
||||
|
||||
ldr r1, =0x00020052
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x53574333
|
||||
str r1, [r0, #0x00C]
|
||||
ldr r1, =0x00100B22
|
||||
str r1, [r0, #0x010]
|
||||
ldr r1, =0x00170778
|
||||
str r1, [r0, #0x038]
|
||||
ldr r1, =0x00C700DB
|
||||
str r1, [r0, #0x014]
|
||||
ldr r1, =0x00201718
|
||||
str r1, [r0, #0x018]
|
||||
ldr r1, =0x0F9F26D2
|
||||
str r1, [r0, #0x02C]
|
||||
ldr r1, =0x009F0E10
|
||||
str r1, [r0, #0x030]
|
||||
ldr r1, =0x0000005F
|
||||
str r1, [r0, #0x040]
|
||||
ldr r1, =0xC4190000
|
||||
str r1, [r0, #0x000]
|
||||
|
||||
ldr r1, =0x00008050
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00008058
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x003F8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x003F8038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0xFF0A8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0xFF0A8038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04028030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04028038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x83018030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x83018038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x01038030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x01038038
|
||||
str r1, [r0, #0x01C]
|
||||
|
||||
ldr r1, =0x20000000
|
||||
str r1, [r0, #0x83C]
|
||||
|
||||
ldr r1, =0x00001800
|
||||
str r1, [r0, #0x020]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x00020052
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00011006
|
||||
str r1, [r0, #0x404]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x01C]
|
||||
.endm
|
||||
|
||||
.macro imx6sll_lpddr2_arm2_setting
|
||||
ldr r0, =IOMUXC_BASE_ADDR
|
||||
ldr r1, =0x00080000
|
||||
str r1, [r0, #0x550]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x534]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x2AC]
|
||||
str r1, [r0, #0x548]
|
||||
str r1, [r0, #0x52C]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x530]
|
||||
ldr r1, =0x00003030
|
||||
str r1, [r0, #0x2B0]
|
||||
str r1, [r0, #0x2B4]
|
||||
str r1, [r0, #0x2B8]
|
||||
str r1, [r0, #0x2BC]
|
||||
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0x540]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x544]
|
||||
str r1, [r0, #0x54C]
|
||||
str r1, [r0, #0x554]
|
||||
str r1, [r0, #0x558]
|
||||
str r1, [r0, #0x294]
|
||||
str r1, [r0, #0x298]
|
||||
str r1, [r0, #0x29C]
|
||||
str r1, [r0, #0x2A0]
|
||||
|
||||
ldr r1, =0x00082030
|
||||
str r1, [r0, #0x2C0]
|
||||
|
||||
ldr r0, =MMDC_P0_BASE_ADDR
|
||||
ldr r1, =0x00008000
|
||||
str r1, [r0, #0x1C]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x084700C7
|
||||
str r1, [r0, #0x85C]
|
||||
ldr r1, =0x00400000
|
||||
str r1, [r0, #0x890]
|
||||
|
||||
ldr r1, =0x3A383C40
|
||||
str r1, [r0, #0x848]
|
||||
ldr r1, =0x242C3020
|
||||
str r1, [r0, #0x850]
|
||||
|
||||
ldr r1, =0x33333333
|
||||
str r1, [r0, #0x81C]
|
||||
str r1, [r0, #0x820]
|
||||
str r1, [r0, #0x824]
|
||||
str r1, [r0, #0x828]
|
||||
|
||||
ldr r1, =0xf3333333
|
||||
str r1, [r0, #0x82C]
|
||||
str r1, [r0, #0x830]
|
||||
str r1, [r0, #0x834]
|
||||
str r1, [r0, #0x838]
|
||||
|
||||
ldr r1, =0x24922492
|
||||
str r1, [r0, #0x8C0]
|
||||
ldr r1, =0x00000800
|
||||
str r1, [r0, #0x8B8]
|
||||
|
||||
ldr r1, =0x00020052
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x53574333
|
||||
str r1, [r0, #0x00C]
|
||||
ldr r1, =0x00100A82
|
||||
str r1, [r0, #0x010]
|
||||
ldr r1, =0x00170777
|
||||
str r1, [r0, #0x038]
|
||||
ldr r1, =0x00C70093
|
||||
str r1, [r0, #0x014]
|
||||
ldr r1, =0x00201708
|
||||
str r1, [r0, #0x018]
|
||||
ldr r1, =0x0F9F26D2
|
||||
str r1, [r0, #0x02C]
|
||||
ldr r1, =0x009F0E10
|
||||
str r1, [r0, #0x030]
|
||||
ldr r1, =0x0000004F
|
||||
str r1, [r0, #0x040]
|
||||
ldr r1, =0xC3110000
|
||||
str r1, [r0, #0x000]
|
||||
|
||||
ldr r1, =0x00008050
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x00008058
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x003F8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x003F8038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0xFF0A8030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0xFF0A8038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04028030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x04028038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x82018030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x82018038
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x01038030
|
||||
str r1, [r0, #0x01C]
|
||||
ldr r1, =0x01038038
|
||||
str r1, [r0, #0x01C]
|
||||
|
||||
ldr r1, =0x20000000
|
||||
str r1, [r0, #0x83C]
|
||||
|
||||
ldr r1, =0x00001800
|
||||
str r1, [r0, #0x020]
|
||||
ldr r1, =0xA1390003
|
||||
str r1, [r0, #0x800]
|
||||
ldr r1, =0x00020052
|
||||
str r1, [r0, #0x004]
|
||||
ldr r1, =0x00011006
|
||||
str r1, [r0, #0x404]
|
||||
ldr r1, =0x00000000
|
||||
str r1, [r0, #0x01C]
|
||||
.endm
|
||||
.macro imx6_clock_gating
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0xffffffff
|
||||
str r1, [r0, #0x068]
|
||||
str r1, [r0, #0x06c]
|
||||
str r1, [r0, #0x070]
|
||||
str r1, [r0, #0x074]
|
||||
str r1, [r0, #0x078]
|
||||
str r1, [r0, #0x07c]
|
||||
str r1, [r0, #0x080]
|
||||
.endm
|
||||
|
||||
.macro imx6_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx6_ddr_setting
|
||||
#if defined (CONFIG_LPDDR2_BOARD)
|
||||
imx6sll_lpddr2_arm2_setting
|
||||
#else
|
||||
imx6sll_lpddr3_arm2_setting
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx6_plugin.S>
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright 2013-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6SL EVK board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
|
||||
/* I2C Configs */
|
||||
#ifndef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#ifndef CONFIG_DM_PMIC
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
#endif
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"epdc_waveform=epdc_splash.bin\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"usb start; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M)
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#ifdef CONFIG_LPDDR2_BOARD
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
#else
|
||||
#define PHYS_SDRAM_SIZE SZ_2G
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Environment organization */
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (896 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#endif
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#define CONFIG_IOMUX_LPSR
|
||||
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
|
||||
|
||||
/*#define CONFIG_MXC_EPDC 1*/
|
||||
|
||||
/*
|
||||
* EPDC SPLASH SCREEN Configs
|
||||
*/
|
||||
#ifdef CONFIG_MXC_EPDC
|
||||
/*
|
||||
* Framebuffer and LCD
|
||||
*/
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#undef LCD_TEST_PATTERN
|
||||
#define LCD_BPP LCD_MONOCHROME
|
||||
|
||||
#define CONFIG_WAVEFORM_BUF_SIZE 0x200000
|
||||
#endif /* CONFIG_MXC_EPDC */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue