diff --git a/board/nm/nrhw20/board.c b/board/nm/nrhw20/board.c
index cf7ce889a8..9df873cacd 100644
--- a/board/nm/nrhw20/board.c
+++ b/board/nm/nrhw20/board.c
@@ -40,6 +40,11 @@
 #include "shield_comio.h"
 #include "fileaccess.h"
 
+
+/* TODO: place in proper header file */
+extern void serial_set_console_index(int index);
+
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -133,7 +138,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IOEXT_LEDS_ALL_MASK		(0x03FF)
 
 
-
 #define DDR3_CLOCK_FREQUENCY		(400)
 
 
@@ -305,21 +309,24 @@ static inline int __maybe_unused read_eeprom(void)
  */
 struct serial_device *default_serial_console(void)
 {
-	/* Mux pins for selected UART properly. 
-	 * Note: uart indexes start at 0 while 
-	 * eserial indexes start at 1. 
+	/*
+	 * Mux pins for selected UART properly. 
+	 * Note: UART indexes start at 0 while eserial indexes start at 1. 
+	 * 
+	 * Provide console on internal UART1 regardless of boot mode.
+	 * This only has a side effect when using X-Modem boot
 	 */
-
-	if ((spl_boot_device() == BOOT_DEVICE_UART) || 
-		(spl_boot_device() == BOOT_DEVICE_JTAG)) {
+	if (spl_boot_device() == BOOT_DEVICE_UART) {
+		/* Continue booting from UART in case of serial (xmodem) boot */
 		enable_uart0_pin_mux();
 		return &eserial1_device;
 	} else {
 		/* Use bluetooth uart, if no ouput shall be seen. */
 		/* TODO: Sorry, what are we doing here.... */
 		/* This is at least dangerous if not completely wrong */
-		enable_uart5_pin_mux();
-		return &eserial6_device;
+		/* TODO: Using UART1 for moment until it is clear what to do */
+		enable_uart1_pin_mux();
+		return &eserial2_device;
 	}
 }
 
@@ -371,8 +378,6 @@ static void init_pmic_spl(void)
 
 	bus = da9063_claim_i2c_bus();
 
-	/* TODO: Move to init_pmic_spl() */
-	
 	/* Configure default PMIC current limits. Will be overridden in Linux.
 	 * MEM   = 1.5A (0.55A)
 	 * IO    = 1.5A (0.5A)
@@ -394,10 +399,6 @@ static void init_pmic_spl(void)
 	(void)da9063_set_reg(PMIC_REG_BMEM_CONF, 0x81);
 	(void)da9063_set_reg(PMIC_REG_BPERI_CONF, 0x81);
 
-	/* TODO: Enable later */
-	/* da9063_reset_reason_update(RESET_REASON_SHM_LOCATION); */
-	/* TODO: Move code from below to here */
-
 	/* Enable charging of RTC backup capacitor (1mA, 3.1V) */
 	(void)da9063_set_reg(PMIC_REG_BBAT_CONT, 0xCF);
 	/* TODO: Check documentation 1 mA correct ? */
@@ -405,6 +406,62 @@ static void init_pmic_spl(void)
 	da9063_release_i2c_bus(bus);
 }
 
+struct reset_registers {
+	uint32_t value;
+	uint32_t value_crc;
+};
+
+#ifdef CONFIG_NRSW
+
+/* TODO: Move ethernet crc to dedicated file */
+static uint32_t ether_crc(size_t len, uint8_t const *p)
+{
+	uint32_t crc;
+	unsigned i;
+
+	crc = ~0;
+	while (len--) {
+		crc ^= *p++;
+		for (i = 0; i < 8; i++)
+			crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+	}
+
+	/* an reverse the bits, cuz of way they arrive -- last-first */
+	crc = (crc >> 16) | (crc << 16);
+	crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
+	crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
+	crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
+	crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
+	
+	return crc;
+}
+
+void check_pmic_reset_reason(unsigned int reset_reason_shm_location)
+{
+	volatile struct reset_registers* reset_regs = (struct reset_registers*)reset_reason_shm_location;
+	uint8_t state = 0x00;
+	int bus;
+	int ret;
+
+	bus = da9063_claim_i2c_bus();
+
+	ret = da9063_get_reg(PMIC_REG_FAULT_LOG, &state);
+	if ((ret == 0) && (state != 0)) {
+		if (state & PMIC_FAULT_TWD_ERROR_MASK) {
+			reset_regs->value = EXTERNAL_WATCHDOG_PATTERN;
+			reset_regs->value_crc = ether_crc(sizeof(reset_regs->value), 
+							 (const uint8_t*)&(reset_regs->value));
+		}
+
+		/* clear pmic fault log by writing back all bits currently set */
+		da9063_set_reg(PMIC_REG_FAULT_LOG, state);
+	}
+
+	da9063_release_i2c_bus(bus);
+}
+
+#endif
+
 void am33xx_spl_board_init(void)
 {
 	/* Set CPU speed to 600 MHz (fix) */
@@ -428,6 +485,11 @@ void am33xx_spl_board_init(void)
 	/* Set MPU Frequency to what we detected now that voltages are set */
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 
+#ifdef CONFIG_NRSW
+	/* TODO: Move to board_late_init? It is not urgent to have this in SPL. */
+	check_pmic_reset_reason(RESET_REASON_SHM_LOCATION);
+#endif
+
 	/* Debugger can place marker at end of SRAM to stop boot here */
 	if (is_jtag_boot(CONFIG_JTAG_MARKER_SPL))
 	{
@@ -643,10 +705,6 @@ int board_init(void)
 
 #if !defined(CONFIG_SPL_BUILD)
 
-/* TODO: Move to top of file or place into header file */
-extern int console_init_f(void);
-extern void serial_set_console_index(int index);
-
 /*
  * Set Linux console based on
  * - Selection in /root/boot/consoledev
@@ -736,8 +794,10 @@ static void get_variant_name(void)
 
 static void get_hw_version(void)
 {
+#ifdef CONFIG_NRSW
 	char hw_versions[16];
 	char new_env[256];	/* current bootargs = 84 bytes */
+#endif
 
 	bd_get_hw_version(&hw_ver, &hw_rev);
 	bd_get_hw_patch(&hw_patch);
@@ -745,10 +805,12 @@ static void get_hw_version(void)
 	printf("HW20:  V%d.%d\n", hw_ver, hw_rev);
 
 	/* TODO: Check if this can be removed eventually */
+#ifdef CONFIG_NRSW
 	/* add hardware versions to environment */
 	snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
 	snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
 	setenv("add_version_bootargs", new_env);
+#endif
 }
 
 static void get_pmic_version(void)
@@ -846,20 +908,20 @@ static void shield_config(void)
 #define MAX_SHIELD_CMD_LEN 128
 
 	char shieldcmd_linux[MAX_SHIELD_CMD_LEN];
-	const char *shieldcmd;
+	const char *shieldcmd = ";";		/* default shield command is empty */
 	const struct shield_command *cmd;
 	int len;
 
 	int shield_id = bd_get_shield(0);
 	if (shield_id < 0) {
 		debug("No shield found in bd\n");
-		return;
+		goto end;
 	}
 
 	cmd = get_shield_command(shield_id);
 	if (cmd == NULL) {
 		printf ("Unknown shield id %d\n", shield_id);
-		return;
+		goto end;
 	}
 
 	printf("Shield:%s\n", cmd->name);
@@ -876,6 +938,7 @@ static void shield_config(void)
 		shieldcmd = shieldcmd_linux;
 	}
 
+end:
 	setenv("shieldcmd", shieldcmd);
 }
 
@@ -902,13 +965,22 @@ static bool get_button_state(void)
 	return pressed;
 }
 
-static void blink_led(void)
+static void blink_led(int pulses)
 {
 	const int pulse_width = 400*1000; /* 400ms */
 
-	/* Assumes green status LED is on */
-	udelay(pulse_width);
-	set_status_led(0, 0);	/* Off */
+	/* Assumes status led on, indicator off */
+	set_status_led(0, 0);
+
+	while (pulses) {
+		udelay(pulse_width);
+		set_status_led(1, 1);
+
+		udelay(pulse_width);
+		set_status_led(0, 0);
+
+		pulses--;
+	}
 
 	udelay(pulse_width);
 	set_status_led(0, 1);
@@ -928,12 +1000,11 @@ static void check_reset_button(void)
 
 		if (counter == 2000) {
 			/* Indicate factory reset threshold */
-			blink_led();
+			blink_led(1);
 		}
 		else if (counter == 12000) {
 			/* Indicate recovery boot threshold */
-			blink_led();
-			blink_led();
+			blink_led(2);
 		}
 	} while (counter < 12000);
 
@@ -1221,6 +1292,8 @@ static void ft_hw_info(void *blob)
 
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	/* TODO: Rework to behave like HW24, once this one is finalized */
+	/* ft_shields() function with switch case for shields */
 	int shield_type = -1;
 
 	ft_bootloader_version(blob);
diff --git a/board/nm/nrhw20/board.h b/board/nm/nrhw20/board.h
index 40d879576a..eb71c2d809 100644
--- a/board/nm/nrhw20/board.h
+++ b/board/nm/nrhw20/board.h
@@ -10,6 +10,7 @@
 
 #ifndef _BOARD_H_
 #define _BOARD_H_
+
 /*
  * We have three pin mux functions that must exist.  We must be able to enable
  * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
@@ -19,12 +20,12 @@
 void enable_uart0_pin_mux(void);
 void disable_uart0_pin_mux(void);
 void enable_uart1_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart5_pin_mux(void);
 
-void enable_i2c0_pin_mux(void);
-void enable_i2c2_pin_mux(void);
+/* TODO: Remove */
+/*void enable_uart5_pin_mux(void);*/
+
 void enable_board_pin_mux(void);
 
 #define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
 #endif
diff --git a/board/nm/nrhw20/mux.c b/board/nm/nrhw20/mux.c
index a2f69abb06..aff33738bd 100644
--- a/board/nm/nrhw20/mux.c
+++ b/board/nm/nrhw20/mux.c
@@ -1,7 +1,7 @@
 /*
  * mux.c
  *
- * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
@@ -23,50 +23,52 @@
 
 static struct module_pin_mux gpio_pin_mux[] = {
 	/*
-	* GPIO0_2: RST_GNSS~
-	* GPIO0_3: GEOFENCE_GNSS
-	* GPIO0_4: RTK_STAT_GNSS
-	* GPIO0_5: EXTINT_GNSS
-	* GPIO0_6: TIMEPULSE_GNSS
-	* GPIO0_7: PWM / SHIELD LATCH
-	* GPIO0_16: RST_PHY~
-	* GPIO0_17: PMIC FAULT
-	* GPIO0_27: RST_SHIELD~
+	* CPU GPIOs
 	*
-	* GPIO1_14: DIG_OUT
-	* GPIO1_15: DIG_IN
-	* GPIO1_20: BT_EN
-	* GPIO1_21: GSM_PWR_EN
-	* GPIO1_25: RST_GSM
-	* GPIO1_26: WLAN_EN
-	* GPIO1_27: WLAN_IRQ
+	* (A17) GPIO0_2: RST_GNSS~
+	* (B17) GPIO0_3: GEOFENCE_GNSS
+	* (B16) GPIO0_4: RTK_STAT_GNSS
+	* (A16) GPIO0_5: EXTINT_GNSS
+	* (C15) GPIO0_6: TIMEPULSE
+	* (C18) GPIO0_7: PWM / SHIELD LATCH
+	* (J18) GPIO0_16: RST_PHY~
+	* (K15) GPIO0_17: PMIC FAULT
+	* (U12) GPIO0_27: RST_SHIELD~
 	*
-	* GPIO3_4: PCIe_IO.WAKE
-	* GPIO3_9: PCIe_IO.W_DIS
-	* GPIO3_10: PCIe_IO.RST
-	* GPIO3_17: SIM_SEL
-	* GPIO3_21: RST_HUB~ (USB)
+	* (V13) GPIO1_14: DIG_OUT
+	* (U13) GPIO1_15: DIG_IN
+	* (R14) GPIO1_20: BT_EN
+	* (V15) GPIO1_21: GSM_PWR_EN
+	* (U16) GPIO1_25: RST_GSM
+	* (T16) GPIO1_26: WLAN_EN
+	* (V17) GPIO1_27: WLAN_IRQ
+	*
+	* (J17) GPIO3_4: PCIe_IO.WAKE
+	* (K18) GPIO3_9: PCIe_IO.W_DIS
+	* (L18) GPIO3_10: PCIe_IO.RST
+	* (C12) GPIO3_17: SIM_SEL
+	* (A14) GPIO3_21: RST_HUB~ (USB)
 	*/
 
 	/* Bank 0 */
-	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},			/* (A17) gpio0[2] */  /* RST_GNSS */
-	{OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (B17) gpio0[3] */  /* GEOFENCE_GNSS */
-	{OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (B16) gpio0[4] */  /* RTK_STAT_GNSS */
-	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (A16) gpio0[5] */  /* EXTINT_GNSS */
-	{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (C15) gpio0[6] */  /* TIMEPULSE_GNSS */
-	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) gpio0[7] */  /* IO_SHIELD */
-	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},			/* (J18) gpio0[16] */  /* RST_PHY~ */
-	{OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (K15) gpio0[17] */  /* PMIC_FAULT */
-	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},			/* (U12) gpio0[27] */  /* RST_SHIELD~ */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},				/* (A17) gpio0[2] */  /* RST_GNSS */
+	{OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},		/* (B17) gpio0[3] */  /* GEOFENCE_GNSS */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},		/* (B16) gpio0[4] */  /* RTK_STAT_GNSS */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},			/* (A16) gpio0[5] */  /* EXTINT_GNSS */
+	{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (C15) gpio0[6] */  /* TIMEPULSE */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (C18) gpio0[7] */  /* IO_SHIELD */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (K15) gpio0[17] */  /* PMIC_FAULT */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},				/* (U12) gpio0[27] */  /* RST_SHIELD~ */
 
 	/* Bank 1 */
-	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},			/* (V13) gpio1[14] */  /* DIG_OUT */
-	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (U13) gpio1[15] */  /* DIG_IN */
-	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},			/* (R14) gpio1[20] */  /* BT_EN */
-	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},			/* (V15) gpio1[21] */  /* GSM_PWR_EN */
-	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},			/* (U16) gpio1[25] */  /* RST_GSM */
-	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},			/* (T16) gpio1[26] */  /* WLAN_EN */
-	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (V17) gpio1[27] */  /* WLAN_IRQ */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},				/* (V13) gpio1[14] */  /* DIG_OUT */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U13) gpio1[15] */  /* DIG_IN */
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},				/* (R14) gpio1[20] */  /* BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},				/* (V15) gpio1[21] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},				/* (U16) gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},				/* (T16) gpio1[26] */  /* WLAN_EN */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V17) gpio1[27] */  /* WLAN_IRQ */
 
 	/* TODO: What about all the unused GPMC pins ? */
 
@@ -85,20 +87,20 @@ static struct module_pin_mux gpio_pin_mux[] = {
 #endif
 
 	/* Bank 3 */
-	{OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (H16) gpio3[0] */  /* BUTTON */
-	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (J17) gpio3[4] */  /* PCIe_IO.WAKE */
-	{OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)},			/* (K18) gpio3[9] */  /* PCIe_IO.W_DIS */
-	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},			/* (L18) gpio3[10] */  /* PCIe_IO.RST */
-	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* (C12) gpio3[17] */  /* SIM_SEL */
-	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN)},			/* (A14) gpio3[21] */  /* RST_HUB~ */
-	{-1},
+	{OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (H16) gpio3[0] */  /* BUTTON */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (J17) gpio3[4] */  /* PCIe_IO.WAKE */
+	{OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)},				/* (K18) gpio3[9] */  /* PCIe_IO.W_DIS */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},				/* (L18) gpio3[10] */  /* PCIe_IO.RST */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (C12) gpio3[17] */  /* SIM_SEL */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN)},				/* (A14) gpio3[21] */  /* RST_HUB~ */
+	{-1}
 };
 
 /* I2C0 PMIC */
 static struct module_pin_mux i2c0_pin_mux[] = {
 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
-	{-1},
+	{-1}
 };
 
 /* I2C2 System */
@@ -126,40 +128,40 @@ static struct module_pin_mux rmii1_pin_mux[] = {
 
 	/* 25MHz Clock Output */
 	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for Switch) */
-	{-1},
+	{-1}
 };
 
 /* MMC0: WiFi */
 static struct module_pin_mux mmc0_sdio_pin_mux[] = {
-	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CMD */
-	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT3 */
-	{-1},
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
 };
 
 /* MMC1: eMMC */
 static struct module_pin_mux mmc1_emmc_pin_mux[] = {
-	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
-	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
-	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT0 */
-	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT1 */
-	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT2 */
-	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT3 */
-	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT4 */
-	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT5 */
-	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT6 */
-	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT7 */
-	{-1},
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
 };
 
 /* USB_DRVBUS not used -> configure as GPIO */
 static struct module_pin_mux usb_pin_mux[] = {
 	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
 	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
-	{-1},
+	{-1}
 };
 
 /* UART0: RS232/RS485 shield mode */
@@ -191,7 +193,7 @@ static struct module_pin_mux uart1_pin_mux[] = {
 static struct module_pin_mux uart3_pin_mux[] = {
 	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (L17) UART3_RXD */
 	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (L16) UART3_TXD */
-	{-1},
+	{-1}
 };
 
 /* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
@@ -200,7 +202,7 @@ static struct module_pin_mux uart5_pin_mux[] = {
 	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
 	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
 	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
-	{-1},
+	{-1}
 };
 
 static struct module_pin_mux unused_pin_mux[] = {
@@ -212,7 +214,7 @@ static struct module_pin_mux unused_pin_mux[] = {
 
 	/* TODO: GPMCA1..3, A6..8 */
 
-	{-1},
+	{-1}
 };
 
 
@@ -249,12 +251,10 @@ void enable_uart1_pin_mux(void)
 	configure_module_pin_mux(uart1_pin_mux);
 }
 
-void enable_uart3_pin_mux(void)
-{
-	configure_module_pin_mux(uart3_pin_mux);
-}
-
+/* TODO: Remove */
+/*
 void enable_uart5_pin_mux(void)
 {
 	configure_module_pin_mux(uart5_pin_mux);
 }
+*/
diff --git a/include/configs/am335x_nrhw20.h b/include/configs/am335x_nrhw20.h
index 009a78e9c5..d05ec46e95 100644
--- a/include/configs/am335x_nrhw20.h
+++ b/include/configs/am335x_nrhw20.h
@@ -19,6 +19,11 @@
 
 #include <configs/ti_am335x_common.h>
 
+/* TODO: Inject via build system */
+#define CONFIG_NRSW
+
+
+
 /* Disable U-Boot load from filesystems, to save around 10 kB SPL image size */
 #ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 # undef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
@@ -43,9 +48,9 @@
 
 /* TODO: It could be preconsole buffer is not properly working in SPL
  * Observed lock ups when printing too much text.
-#define CONFIG_PRE_CONSOLE_BUFFER 1
-#define CONFIG_PRE_CON_BUF_ADDR   0x80000000
-#define CONFIG_PRE_CON_BUF_SZ     64*1024
+#define CONFIG_PRE_CONSOLE_BUFFER
+#define CONFIG_PRE_CON_BUF_ADDR   	0x80000000
+#define CONFIG_PRE_CON_BUF_SZ     	64*1024
 */
 
 /* Clock Defines */
@@ -70,6 +75,118 @@ int eth_phy_timeout(void);
 #define CONFIG_NET_RETRY_COUNT		5
 #define CONFIG_BOOTP_MAY_FAIL
 
+#ifndef CONFIG_SPL_BUILD
+
+
+/*
+ * Memory map for booting Linux
+ *
+ * 0x80000000   63MB	KERNEL_ADDR (kernel_addr), kernel execution address
+ * 0x83F00000    1MB	FDT_ADDR_R (fdt_addr_r), device tree loading address if not included in kernel
+ *             126MB	INIT_RD_HIGH (initrd_high), ramdisc top address for relocation
+ * 0x8BE00000	 2MB	PXE_ADDR (pxefile_addr_r), pxe configuration file (pxe get command)
+ * 0x8C000000    1MB	LOAD_ADDR (load_addr), loading address for generic files
+ * 0x8C100000   31MB	KERNEL_ADDR_R (kernel_addr_r), kernel loading address (will be relocated to kernel_addr)
+ * 0x8E000000    4B     NRSW reset reason
+ * 0x90000000  256MB	<>, Free space 512MB systems
+ * 0xA0000000  512MB	<>, Free space, 1GB systems only
+ * 0xC0000000		End of RAM
+ * 
+ * ((0x84000000  126MB	RD_ADDR (ramdisk_addr_r), ramdisc loading address))
+ */
+
+#define KERNEL_ADDR	"0x80000000"
+/*#define FDT_ADDR	"0x82000000"	*/ /* NRSW, trying to use FDT_ADDR_R = 0x83F00000 instead */
+#define FDT_ADDR_R	"0x83F00000"
+#define PXE_ADDR	"0x8BE00000"
+#define LOAD_ADDR	"0x8C000000"
+#define KERNEL_ADDR_R	"0x8C100000"
+
+/* TODO: Check this with 1 GByte system */
+/* Most likely ramdisk and FDT will be loaded to too high adresses and boot will fail */
+#if 0
+/*
+ * Avoid copying ramdisc and dtb above 512MB, as it breaks Linux boot.
+ * -1 means "do not copy" to high address, use in place.
+ */
+#define INITRD_HIGH_ADDR "0x8BE0000"
+#define RD_ADDR		"0x84000000"
+#define FDT_HIGH_ADDR	"0x87000000"
+#define FDT_HIGH_ADDR	"0xffffffff"
+
+	"fdt_high=" FDT_HIGH_ADDR "\0" /* Breaks NRSW, required by Yocto ! */ \
+	"fdt_addr=" FDT_ADDR "\0" /* NRSW only, breaks yocto, can we move that to fdt_addr_r ? */ \
+	"initrd_high=" INITRD_HIGH_ADDR "\0" /* (0x84000000) ->  INIT_RD_ADDR (0x88000000) */ \
+	"ramdisk_addr_r=" RD_ADDR "\0" \
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	/* Memory Adresses */ \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"kernel_addr=" KERNEL_ADDR "\0" /* NRSW only */ \
+	"kernel_addr_r=" KERNEL_ADDR_R  "\0" \
+	"load_addr=" LOAD_ADDR "\0" \
+	"pxefile_addr_r=" PXE_ADDR "\0" \
+	\
+	/* Misc */ \
+	"defaultconsole=ttyS1\0" \
+	"fdt_skip_update=yes\0" \
+	"bootdelay=0\0" \
+	\
+	/* Networking */ \
+	"ethprime=cpsw\0" \
+	"ethopts=ti_cpsw.rx_packet_max=1526\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"tftptimeout=2000\0" \
+	"tftptimeoutcountmax=5\0" \
+	"bootpretryperiod=10000\0" /* 2000 */ \
+	"autoload=false\0" \
+	\
+	/* OSTree boot */ \
+	"bootcmd_otenv=ext4load mmc 1:1 $load_addr /boot/loader/uEnv.txt; " \
+			"env import -t $load_addr $filesize; " \
+			"setenv bootargs $bootargs root=/dev/ram0 console=$defaultconsole,115200 " \
+			"$ethopts rw ostree_root=/dev/mmcblk1p1\0" \
+	"bootcmd_rd_in_mmc=ext4load mmc 1:1 $kernel_addr_r /boot$kernel_image; " \
+			"bootm $kernel_addr_r\0" \
+	"bootcmd=run shieldcmd; run bootcmd_otenv; run bootcmd_rd_in_mmc\0" \
+	\
+	/* NRSW boot */ \
+	"root_part=1\0" /* from NRSW, required here? set from board.c */ \
+	"kernel_image=kernel.bin\0" \
+	"fdt_image=am335x-nmhw24-prod1.dtb\0" /* diff, openwrt-nrhw24-nb801.dtb, not relevant as it will be overwritten */ \
+	"add_sd_bootargs=setenv bootargs $bootargs root=/dev/${mmc_dev}p$root_part rootfstype=ext4 " \
+			"console=$defaultconsole,115200 rootwait loglevel=4 ti_cpsw.rx_packet_max=1526\0" \
+	"add_version_bootargs=setenv bootargs $bootargs\0" \
+	"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
+	"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
+	"sdboot=env set fdt_addr " FDT_ADDR_R "; "\
+			"if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
+			"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
+			"else run sdbringup; fi; " \
+			/* For v4.19 kernel $mmc_dev should be "mmcblk1" (read from DT), for v3.18 kernel: "mmcblk0" */ \
+			"fdt addr $fdt_addr;if fdt get value mmc_dev /nm_env nm,mmc-dev;then;else setenv mmc_dev mmcblk0;fi;" \
+			"run add_sd_bootargs; run add_version_bootargs; run shieldcmd; " \
+			"bootz $kernel_addr - $fdt_addr; fi\0" \
+	/* "bootcmd=run sdboot\0" */ \
+	\
+	/* Recovery boot */ \
+	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" \
+	/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs internally */ \
+	"pxe_recovery=mdio up $ethprime && dhcp && pxe get && pxe boot\0" \
+	"tftp_recovery=tftpboot $kernel_addr_r recovery-image; tftpboot $fdt_addr_r recovery-dtb; " /* kernel_addr_r ? */ \
+			"setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 " \
+			"debug $ethopts; " \
+			"bootz $kernel_addr_r - $fdt_addr_r\0" /* kernel_addr_r */
+
+#endif
+
+#if 0
+
 #ifndef CONFIG_SPL_BUILD
 #define KERNEL_ADDR			"0x80000000"
 #define LOAD_ADDR			"0x83000000"
@@ -131,9 +248,16 @@ int eth_phy_timeout(void);
 			/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
 #endif
 
+#endif
+
+
+/* TODO: Check if ok for NRSW? */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
 /* UART Configuration */
 #define CONFIG_SYS_NS16550_COM1			0x44e09000	/* UART0: XModem Boot, Shield */
 #define CONFIG_SYS_NS16550_COM2			0x48022000	/* UART1: eMMC Boot, User UART */
+/* TODO: Can the following be removed, as they shouldn't be required for bootloader */
 #define CONFIG_SYS_NS16550_COM3			0x48024000	/* Unused */
 #define CONFIG_SYS_NS16550_COM4			0x481A6000	/* GNSS */
 #define CONFIG_SYS_NS16550_COM5			0x481A8000	/* Unused */
@@ -172,7 +296,6 @@ int eth_phy_timeout(void);
 #undef CONFIG_SPI_BOOT
 #undef CONFIG_SPL_OS_BOOT
 
-#define CONFIG_SPL_POWER_SUPPORT	/* TODO: Check */
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
@@ -193,16 +316,6 @@ int eth_phy_timeout(void);
 #define CONFIG_AM335X_USB0
 #define CONFIG_AM335X_USB0_MODE		MUSB_HOST
 
-/* TODO: remove */
-#if 0
-/* Fastboot */
-#define CONFIG_USB_FUNCTION_FASTBOOT
-#define CONFIG_CMD_FASTBOOT
-#define CONFIG_ANDROID_BOOT_IMAGE
-#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
-#define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
-#endif
-
 /* To support eMMC booting */
 #define CONFIG_STORAGE_EMMC
 #define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
@@ -247,13 +360,21 @@ int eth_phy_timeout(void);
 #define CONFIG_MV88E60XX_CPU_PORT	5
 
 
-#define CONFIG_SYS_MEMTEST_START    0x80000000
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START    0x84000000
 #define CONFIG_SYS_MEMTEST_END      0x87900000
 
-/* Enable for NRSW support
-#define CONFIG_NM_LOGIN
+
+#ifdef CONFIG_NRSW
+/* support for NM packed bootloader */
+#define CONFIG_NM_BOOTLOADER_FORMAT
+
+/* password protected login */
 #define CONFIG_CRYPT
-*/
+#define CONFIG_NM_LOGIN
+#define CONFIG_NM_LOGIN_PART	"1:3"	/* TODO: Define location of file for OSTree/Yocto */
+#define CONFIG_NM_LOGIN_PASSWD	"/root/boot/bootpass"
+#endif
 
 #define CONFIG_CMD_PXE
 
@@ -262,6 +383,13 @@ int eth_phy_timeout(void);
 #define CONFIG_JTAG_MARKER_SPL		0x402FFF00
 #define CONFIG_JTAG_MARKER_UBOOT	0x807FFF00
 
+/* NRSW PMIC Reset Reason */
+#ifdef CONFIG_NRSW
+#define RESET_REASON_SHM_LOCATION	0x8e000000
+#define EXTERNAL_WATCHDOG_PATTERN	0x781f9ce2
+#endif
+
+
 /* SPL command is not needed */
 #undef CONFIG_CMD_SPL