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Merge git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Tom Rini 2016-12-04 13:55:15 -05:00
parent d50dbc826c 54db3c20bd
commit 194eded14c
107 changed files with 276 additions and 227 deletions
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6
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -28,6 +28,12 @@ config NUM_DDR_CONTROLLERS
int "Maximum DDR controllers"
default 1
config SECURE_BOOT
bool "Secure Boot"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"

5
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -71,6 +71,11 @@ config NUM_DDR_CONTROLLERS
default 3 if ARCH_LS2080A
default 1
config SECURE_BOOT
bool
help
Enable Freescale Secure Boot feature
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -138,7 +138,6 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_ESDHC_BE

4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -120,7 +120,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_CCSRBAR 0x01000000
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@ -128,7 +128,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \

156
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -309,125 +309,179 @@ config TARGET_UCP1020
bool "Support uCP1020"
select ARCH_P1020
config TARGET_CYRUS
bool "Support Varisys Cyrus"
config TARGET_CYRUS_P5020
bool "Support Varisys Cyrus P5020"
select ARCH_P5020
select PHYS_64BIT
config TARGET_CYRUS_P5040
bool "Support Varisys Cyrus P5040"
select ARCH_P5040
select PHYS_64BIT
endchoice
config ARCH_B4420
bool
select FSL_LAW
config ARCH_B4860
bool
select FSL_LAW
config ARCH_BSC9131
bool
select FSL_LAW
config ARCH_BSC9132
bool
select FSL_LAW
config ARCH_C29X
bool
select FSL_LAW
config ARCH_MPC8536
bool
select FSL_LAW
config ARCH_MPC8540
bool
select FSL_LAW
config ARCH_MPC8541
bool
select FSL_LAW
config ARCH_MPC8544
bool
select FSL_LAW
config ARCH_MPC8548
bool
select FSL_LAW
config ARCH_MPC8555
bool
select FSL_LAW
config ARCH_MPC8560
bool
select FSL_LAW
config ARCH_MPC8568
bool
select FSL_LAW
config ARCH_MPC8569
bool
select FSL_LAW
config ARCH_MPC8572
bool
select FSL_LAW
config ARCH_P1010
bool
select FSL_LAW
config ARCH_P1011
bool
select FSL_LAW
config ARCH_P1020
bool
select FSL_LAW
config ARCH_P1021
bool
select FSL_LAW
config ARCH_P1022
bool
select FSL_LAW
config ARCH_P1023
bool
select FSL_LAW
config ARCH_P1024
bool
select FSL_LAW
config ARCH_P1025
bool
select FSL_LAW
config ARCH_P2020
bool
select FSL_LAW
config ARCH_P2041
bool
select FSL_LAW
config ARCH_P3041
bool
select FSL_LAW
config ARCH_P4080
bool
select FSL_LAW
config ARCH_P5020
bool
select FSL_LAW
config ARCH_P5040
bool
select FSL_LAW
config ARCH_QEMU_E500
bool
config ARCH_T1023
bool
select FSL_LAW
config ARCH_T1024
bool
select FSL_LAW
config ARCH_T1040
bool
select FSL_LAW
config ARCH_T1042
bool
select FSL_LAW
config ARCH_T2080
bool
select FSL_LAW
config ARCH_T2081
bool
select FSL_LAW
config ARCH_T4160
bool
select FSL_LAW
config ARCH_T4240
bool
select FSL_LAW
config FSL_LAW
bool
help
Use Freescale common code for Local Access Window
config SECURE_BOOT
bool "Secure Boot"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
@ -465,6 +519,104 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_MPC8540 || \
ARCH_MPC8541 || \
ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8555 || \
ARCH_MPC8560 || \
ARCH_MPC8568 || \
ARCH_MPC8569 || \
ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
default 0xff600000 if ARCH_P1023
default 0xfe000000 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T1013 || \
ARCH_T1014 || \
ARCH_T1020 || \
ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
help
Default value of CCSRBAR comes from power-on-reset. It
is fixed on each SoC. Some SoCs can have different value
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
config SYS_FSL_NUM_LAWS
int "Number of local access windows"
depends on FSL_LAW
default 32 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5020 || \
ARCH_P5040 || \
ARCH_T2080 || \
ARCH_T2081 || \
ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1013 || \
ARCH_T1014 || \
ARCH_T1020 || \
ARCH_T1022 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
default 12 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1022 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020
default 10 if ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8568 || \
ARCH_MPC8569
default 8 if ARCH_MPC8540 || \
ARCH_MPC8541 || \
ARCH_MPC8555 || \
ARCH_MPC8560
help
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"

22
arch/powerpc/cpu/mpc86xx/Kconfig
View File

@ -28,9 +28,31 @@ endchoice
config ARCH_MPC8610
bool
select FSL_LAW
config ARCH_MPC8641
bool
select FSL_LAW
config FSL_LAW
bool
help
Use Freescale common code for Local Access Window
config SYS_CCSRBAR_DEFAULT
hex "Default CCSRBAR address"
default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
help
Default value of CCSRBAR comes from power-on-reset. It
is fixed on each SoC. Some SoCs can have different value
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
config SYS_FSL_NUM_LAWS
int "Number of local access windows"
default 10 if ARCH_MPC8610 || ARCH_MPC8641
help
Number of local access windows. This is fixed per SoC.
If not sure, do not change.
source "board/freescale/mpc8610hpcd/Kconfig"
source "board/freescale/mpc8641hpcn/Kconfig"

73
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -9,10 +9,6 @@
/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
#endif
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
@ -36,38 +32,28 @@
#endif
#if defined(CONFIG_ARCH_MPC8536)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8540)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8541)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8544)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
@ -81,24 +67,18 @@
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#elif defined(CONFIG_ARCH_MPC8555)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8560)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_ARCH_MPC8568)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -106,12 +86,10 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -121,10 +99,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
#define CONFIG_SYS_FSL_ERRATUM_A004508
@ -132,7 +108,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@ -140,7 +115,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@ -159,25 +133,21 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
@ -187,12 +157,10 @@
#endif
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@ -203,12 +171,10 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
@ -217,7 +183,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
@ -227,7 +192,6 @@
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
@ -235,13 +199,11 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
@ -249,13 +211,11 @@
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@ -265,10 +225,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@ -285,7 +243,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@ -295,7 +252,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@ -322,7 +278,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@ -332,7 +287,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@ -361,7 +315,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@ -374,7 +327,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@ -412,7 +364,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@ -423,7 +374,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@ -447,7 +397,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@ -460,7 +409,6 @@
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@ -477,7 +425,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
@ -486,7 +433,6 @@
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
@ -496,7 +442,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
@ -507,7 +452,6 @@
#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
@ -545,7 +489,6 @@
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
@ -575,7 +518,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007798
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
@ -588,7 +530,6 @@
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_MAPLE
@ -618,7 +559,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
@ -657,7 +597,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@ -681,7 +620,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
@ -704,7 +642,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@ -725,7 +662,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
@ -743,7 +679,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
@ -778,7 +713,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -791,7 +725,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_SEC_COMPAT 6
@ -799,22 +732,16 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#elif defined(CONFIG_ARCH_QEMU_E500)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
#else
#error Processor type not defined for this platform
#endif
#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
#endif
#ifdef CONFIG_E6500
#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
#else

12
arch/powerpc/include/asm/config_mpc86xx.h
View File

@ -9,16 +9,4 @@
#define CONFIG_SYS_FSL_DDR_86XX
/* SoC specific defines for Freescale MPC86xx processors */
#if defined(CONFIG_ARCH_MPC8610)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#elif defined(CONFIG_ARCH_MPC8641)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#else
#error Processor type not defined for this platform
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */

2
board/varisys/cyrus/Kconfig
View File

@ -1,4 +1,4 @@
if TARGET_CYRUS
if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
config SYS_BOARD
default "cyrus"

2
configs/B4860QDS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/C29XPCIE_NOR_SECBOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

4
configs/Cyrus_P5020_defconfig
View File

@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CYRUS=y
CONFIG_TARGET_CYRUS_P5020=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5020"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y

4
configs/Cyrus_P5040_defconfig
View File

@ -1,11 +1,11 @@
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_CYRUS=y
CONFIG_TARGET_CYRUS_P5040=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5040"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PA_NAND_SECBOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/P1010RDB-PA_NOR_SECBOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PB_NAND_SECBOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/P1010RDB-PB_NOR_SECBOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

2
configs/P2041RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

3
configs/P3041DS_NAND_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/P3041DS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/P4080DS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

3
configs/P5020DS_NAND_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/P5020DS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

3
configs/P5040DS_NAND_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/P5040DS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

3
configs/T1023RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="T1023RDB,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="T1023RDB"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y

3
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

2
configs/T1024QDS_SECURE_BOOT_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

3
configs/T1024RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="T1024RDB,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="T1024RDB"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

3
configs/T1040D4RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

2
configs/T1040QDS_SECURE_BOOT_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

2
configs/T1040RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

3
configs/T1042D4RDB_SECURE_BOOT_defconfig
View File

@ -7,7 +7,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

3
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
View File

@ -13,7 +13,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

2
configs/T1042RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y

2
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/T2080RDB_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y

2
configs/T4160QDS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/T4240QDS_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y

2
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -7,7 +7,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

2
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -6,7 +6,7 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

3
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -13,7 +13,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set

2
configs/ls1043ardb_SECURE_BOOT_defconfig
View File

@ -5,7 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y

3
configs/ls2080aqds_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y

3
configs/ls2080ardb_SECURE_BOOT_defconfig
View File

@ -6,7 +6,8 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
CONFIG_SECURE_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y

4
doc/README.ramboot-ppc85xx
View File

@ -90,8 +90,8 @@ In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
This will finally use the CONFIG_SYS_RAMBOOT.
3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
In the section of the particular SOC, for example P1020,
3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
In the section of the particular SOC, for example P1020, pseudo code
#if defined(CONFIG_GO)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xffe00000

3
include/configs/B4860QDS.h
View File

@ -19,7 +19,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@ -80,8 +79,6 @@
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x77

1
include/configs/BSC9131RDB.h
View File

@ -51,7 +51,6 @@
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

1
include/configs/BSC9132QDS.h
View File

@ -103,7 +103,6 @@
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_TSEC_ENET /* ethernet */

1
include/configs/C29XPCIE.h
View File

@ -102,7 +102,6 @@
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8536DS.h
View File

@ -51,7 +51,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

1
include/configs/MPC8540ADS.h
View File

@ -36,7 +36,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* sysclk for MPC85xx

2
include/configs/MPC8541CDS.h
View File

@ -25,8 +25,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
#ifndef __ASSEMBLY__

2
include/configs/MPC8544DS.h
View File

@ -28,8 +28,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */

1
include/configs/MPC8548CDS.h
View File

@ -35,7 +35,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA

1
include/configs/MPC8555CDS.h
View File

@ -24,7 +24,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA

1
include/configs/MPC8560ADS.h
View File

@ -34,7 +34,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
/*

1
include/configs/MPC8568MDS.h
View File

@ -28,7 +28,6 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);

1
include/configs/MPC8569MDS.h
View File

@ -26,7 +26,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);

2
include/configs/MPC8572DS.h
View File

@ -39,8 +39,6 @@
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

2
include/configs/MPC8610HPCD.h
View File

@ -42,7 +42,6 @@
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
@ -72,7 +71,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */

2
include/configs/MPC8641HPCN.h
View File

@ -44,7 +44,6 @@
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@ -87,7 +86,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */

3
include/configs/P1010RDB.h
View File

@ -19,7 +19,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@ -45,7 +44,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
@ -201,7 +199,6 @@
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

4
include/configs/P1022DS.h
View File

@ -15,7 +15,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@ -36,7 +35,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@ -115,8 +113,6 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */

1
include/configs/P1023RDB.h
View File

@ -35,7 +35,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);

2
include/configs/P2041RDB.h
View File

@ -58,8 +58,6 @@
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH

2
include/configs/T102xQDS.h
View File

@ -28,7 +28,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP
@ -42,7 +41,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000

2
include/configs/T102xRDB.h
View File

@ -28,7 +28,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
@ -45,7 +44,6 @@
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000

2
include/configs/T1040QDS.h
View File

@ -69,8 +69,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH

3
include/configs/T104xRDB.h
View File

@ -24,7 +24,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@ -180,8 +179,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_NO_FLASH

2
include/configs/T208xQDS.h
View File

@ -41,7 +41,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
@ -49,7 +48,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000

2
include/configs/T208xRDB.h
View File

@ -34,7 +34,6 @@
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_RAMBOOT_PBL
@ -42,7 +41,6 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000

1
include/configs/T4240QDS.h
View File

@ -24,7 +24,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000

3
include/configs/T4240RDB.h
View File

@ -23,7 +23,6 @@
#else
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000
@ -85,8 +84,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
/*

2
include/configs/UCP1020.h
View File

@ -124,8 +124,6 @@
#define CONFIG_MP
#define CONFIG_FSL_LAW
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CMD_SATA

1
include/configs/controlcenterd.h
View File

@ -42,7 +42,6 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP

2
include/configs/corenet_ds.h
View File

@ -69,8 +69,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH

2
include/configs/cyrus.h
View File

@ -59,8 +59,6 @@
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_NO_FLASH

2
include/configs/km/kmp204x-common.h
View File

@ -46,8 +46,6 @@
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */
/* Environment in SPI Flash */
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH

3
include/configs/p1_p2_rdb_pc.h
View File

@ -174,7 +174,6 @@
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@ -195,7 +194,6 @@
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x20000
@ -274,7 +272,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

1
include/configs/p1_twr.h
View File

@ -52,7 +52,6 @@
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

2
include/configs/sbc8548.h
View File

@ -69,8 +69,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
*/

2
include/configs/sbc8641d.h
View File

@ -46,7 +46,6 @@
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@ -87,7 +86,6 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */

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