MLK-18243-6 arm: imx8m: add clock driver for i.MX8MM
The PLL used on i.MX8MM is different from i.MX8MQ, so add new clock_imx8mm.c dedicated for i.MX8MM, Currently use two new files for i.MX8MM, in future the code could be restructed to share to avoid code duplication. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 4415e28950b1baf62a9b9e3c819d93e7deba0cad)
This commit is contained in:
Peng Fan
Ye Li
parent
6ccb18feb6
commit
19e09b42ca
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@ -5,5 +5,7 @@
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#
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obj-y += lowlevel_init.o
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obj-y += clock.o clock_slice.o soc.o
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obj-y += soc.o clock_slice.o
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obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
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obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
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obj-$(CONFIG_VIDEO_IMXDCSS) += video_common.o
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@ -0,0 +1,825 @@
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/* Copyright 2018 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SECURE_BOOT
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void hab_caam_clock_enable(unsigned char enable)
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{
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/* The CAAM clock is always on for iMX8M */
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}
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#endif
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable)
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{
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clock_enable(CCGR_OCOTP, !!enable);
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}
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#endif
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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/* 0 - 3 is valid i2c num */
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if (i2c_num > 3)
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return -EINVAL;
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clock_enable(CCGR_I2C1 + i2c_num, !!enable);
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return 0;
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}
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u32 decode_intpll(enum clk_root_src intpll)
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{
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u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
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u32 main_div, pre_div, post_div, div;
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u64 freq;
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switch (intpll) {
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case ARM_PLL_CLK:
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pll_gnrl_ctl = readl((void __iomem *)ARM_PLL_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)ARM_PLL_DIV_CTL);
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break;
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case GPU_PLL_CLK:
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pll_gnrl_ctl = readl((void __iomem *)GPU_PLL_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)GPU_PLL_DIV_CTL);
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break;
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case VPU_PLL_CLK:
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pll_gnrl_ctl = readl((void __iomem *)VPU_PLL_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)VPU_PLL_DIV_CTL);
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break;
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case SYSTEM_PLL1_800M_CLK:
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case SYSTEM_PLL1_400M_CLK:
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case SYSTEM_PLL1_266M_CLK:
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case SYSTEM_PLL1_200M_CLK:
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case SYSTEM_PLL1_160M_CLK:
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case SYSTEM_PLL1_133M_CLK:
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case SYSTEM_PLL1_100M_CLK:
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case SYSTEM_PLL1_80M_CLK:
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case SYSTEM_PLL1_40M_CLK:
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pll_gnrl_ctl = readl((void __iomem *)SYS_PLL1_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)SYS_PLL1_DIV_CTL);
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break;
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case SYSTEM_PLL2_1000M_CLK:
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case SYSTEM_PLL2_500M_CLK:
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case SYSTEM_PLL2_333M_CLK:
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case SYSTEM_PLL2_250M_CLK:
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case SYSTEM_PLL2_200M_CLK:
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case SYSTEM_PLL2_166M_CLK:
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case SYSTEM_PLL2_125M_CLK:
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case SYSTEM_PLL2_100M_CLK:
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case SYSTEM_PLL2_50M_CLK:
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pll_gnrl_ctl = readl((void __iomem *)SYS_PLL2_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)SYS_PLL2_DIV_CTL);
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break;
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case SYSTEM_PLL3_CLK:
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pll_gnrl_ctl = readl((void __iomem *)SYS_PLL3_GNRL_CTL);
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pll_div_ctl = readl((void __iomem *)SYS_PLL3_DIV_CTL);
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break;
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default:
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return -EINVAL;
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}
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/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
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if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
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return 0;
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if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
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return 0;
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/*
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* When BYPASS is equal to 1, PLL enters the bypass mode
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* regardless of the values of RESETB
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*/
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if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
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return 24000000u;
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if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
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puts("pll not locked\n");
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return 0;
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}
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switch (intpll) {
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case ARM_PLL_CLK:
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case GPU_PLL_CLK:
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case VPU_PLL_CLK:
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case SYSTEM_PLL3_CLK:
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case SYSTEM_PLL1_800M_CLK:
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case SYSTEM_PLL2_1000M_CLK:
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pll_clke_mask = INTPLL_CLKE_MASK;
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div = 1;
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break;
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case SYSTEM_PLL1_400M_CLK:
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case SYSTEM_PLL2_500M_CLK:
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pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
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div = 2;
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break;
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case SYSTEM_PLL1_266M_CLK:
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case SYSTEM_PLL2_333M_CLK:
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pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
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div = 3;
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break;
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case SYSTEM_PLL1_200M_CLK:
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case SYSTEM_PLL2_250M_CLK:
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pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
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div = 4;
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break;
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case SYSTEM_PLL1_160M_CLK:
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case SYSTEM_PLL2_200M_CLK:
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pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
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div = 5;
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break;
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case SYSTEM_PLL1_133M_CLK:
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case SYSTEM_PLL2_166M_CLK:
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pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
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div = 6;
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break;
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case SYSTEM_PLL1_100M_CLK:
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case SYSTEM_PLL2_125M_CLK:
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pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
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div = 8;
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break;
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case SYSTEM_PLL1_80M_CLK:
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case SYSTEM_PLL2_100M_CLK:
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pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
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div = 10;
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break;
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case SYSTEM_PLL1_40M_CLK:
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case SYSTEM_PLL2_50M_CLK:
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pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
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div = 20;
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break;
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default:
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return -EINVAL;
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}
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if ((pll_gnrl_ctl & pll_clke_mask) == 0)
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return 0;
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main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
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INTPLL_MAIN_DIV_SHIFT;
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pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
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INTPLL_PRE_DIV_SHIFT;
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post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
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INTPLL_POST_DIV_SHIFT;
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/* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
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freq = 24000000ULL * main_div;
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return lldiv(freq, pre_div * (1 << post_div) * div);
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}
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u32 decode_fracpll(enum clk_root_src frac_pll)
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{
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u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
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u32 main_div, pre_div, post_div, k;
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switch (frac_pll) {
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case DRAM_PLL1_CLK:
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pll_gnrl_ctl = readl((void __iomem *)DRAM_PLL_GNRL_CTL);
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pll_fdiv_ctl0 = readl((void __iomem *)DRAM_PLL_FDIV_CTL0);
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pll_fdiv_ctl1 = readl((void __iomem *)DRAM_PLL_FDIV_CTL1);
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break;
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case AUDIO_PLL1_CLK:
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pll_gnrl_ctl = readl((void __iomem *)AUDIO_PLL1_GNRL_CTL);
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pll_fdiv_ctl0 = readl((void __iomem *)AUDIO_PLL1_FDIV_CTL0);
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pll_fdiv_ctl1 = readl((void __iomem *)AUDIO_PLL1_FDIV_CTL1);
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break;
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case AUDIO_PLL2_CLK:
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pll_gnrl_ctl = readl((void __iomem *)AUDIO_PLL2_GNRL_CTL);
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pll_fdiv_ctl0 = readl((void __iomem *)AUDIO_PLL2_FDIV_CTL0);
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pll_fdiv_ctl1 = readl((void __iomem *)AUDIO_PLL2_FDIV_CTL1);
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break;
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case VIDEO_PLL_CLK:
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pll_gnrl_ctl = readl((void __iomem *)VIDEO_PLL1_GNRL_CTL);
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pll_fdiv_ctl0 = readl((void __iomem *)VIDEO_PLL1_FDIV_CTL0);
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pll_fdiv_ctl1 = readl((void __iomem *)VIDEO_PLL1_FDIV_CTL1);
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break;
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default:
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printf("Not supported\n");
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return 0;
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}
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/* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
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if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
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return 0;
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if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
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return 0;
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/*
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* When BYPASS is equal to 1, PLL enters the bypass mode
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* regardless of the values of RESETB
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*/
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if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
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return 24000000u;
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if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
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puts("pll not locked\n");
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return 0;
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}
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if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK))
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return 0;
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main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >>
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INTPLL_MAIN_DIV_SHIFT;
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pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >>
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INTPLL_PRE_DIV_SHIFT;
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post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >>
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INTPLL_POST_DIV_SHIFT;
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k = pll_fdiv_ctl1 & GENMASK(15, 0);
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/* FFOUT = ((m + k / 65536) * FFIN) / (p * 2^s), 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6 */
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return lldiv((main_div * 65536 + k) * 24000000ULL, 65536 * pre_div * (1 << post_div));
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}
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enum intpll_out_freq {
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INTPLL_OUT_800M,
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INTPLL_OUT_1200M,
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INTPLL_OUT_1000M,
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INTPLL_OUT_2000M,
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};
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#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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#define LOCK_STATUS BIT(31)
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#define LOCK_SEL_MASK BIT(29)
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#define CLKE_MASK BIT(11)
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#define RST_MASK BIT(9)
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#define BYPASS_MASK BIT(4)
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#define MDIV_SHIFT 12
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#define MDIV_MASK GENMASK(21, 12)
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#define PDIV_SHIFT 4
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#define PDIV_MASK GENMASK(9, 4)
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#define SDIV_SHIFT 0
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#define SDIV_MASK GENMASK(2, 0)
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#define KDIV_SHIFT 0
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#define KDIV_MASK GENMASK(15, 0)
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struct imx_int_pll_rate_table {
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u32 rate;
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int mdiv;
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int pdiv;
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int sdiv;
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int kdiv;
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};
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static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
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PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
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PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
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PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
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PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
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PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
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};
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int fracpll_configure(enum pll_clocks pll, u32 freq)
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{
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int i;
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u32 tmp, div_val;
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void *pll_base;
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struct imx_int_pll_rate_table *rate;
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for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
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if (freq == imx8mm_fracpll_tbl[i].rate)
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break;
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}
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if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
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printf("No matched freq table %u\n", freq);
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return -EINVAL;
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}
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rate = &imx8mm_fracpll_tbl[i];
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switch (pll) {
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case ANATOP_DRAM_PLL:
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#define SRC_DDR1_ENABLE_MASK (0x8F000000UL)
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setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
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setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
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writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
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pll_base = (void __iomem *)DRAM_PLL_GNRL_CTL;
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break;
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default:
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return 0;
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}
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/* Bypass clock and set lock to pll output lock */
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tmp = readl(pll_base);
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tmp |= BYPASS_MASK;
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writel(tmp, pll_base);
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/* Enable RST */
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tmp &= ~RST_MASK;
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writel(tmp, pll_base);
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div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
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(rate->sdiv << SDIV_SHIFT);
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writel(div_val, pll_base + 4);
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writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
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__udelay(100);
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/* Disable RST */
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tmp |= RST_MASK;
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writel(tmp, pll_base);
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/* Wait Lock*/
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while (!(readl(pll_base) & LOCK_STATUS))
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;
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/* Bypass */
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tmp &= ~BYPASS_MASK;
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writel(tmp, pll_base);
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return 0;
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}
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void dram_pll_init(enum dram_pll_out_val pll_val)
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{
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u32 freq;
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switch (pll_val) {
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case DRAM_PLL_OUT_100M:
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freq = 100000000UL;
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break;
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case DRAM_PLL_OUT_667M:
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freq = 667000000UL;
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break;
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case DRAM_PLL_OUT_400M:
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freq = 400000000UL;
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break;
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case DRAM_PLL_OUT_600M:
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freq = 600000000UL;
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break;
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case DRAM_PLL_OUT_750M:
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freq = 750000000UL;
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break;
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case DRAM_PLL_OUT_800M:
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freq = 800000000UL;
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break;
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default:
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return;
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}
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fracpll_configure(ANATOP_DRAM_PLL, freq);
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}
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int intpll_configure(enum pll_clocks pll, enum intpll_out_freq freq)
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{
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void __iomem *pll_gnrl_ctl, __iomem *pll_div_ctl;
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u32 pll_div_ctl_val, pll_clke_masks;
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switch (pll) {
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case ANATOP_SYSTEM_PLL1:
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pll_gnrl_ctl = (void __iomem *)SYS_PLL1_GNRL_CTL;
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pll_div_ctl = (void __iomem *)SYS_PLL1_DIV_CTL;
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pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
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INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
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INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
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INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
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INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
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break;
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case ANATOP_SYSTEM_PLL2:
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pll_gnrl_ctl = (void __iomem *)SYS_PLL2_GNRL_CTL;
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pll_div_ctl = (void __iomem *)SYS_PLL2_DIV_CTL;
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pll_clke_masks = INTPLL_DIV20_CLKE_MASK |
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INTPLL_DIV10_CLKE_MASK | INTPLL_DIV8_CLKE_MASK |
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INTPLL_DIV6_CLKE_MASK | INTPLL_DIV5_CLKE_MASK |
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INTPLL_DIV4_CLKE_MASK | INTPLL_DIV3_CLKE_MASK |
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INTPLL_DIV2_CLKE_MASK | INTPLL_CLKE_MASK;
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break;
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case ANATOP_SYSTEM_PLL3:
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pll_gnrl_ctl = (void __iomem *)SYS_PLL3_GNRL_CTL;
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pll_div_ctl = (void __iomem *)SYS_PLL3_DIV_CTL;
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pll_clke_masks = INTPLL_CLKE_MASK;
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break;
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case ANATOP_ARM_PLL:
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pll_gnrl_ctl = (void __iomem *)ARM_PLL_GNRL_CTL;
|
||||
pll_div_ctl = (void __iomem *)ARM_PLL_DIV_CTL;
|
||||
pll_clke_masks = INTPLL_CLKE_MASK;
|
||||
break;
|
||||
case ANATOP_GPU_PLL:
|
||||
pll_gnrl_ctl = (void __iomem *)GPU_PLL_GNRL_CTL;
|
||||
pll_div_ctl = (void __iomem *)GPU_PLL_DIV_CTL;
|
||||
pll_clke_masks = INTPLL_CLKE_MASK;
|
||||
break;
|
||||
case ANATOP_VPU_PLL:
|
||||
pll_gnrl_ctl = (void __iomem *)VPU_PLL_GNRL_CTL;
|
||||
pll_div_ctl = (void __iomem *)VPU_PLL_DIV_CTL;
|
||||
pll_clke_masks = INTPLL_CLKE_MASK;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
};
|
||||
|
||||
switch (freq) {
|
||||
case INTPLL_OUT_800M:
|
||||
/* 24 * 0x190 / 3 / 2 ^ 2 */
|
||||
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x190) |
|
||||
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
|
||||
break;
|
||||
case INTPLL_OUT_1000M:
|
||||
/* 24 * 0xfa / 3 / 2 ^ 1 */
|
||||
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
|
||||
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1);
|
||||
break;
|
||||
case INTPLL_OUT_1200M:
|
||||
/* 24 * 0xc8 / 2 / 2 ^ 1 */
|
||||
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) |
|
||||
INTPLL_PRE_DIV_VAL(2) | INTPLL_POST_DIV_VAL(1);
|
||||
break;
|
||||
case INTPLL_OUT_2000M:
|
||||
/* 24 * 0xfa / 3 / 2 ^ 0 */
|
||||
pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) |
|
||||
INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
};
|
||||
/* Bypass clock and set lock to pll output lock */
|
||||
setbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK | INTPLL_LOCK_SEL_MASK);
|
||||
/* Enable reset */
|
||||
clrbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
|
||||
/* Configure */
|
||||
writel(pll_div_ctl_val, pll_div_ctl);
|
||||
|
||||
__udelay(100);
|
||||
|
||||
/* Disable reset */
|
||||
setbits_le32(pll_gnrl_ctl, INTPLL_RST_MASK);
|
||||
/* Wait Lock */
|
||||
while (!(readl(pll_gnrl_ctl) & INTPLL_LOCK_MASK))
|
||||
;
|
||||
/* Clear bypass */
|
||||
clrbits_le32(pll_gnrl_ctl, INTPLL_BYPASS_MASK);
|
||||
setbits_le32(pll_gnrl_ctl, pll_clke_masks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clock_init()
|
||||
{
|
||||
uint32_t val_cfg0;
|
||||
|
||||
clock_enable(CCGR_GIC, 1);
|
||||
|
||||
/* Configure ARM at 1GHz */
|
||||
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
|
||||
CLK_ROOT_SOURCE_SEL(0));
|
||||
|
||||
intpll_configure(ANATOP_ARM_PLL, INTPLL_OUT_1200M);
|
||||
|
||||
clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
|
||||
CLK_ROOT_SOURCE_SEL(1) | \
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
|
||||
|
||||
/*
|
||||
* According to ANAMIX SPEC
|
||||
* sys pll1 fixed at 800MHz
|
||||
* sys pll2 fixed at 1GHz
|
||||
* Here we only enable the outputs.
|
||||
*/
|
||||
val_cfg0 = readl(SYS_PLL1_GNRL_CTL);
|
||||
val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
|
||||
INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
|
||||
INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
|
||||
INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
|
||||
INTPLL_DIV20_CLKE_MASK;
|
||||
writel(val_cfg0, SYS_PLL1_GNRL_CTL);
|
||||
|
||||
val_cfg0 = readl(SYS_PLL2_GNRL_CTL);
|
||||
val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
|
||||
INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
|
||||
INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
|
||||
INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
|
||||
INTPLL_DIV20_CLKE_MASK;
|
||||
writel(val_cfg0, SYS_PLL2_GNRL_CTL);
|
||||
|
||||
intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_800M);
|
||||
/*
|
||||
* set uart clock root
|
||||
* 24M OSC
|
||||
*/
|
||||
clock_enable(CCGR_UART1, 0);
|
||||
clock_enable(CCGR_UART2, 0);
|
||||
clock_enable(CCGR_UART3, 0);
|
||||
clock_enable(CCGR_UART4, 0);
|
||||
clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_UART1, 1);
|
||||
clock_enable(CCGR_UART2, 1);
|
||||
clock_enable(CCGR_UART3, 1);
|
||||
clock_enable(CCGR_UART4, 1);
|
||||
|
||||
/*
|
||||
* set usdhc clock root
|
||||
* sys pll1 400M
|
||||
*/
|
||||
clock_enable(CCGR_USDHC1, 0);
|
||||
clock_enable(CCGR_USDHC2, 0);
|
||||
clock_enable(CCGR_USDHC3, 0);
|
||||
clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
|
||||
clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
|
||||
clock_enable(CCGR_USDHC1, 1);
|
||||
clock_enable(CCGR_USDHC2, 1);
|
||||
clock_enable(CCGR_USDHC3, 1);
|
||||
|
||||
clock_enable(CCGR_DDR1, 0);
|
||||
clock_set_target_val(DRAM_ALT_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
|
||||
clock_set_target_val(DRAM_APB_CLK_ROOT,CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
|
||||
clock_enable(CCGR_DDR1, 1);
|
||||
|
||||
/*
|
||||
* set qspi root
|
||||
* sys pll1 100M
|
||||
*/
|
||||
clock_enable(CCGR_QSPI, 0);
|
||||
clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_QSPI, 1);
|
||||
|
||||
/*
|
||||
* set rawnand root
|
||||
* sys pll1 400M
|
||||
*/
|
||||
clock_enable(CCGR_RAWNAND, 0);
|
||||
clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
|
||||
clock_enable(CCGR_RAWNAND, 1);
|
||||
|
||||
clock_enable(CCGR_WDOG1, 0);
|
||||
clock_enable(CCGR_WDOG2, 0);
|
||||
clock_enable(CCGR_WDOG3, 0);
|
||||
clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_WDOG1, 1);
|
||||
clock_enable(CCGR_WDOG2, 1);
|
||||
clock_enable(CCGR_WDOG3, 1);
|
||||
|
||||
clock_enable(CCGR_TEMP_SENSOR, 1);
|
||||
|
||||
clock_enable(CCGR_ECSPI1, 0);
|
||||
clock_enable(CCGR_ECSPI2, 0);
|
||||
clock_enable(CCGR_ECSPI3, 0);
|
||||
clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
|
||||
clock_enable(CCGR_ECSPI1, 1);
|
||||
clock_enable(CCGR_ECSPI2, 1);
|
||||
clock_enable(CCGR_ECSPI3, 1);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
int set_clk_qspi(void)
|
||||
{
|
||||
clock_enable(CCGR_QSPI, 0);
|
||||
/*
|
||||
* TODO: configure clock
|
||||
*/
|
||||
clock_enable(CCGR_QSPI, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int set_clk_enet(enum enet_freq type)
|
||||
{
|
||||
u32 target;
|
||||
u32 enet1_ref;
|
||||
|
||||
/* disable the clock first */
|
||||
clock_enable(CCGR_ENET1, 0);
|
||||
clock_enable(CCGR_SIM_ENET, 0);
|
||||
|
||||
switch (type) {
|
||||
case ENET_125MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
|
||||
break;
|
||||
case ENET_50MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
|
||||
break;
|
||||
case ENET_25MHZ:
|
||||
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* set enet axi clock 266Mhz */
|
||||
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
|
||||
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
|
||||
|
||||
target = CLK_ROOT_ON | enet1_ref |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
|
||||
clock_set_target_val(ENET_REF_CLK_ROOT, target);
|
||||
|
||||
target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
|
||||
clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
|
||||
|
||||
#ifdef CONFIG_FEC_MXC_25M_REF_CLK
|
||||
target = CLK_ROOT_ON |
|
||||
ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
|
||||
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
|
||||
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
|
||||
clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
|
||||
#endif
|
||||
/* enable clock */
|
||||
clock_enable(CCGR_SIM_ENET, 1);
|
||||
clock_enable(CCGR_ENET1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 get_root_src_clk(enum clk_root_src root_src)
|
||||
{
|
||||
switch (root_src) {
|
||||
case OSC_24M_CLK:
|
||||
return 24000000u;
|
||||
case OSC_HDMI_CLK:
|
||||
return 26000000u;
|
||||
case OSC_32K_CLK:
|
||||
return 32000u;
|
||||
case ARM_PLL_CLK:
|
||||
case GPU_PLL_CLK:
|
||||
case VPU_PLL_CLK:
|
||||
case SYSTEM_PLL1_800M_CLK:
|
||||
case SYSTEM_PLL1_400M_CLK:
|
||||
case SYSTEM_PLL1_266M_CLK:
|
||||
case SYSTEM_PLL1_200M_CLK:
|
||||
case SYSTEM_PLL1_160M_CLK:
|
||||
case SYSTEM_PLL1_133M_CLK:
|
||||
case SYSTEM_PLL1_100M_CLK:
|
||||
case SYSTEM_PLL1_80M_CLK:
|
||||
case SYSTEM_PLL1_40M_CLK:
|
||||
case SYSTEM_PLL2_1000M_CLK:
|
||||
case SYSTEM_PLL2_500M_CLK:
|
||||
case SYSTEM_PLL2_333M_CLK:
|
||||
case SYSTEM_PLL2_250M_CLK:
|
||||
case SYSTEM_PLL2_200M_CLK:
|
||||
case SYSTEM_PLL2_166M_CLK:
|
||||
case SYSTEM_PLL2_125M_CLK:
|
||||
case SYSTEM_PLL2_100M_CLK:
|
||||
case SYSTEM_PLL2_50M_CLK:
|
||||
case SYSTEM_PLL3_CLK:
|
||||
return decode_intpll(root_src);
|
||||
case DRAM_PLL1_CLK:
|
||||
case AUDIO_PLL1_CLK:
|
||||
case AUDIO_PLL2_CLK:
|
||||
case VIDEO_PLL_CLK:
|
||||
return decode_fracpll(root_src);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_root_clk(enum clk_root_index clock_id)
|
||||
{
|
||||
enum clk_root_src root_src;
|
||||
u32 post_podf, pre_podf, root_src_clk;
|
||||
|
||||
if (clock_root_enabled(clock_id) <= 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_prediv(clock_id, &pre_podf) < 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_postdiv(clock_id, &post_podf) < 0)
|
||||
return 0;
|
||||
|
||||
if (clock_get_src(clock_id, &root_src) < 0)
|
||||
return 0;
|
||||
|
||||
root_src_clk = get_root_src_clk(root_src);
|
||||
|
||||
return root_src_clk / (post_podf + 1) / (pre_podf + 1);
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum clk_root_index clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (clk >= CLK_ROOT_MAX)
|
||||
return 0;
|
||||
|
||||
if (clk == MXC_ARM_CLK) {
|
||||
return get_root_clk(ARM_A53_CLK_ROOT);
|
||||
}
|
||||
|
||||
if (clk == MXC_IPG_CLK) {
|
||||
clock_get_target_val(IPG_CLK_ROOT, &val);
|
||||
val = val & 0x3;
|
||||
return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
|
||||
}
|
||||
|
||||
return get_root_clk(clk);
|
||||
}
|
||||
|
||||
u32 imx_get_uartclk(void)
|
||||
{
|
||||
return mxc_get_clock(UART1_CLK_ROOT);
|
||||
}
|
||||
|
||||
u32 imx_get_fecclk(void)
|
||||
{
|
||||
return get_root_clk(ENET_AXI_CLK_ROOT);
|
||||
}
|
||||
|
||||
/*
|
||||
* Dump some clockes.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int do_mscale_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
u32 freq;
|
||||
|
||||
freq = decode_intpll(ARM_PLL_CLK);
|
||||
printf("ARM_PLL %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
|
||||
printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
|
||||
printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
|
||||
printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
|
||||
printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
|
||||
printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
|
||||
printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
|
||||
printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
|
||||
printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
|
||||
printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
|
||||
printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
|
||||
printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
|
||||
printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
|
||||
printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
|
||||
printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
|
||||
printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
|
||||
printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
|
||||
printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
|
||||
freq = decode_intpll(SYSTEM_PLL3_CLK);
|
||||
printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(UART1_CLK_ROOT);
|
||||
printf("UART1 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(USDHC1_CLK_ROOT);
|
||||
printf("USDHC1 %8d MHz\n", freq / 1000000);
|
||||
freq = mxc_get_clock(QSPI_CLK_ROOT);
|
||||
printf("QSPI %8d MHz\n", freq / 1000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
|
||||
"display clocks",
|
||||
""
|
||||
);
|
||||
#endif
|
||||
|
|
@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
#ifdef CONFIG_IMX8MQ
|
||||
static struct clk_root_map root_array[] = {
|
||||
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
|
||||
{OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
|
|
@ -477,6 +478,466 @@ static struct clk_root_map root_array[] = {
|
|||
{DRAM_PLL1_CLK}
|
||||
},
|
||||
};
|
||||
#else
|
||||
static struct clk_root_map root_array[] = {
|
||||
{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
|
||||
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
|
||||
{OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
|
||||
},
|
||||
{GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
|
||||
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
|
||||
{OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
|
||||
EXT_CLK_1, EXT_CLK_4}
|
||||
},
|
||||
{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
|
||||
EXT_CLK_1, EXT_CLK_3}
|
||||
},
|
||||
{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
|
||||
},
|
||||
{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
|
||||
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
|
||||
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
|
||||
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
|
||||
{OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
|
||||
{OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
|
||||
SYSTEM_PLL1_400M_CLK}
|
||||
},
|
||||
{PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
|
||||
},
|
||||
{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
|
||||
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
|
||||
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
|
||||
},
|
||||
{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
|
||||
{OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
|
||||
AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
|
||||
},
|
||||
{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
|
||||
},
|
||||
{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
|
||||
},
|
||||
{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
|
||||
},
|
||||
{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
|
||||
{OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
|
||||
VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
|
||||
OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
|
||||
},
|
||||
{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
|
||||
},
|
||||
{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
|
||||
VIDEO_PLL_CLK}
|
||||
},
|
||||
{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
|
||||
SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
|
||||
AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
|
||||
},
|
||||
{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
|
||||
SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
|
||||
},
|
||||
{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
|
||||
},
|
||||
{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
|
||||
},
|
||||
{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
|
||||
},
|
||||
{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
|
||||
},
|
||||
{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
|
||||
},
|
||||
{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
|
||||
},
|
||||
{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
|
||||
VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
|
||||
},
|
||||
{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
|
||||
SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
|
||||
},
|
||||
{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
|
||||
SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
|
||||
AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
|
||||
},
|
||||
{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
|
||||
},
|
||||
{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
|
||||
{OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
|
||||
},
|
||||
{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
|
||||
SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
|
||||
},
|
||||
{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
|
||||
EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
|
||||
EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
|
||||
},
|
||||
{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
|
||||
SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
|
||||
},
|
||||
{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
|
||||
SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
|
||||
},
|
||||
{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
|
||||
{OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
|
||||
SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
|
||||
SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
|
||||
},
|
||||
{VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
|
||||
{OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
|
||||
SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
|
||||
SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
|
||||
},
|
||||
{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
|
||||
{DRAM_PLL1_CLK}
|
||||
},
|
||||
{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
|
||||
{DRAM_PLL1_CLK}
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static int select(enum clk_root_index clock_id)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue