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imx8m: soc: Relocate u-boot to the top DDR in 4GB space 

The EFI memory init uses gd->ram_top for conventional memory. In
current implementation, the ram_top is below optee address. This cause
grub failed to allocation memory for initrd.
The change updates DDR bank setup functions to place the u-boot at top
DDR in 4GB space.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2022-04-07 15:55:56 +08:00 committed by Stefano Babic
parent 1166bd433a
commit 1c9bc0fffa
1 changed files with 70 additions and 51 deletions
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77
arch/arm/mach-imx/imx8m/soc.c
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@ -189,11 +189,9 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
void enable_caches(void) void enable_caches(void)
{ {
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
if (rom_pointer[1]) { * If OPTEE does not run, still update the MMU table according to dram banks structure
/* * to set correct dram size from board_phys_sdram_size
* TEE are loaded, So the ddr bank structures
* have been modified update mmu table accordingly
*/ */
int i = 0; int i = 0;
/* /*
@ -215,7 +213,6 @@ void enable_caches(void)
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
i++; entry++; i++; entry++;
} }
}
icache_enable(); icache_enable();
dcache_enable(); dcache_enable();
@ -227,12 +224,15 @@ __weak int board_phys_sdram_size(phys_size_t *size)
return -EINVAL; return -EINVAL;
*size = PHYS_SDRAM_SIZE; *size = PHYS_SDRAM_SIZE;
#ifdef PHYS_SDRAM_2_SIZE
*size += PHYS_SDRAM_2_SIZE;
#endif
return 0; return 0;
} }
int dram_init(void) int dram_init(void)
{ {
unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size; phys_size_t sdram_size;
int ret; int ret;
@ -246,13 +246,6 @@ int dram_init(void)
else else
gd->ram_size = sdram_size; gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
imx8m_mem_map[entry].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
return 0; return 0;
} }
@ -261,18 +254,28 @@ int dram_init_banksize(void)
int bank = 0; int bank = 0;
int ret; int ret;
phys_size_t sdram_size; phys_size_t sdram_size;
phys_size_t sdram_b1_size, sdram_b2_size;
ret = board_phys_sdram_size(&sdram_size); ret = board_phys_sdram_size(&sdram_size);
if (ret) if (ret)
return ret; return ret;
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0xc0000000) {
sdram_b1_size = 0xc0000000;
sdram_b2_size = sdram_size - 0xc0000000;
} else {
sdram_b1_size = sdram_size;
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM; gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) { if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1]; phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) { if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n"); puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1; return -1;
@ -280,35 +283,51 @@ int dram_init_banksize(void)
gd->bd->bi_dram[bank].start = optee_start + optee_size; gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM + gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_size - gd->bd->bi_dram[bank].start; sdram_b1_size - gd->bd->bi_dram[bank].start;
} }
} else { } else {
gd->bd->bi_dram[bank].size = sdram_size; gd->bd->bi_dram[bank].size = sdram_b1_size;
} }
#ifdef PHYS_SDRAM_2_SIZE if (sdram_b2_size) {
if (++bank >= CONFIG_NR_DRAM_BANKS) { if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1; return -1;
} }
gd->bd->bi_dram[bank].start = PHYS_SDRAM_2; gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE; gd->bd->bi_dram[bank].size = sdram_b2_size;
#endif }
return 0; return 0;
} }
phys_size_t get_effective_memsize(void) phys_size_t get_effective_memsize(void)
{ {
/* return the first bank as effective memory */ int ret;
if (rom_pointer[1]) phys_size_t sdram_size;
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); phys_size_t sdram_b1_size;
ret = board_phys_sdram_size(&sdram_size);
if (!ret) {
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0xc0000000) {
sdram_b1_size = 0xc0000000;
} else {
sdram_b1_size = sdram_size;
}
#ifdef PHYS_SDRAM_2_SIZE if (rom_pointer[1]) {
return gd->ram_size - PHYS_SDRAM_2_SIZE; /* We will relocate u-boot to Top of dram1. Tee position has two cases:
#else * 1. At the top of dram1, Then return the size removed optee size.
return gd->ram_size; * 2. In the middle of dram1, return the size of dram1.
#endif */
if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
}
return sdram_b1_size;
} else {
return PHYS_SDRAM_SIZE;
}
} }
ulong board_get_usable_ram_top(ulong total_size) ulong board_get_usable_ram_top(ulong total_size)