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net: e1000: Fix build warnings for 32-bit 

commit 6497e37 "net: e1000: Support 64-bit physical address" causes
compiler warnings on 32-bit U-Boot build below.

drivers/net/e1000.c: In function 'e1000_configure_tx':
drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default]
drivers/net/e1000.c: In function 'e1000_configure_rx':
drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default]

This commit fixes the build warnings.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Bin Meng 2015-08-26 06:17:27 -07:00 committed by Simon Glass
parent 7d31c6ab83
commit 1d8a078b29
1 changed files with 5 additions and 4 deletions
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9
drivers/net/e1000.c
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@ -4978,8 +4978,8 @@ e1000_configure_tx(struct e1000_hw *hw)
unsigned long tipg, tarc; unsigned long tipg, tarc;
uint32_t ipgr1, ipgr2; uint32_t ipgr1, ipgr2;
E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff); E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32); E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
E1000_WRITE_REG(hw, TDLEN, 128); E1000_WRITE_REG(hw, TDLEN, 128);
@ -5103,6 +5103,7 @@ e1000_configure_rx(struct e1000_hw *hw)
{ {
unsigned long rctl, ctrl_ext; unsigned long rctl, ctrl_ext;
rx_tail = 0; rx_tail = 0;
/* make sure receives are disabled while setting up the descriptors */ /* make sure receives are disabled while setting up the descriptors */
rctl = E1000_READ_REG(hw, RCTL); rctl = E1000_READ_REG(hw, RCTL);
E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
@ -5122,8 +5123,8 @@ e1000_configure_rx(struct e1000_hw *hw)
E1000_WRITE_FLUSH(hw); E1000_WRITE_FLUSH(hw);
} }
/* Setup the Base and Length of the Rx Descriptor Ring */ /* Setup the Base and Length of the Rx Descriptor Ring */
E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff); E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32); E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
E1000_WRITE_REG(hw, RDLEN, 128); E1000_WRITE_REG(hw, RDLEN, 128);