arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3
The device trees for the Beacon RZ/G2[MNH] boards have undergone some changes over time, so resync them now. Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford
Marek Vasut
parent
182754f43a
commit
1eaf61c84d
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@ -197,6 +197,14 @@
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compatible = "audio-graph-card";
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label = "rcar-sound";
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dais = <&rsnd_port0>, <&rsnd_port1>;
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widgets = "Microphone", "Mic Jack",
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"Line", "Line In Jack",
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"Headphone", "Headphone Jack";
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mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
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routing = "Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"IN3R", "MICBIAS",
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"Mic Jack", "IN3R";
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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@ -271,12 +279,12 @@
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&ehci0 {
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dr_mode = "otg";
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
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};
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&ehci1 {
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
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};
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&hdmi0 {
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@ -615,7 +623,7 @@
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};
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&rcar_sound {
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pinctrl-0 = <&sound_pins &sound_clk_pins>;
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pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
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pinctrl-names = "default";
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/* Single DAI */
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@ -639,7 +647,7 @@
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bitclock-master = <&rsnd_endpoint0>;
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frame-master = <&rsnd_endpoint0>;
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playback = <&ssi1 &dvc1 &src1>;
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playback = <&ssi1>, <&dvc1>, <&src1>;
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capture = <&ssi0>;
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};
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};
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@ -7,19 +7,10 @@
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#include <dt-bindings/clk/versaclock.h>
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/ {
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aliases {
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spi0 = &rpc;
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0xc000000>;
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};
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memory@57000000 {
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device_type = "memory";
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reg = <0x0 0x57000000 0x0 0x29000000>;
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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osc_32k: osc_32k {
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@ -59,12 +50,17 @@
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&avb {
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pinctrl-0 = <&avb_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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rx-internal-delay-ps = <1800>;
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tx-internal-delay-ps = <2000>;
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clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
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clock-names = "fck", "refclk";
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status = "okay";
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id004d.d074",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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@ -153,7 +149,7 @@
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};
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eeprom@50 {
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compatible = "microchip,at24c64", "atmel,24c64";
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compatible = "microchip,24c64", "atmel,24c64";
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pagesize = <32>;
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read-only; /* Manufacturing EEPROM programmed at factory */
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reg = <0x50>;
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@ -279,25 +275,6 @@
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};
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};
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&rpc {
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compatible = "renesas,rcar-gen3-rpc";
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num-cs = <1>;
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spi-max-frequency = <40000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "spi-flash", "jedec,spi-nor";
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spi-max-frequency = <40000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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@ -340,17 +317,17 @@
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vqmmc-supply = <®_1p8v>;
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bus-width = <8>;
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mmc-hs200-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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fixed-emmc-driver-type = <1>;
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status = "okay";
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};
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&usb2_clksel {
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status = "okay";
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clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
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<&versaclock5 3>, <&usb3s0_clk>;
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clock-names = "ehci_ohci", "hs-usb-if",
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"usb_extal", "usb_xtal";
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<&versaclock5 3>, <&usb3s0_clk>;
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status = "okay";
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};
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&usb3s0_clk {
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@ -21,6 +21,9 @@
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serial4 = &hscif2;
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serial5 = &scif5;
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ethernet0 = &avb;
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mmc0 = &sdhi3;
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mmc1 = &sdhi0;
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mmc2 = &sdhi2;
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};
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chosen {
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@ -22,6 +22,9 @@
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serial5 = &scif5;
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serial6 = &scif4;
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ethernet0 = &avb;
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mmc0 = &sdhi3;
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mmc1 = &sdhi0;
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mmc2 = &sdhi2;
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};
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chosen {
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@ -22,6 +22,9 @@
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serial5 = &scif5;
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serial6 = &scif4;
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ethernet0 = &avb;
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mmc0 = &sdhi3;
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mmc1 = &sdhi0;
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mmc2 = &sdhi2;
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};
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chosen {
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