diff --git a/board/freescale/imx8mq_aiy/spl.c b/board/freescale/imx8mq_aiy/spl.c
index d0ae36f37f..712c764edf 100644
--- a/board/freescale/imx8mq_aiy/spl.c
+++ b/board/freescale/imx8mq_aiy/spl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2019 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -167,23 +167,32 @@ int power_init_board(void)
 	p = pmic_get("BD71837");
 	pmic_probe(p);
 
-	/* unlock the PMIC regs */
+	/* Unlock reg */
 	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
 
-	/* Set BUCK2 output for ARM to 0.85v */
-	pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f);
+	/* Set BUCK5 output for DRAM to 1.0V */
+	/* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
 
-	/* Set BUCK5 output for DRAM to 0.9V */
-	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2);
+	/* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
 
-	/* Set BUCK6 output for VDD_3V3 to 3.1V */
-	pmic_reg_write(p, BD71837_BUCK6_VOLT, 0x1);
+	/* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
 
-	/* Set BUCK7 output for VDD_1V8 to 1.695V */
-	pmic_reg_write(p, BD71837_BUCK7_VOLT, 0x1);
+	/* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14);
+
+	/* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */
+	/* 0.7-1.3 (10mVstep) */
+	pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14);
 
 	/* lock the PMIC regs */
 	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
+
 	return 0;
 }
 #endif