Merge branch 'master' of git://git.denx.de/u-boot-atmel

arch/arm/mach-at91/Kconfig

@@ -96,6 +96,11 @@ config TARGET_SAMA5D4EK
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_MA5D4EVK
+	bool "DENX MA5D4EVK Evaluation Kit"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_MEESC
 	bool "Support meesc"
 	select CPU_ARM926EJS
@@ -115,6 +120,11 @@ config TARGET_SMARTWEB
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
+config TARGET_VINCO
+	bool "Support VINCO"
+	select CPU_V7
+	select SUPPORT_SPL
+
 endchoice
 
 config SYS_SOC
@@ -135,8 +145,10 @@ source "board/atmel/sama5d4_xplained/Kconfig"
 source "board/atmel/sama5d4ek/Kconfig"
 source "board/bluewater/snapper9260/Kconfig"
 source "board/calao/usb_a9263/Kconfig"
+source "board/denx/ma5d4evk/Kconfig"
 source "board/egnite/ethernut5/Kconfig"
 source "board/esd/meesc/Kconfig"
+source "board/l+g/vinco/Kconfig"
 source "board/mini-box/picosam9g45/Kconfig"
 source "board/ronetix/pm9261/Kconfig"
 source "board/ronetix/pm9263/Kconfig"

arch/arm/mach-at91/Makefile

@@ -15,6 +15,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
 endif
 
+obj-y += clock.o
 obj-$(CONFIG_CPU_ARM920T)	+= arm920t/
 obj-$(CONFIG_CPU_ARM926EJS)	+= arm926ejs/
 obj-$(CONFIG_CPU_V7)		+= armv7/

arch/arm/mach-at91/arm920t/at91rm9200_devices.c

@@ -14,7 +14,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -34,29 +34,23 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTA, 18, PUP);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 20, PUP);		/* RXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 21, 1);		/* TXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 22, PUP);		/* RXD2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 23, 1);		/* TXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)

arch/arm/mach-at91/arm920t/clock.c

@@ -18,6 +18,8 @@
 # error You need to define CONFIG_AT91FAMILY in your board config!
 #endif
 
+#define EN_PLLB_TIMEOUT	500
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long at91_css_to_rate(unsigned long css)
@@ -155,3 +157,39 @@ int at91_clock_init(unsigned long main_clock)
 
 	return 0;
 }
+
+int at91_pllb_clk_enable(u32 pllbr)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(pllbr, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to enable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int at91_pllb_clk_disable(void)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(0, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to disable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}

arch/arm/mach-at91/arm920t/timer.c

@@ -19,7 +19,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,10 +29,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int timer_init(void)
 {
 	at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 
-	/* enables TC1.0 clock */
+	at91_periph_clk_enable(ATMEL_ID_TC0);
-	writel(1 << ATMEL_ID_TC0, &pmc->pcer);	/* enable clock */
 
 	writel(0, &tc->bcr);
 	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |

arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c

@@ -11,8 +11,8 @@
 #include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -32,51 +32,40 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
@@ -106,14 +95,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
@@ -145,9 +131,7 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
-	/* Enable EMAC clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
 	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
@@ -190,9 +174,7 @@ void at91_macb_hw_init(void)
 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
-	/* Enable mci clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI);
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
 
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
 #if defined(CONFIG_ATMEL_MCI_PORTB)

arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c

@@ -9,7 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -29,51 +29,40 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
@@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 30, PUP);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 31, PUP);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 29, PUP);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);

arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c

@@ -13,7 +13,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -33,51 +33,40 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTD, 1, PUP);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 3, PUP);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 30, PUP);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTC, 31, 1);		/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_b_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
 	at91_set_b_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
 	at91_set_b_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
@@ -107,14 +96,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 12, PUP);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, PUP);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
@@ -146,9 +132,7 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 #if defined(CONFIG_GENERIC_ATMEL_MCI)
 void at91_mci_hw_init(void)
 {
-	/* Enable mci clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI1);
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
 
 	at91_set_a_periph(AT91_PIO_PORTA, 6, PUP);	/* MCI1_CK */
 
@@ -207,12 +191,9 @@ void at91_uhp_hw_init(void)
 #ifdef CONFIG_AT91_CAN
 void at91_can_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CAN_TX */
 	at91_set_a_periph(AT91_PIO_PORTA, 14, 1);	/* CAN_RX */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_CAN);
-	writel(1 << ATMEL_ID_CAN, &pmc->pcer);
 }
 #endif

arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c

@@ -8,7 +8,7 @@
 
 #include <common.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 
@@ -29,51 +29,40 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTB, 18, PUP);	/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 7, PUP);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
@@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 15, PUP);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 16, PUP);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
@@ -169,8 +155,6 @@ void at91_macb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 void at91_mci_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* MCI0 CLK */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* MCI0 CDA */
 	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* MCI0 DA0 */
@@ -178,7 +162,6 @@ void at91_mci_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* MCI0 DA2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* MCI0 DA3 */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
-	writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
 }
 #endif

arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c

@@ -8,8 +8,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
 
 unsigned int has_lcdc()
 {
@@ -18,60 +18,47 @@ unsigned int has_lcdc()
 
 void at91_serial0_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_serial3_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_b_periph(AT91_PIO_PORTC, 22, 1);		/* TXD3 */
 	at91_set_b_periph(AT91_PIO_PORTC, 23, 0);		/* RXD3 */
-	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART3);
 }
 
 void at91_seriald_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0))
 		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
@@ -85,14 +72,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
 	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
 	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0))
 		at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
@@ -107,8 +91,6 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 
 void at91_mci_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* MCCK */
 	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* MCCDA */
 	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* MCDA0 */
@@ -116,14 +98,12 @@ void at91_mci_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* MCDA2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* MCDA3 */
 
-	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_HSMCI0);
 }
 
 #ifdef CONFIG_LCD
 void at91_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDPWR */
 	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDVSYNC */
 	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDHSYNC */
@@ -156,6 +136,6 @@ void at91_lcd_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
 	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 }
 #endif

arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c

@@ -9,7 +9,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 /*
@@ -29,51 +29,40 @@
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);		/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTA, 7, PUP);		/* RXD0 */
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTA, 12, PUP);		/* RXD1 */
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 14, PUP);		/* RXD2 */
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 21, PUP);		/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 22, 1);		/* DTXD */
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 25, PUP);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTA, 26, PUP);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTA, 27, PUP);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI);
-	writel(1 << ATMEL_ID_SPI, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
@@ -105,8 +94,6 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 void at91_mci_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 2, 0);        /* MCI CLK */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);        /* MCI CDA */
 	at91_set_a_periph(AT91_PIO_PORTA, 0, 0);        /* MCI DA0 */
@@ -114,7 +101,6 @@ void at91_mci_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTA, 4, 0);        /* MCI DA2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 5, 0);        /* MCI DA3 */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI);
-	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
 }
 #endif

arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c

@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 
@@ -64,42 +64,34 @@ char *get_cpu_name()
 
 void at91_seriald_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* DTXD */
 
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_SYS);
 }
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 0, 1);	/* TXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* RXD */
 
-	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART0);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);	/* TXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 6, 0);	/* RXD */
 
-	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART1);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* TXD */
 	at91_set_a_periph(AT91_PIO_PORTA, 8, 0);	/* RXD */
 
-	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_USART2);
 }
 
 void at91_mci_hw_init(void)
@@ -112,22 +104,17 @@ void at91_mci_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTA, 19, 1);	/* MCDA2 */
 	at91_set_a_periph(AT91_PIO_PORTA, 20, 1);	/* MCDA3 */
 
-	/* Enable clock for MCI0 */
+	at91_periph_clk_enable(ATMEL_ID_HSMCI0);
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
 }
 
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SPI0_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
-	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0))
 		at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
@@ -149,14 +136,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_b_periph(AT91_PIO_PORTA, 21, 0);	/* SPI1_MISO */
 	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* SPI1_MOSI */
 	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* SPI1_SPCK */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI1);
-	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0))
 		at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
@@ -193,11 +177,9 @@ void at91_uhp_hw_init(void)
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	if (has_emac0()) {
 		/* Enable EMAC0 clock */
-		writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+		at91_periph_clk_enable(ATMEL_ID_EMAC0);
 		/* EMAC0 pins setup */
 		at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* ETXCK */
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* ERXDV */
@@ -213,7 +195,7 @@ void at91_macb_hw_init(void)
 
 	if (has_emac1()) {
 		/* Enable EMAC1 clock */
-		writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
+		at91_periph_clk_enable(ATMEL_ID_EMAC1);
 		/* EMAC1 pins setup */
 		at91_set_b_periph(AT91_PIO_PORTC, 29, 0);	/* ETXCK */
 		at91_set_b_periph(AT91_PIO_PORTC, 28, 0);	/* ECRSDV */

arch/arm/mach-at91/arm926ejs/clock.c

@@ -18,6 +18,8 @@
 # error You need to define CONFIG_AT91FAMILY in your board config!
 #endif
 
+#define EN_PLLB_TIMEOUT	500
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long at91_css_to_rate(unsigned long css)
@@ -243,9 +245,38 @@ void at91_mck_init(u32 mckr)
 		;
 }
 
-void at91_periph_clk_enable(int id)
+int at91_pllb_clk_enable(u32 pllbr)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
 
-	writel(1 << id, &pmc->pcer);
+	start_time = get_timer(0);
+	writel(pllbr, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to enable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int at91_pllb_clk_disable(void)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(0, &pmc->pllbr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
+			printf("ERROR: failed to disable PLLB\n");
+			return -1;
+		}
+	}
+
+	return 0;
 }

arch/arm/mach-at91/arm926ejs/cpu.c

@@ -10,7 +10,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pit.h>
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>

arch/arm/mach-at91/arm926ejs/timer.c

@@ -10,7 +10,6 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <div64.h>
 
@@ -38,11 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int timer_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
 
-	/* Enable PITC Clock */
+	at91_periph_clk_enable(ATMEL_ID_SYS);
-	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
 
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

arch/arm/mach-at91/armv7/clock.c

@@ -150,32 +150,6 @@ void at91_mck_init(u32 mckr)
 		;
 }
 
-void at91_periph_clk_enable(int id)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 regval;
-
-	if (id > AT91_PMC_PCR_PID_MASK)
-		return;
-
-	regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
-
-	writel(regval, &pmc->pcr);
-}
-
-void at91_periph_clk_disable(int id)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 regval;
-
-	if (id > AT91_PMC_PCR_PID_MASK)
-		return;
-
-	regval = AT91_PMC_PCR_CMD_WRITE | id;
-
-	writel(regval, &pmc->pcr);
-}
-
 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

arch/arm/mach-at91/armv7/cpu.c

@@ -12,7 +12,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pit.h>
 #include <asm/arch/at91_gpbr.h>
 #include <asm/arch/clk.h>

arch/arm/mach-at91/armv7/sama5d2_devices.c

@@ -7,7 +7,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5d2.h>
 
@@ -48,9 +47,7 @@ char *get_cpu_name()
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 void at91_udp_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_upll_clk_enable();
-
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
 
 	at91_periph_clk_enable(ATMEL_ID_UDPHS);
 }

arch/arm/mach-at91/armv7/sama5d3_devices.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/arch/sama5d3.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
@@ -208,10 +207,8 @@ void at91_lcd_hw_init(void)
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 void at91_udp_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable UPLL clock */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	at91_upll_clk_enable();
 	/* Enable UDPHS clock */
 	at91_periph_clk_enable(ATMEL_ID_UDPHS);
 }

arch/arm/mach-at91/armv7/sama5d4_devices.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5_sfr.h>
 #include <asm/arch/sama5d4.h>
@@ -37,10 +36,8 @@ char *get_cpu_name()
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 void at91_udp_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable UPLL clock */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	at91_upll_clk_enable();
 	/* Enable UDPHS clock */
 	at91_periph_clk_enable(ATMEL_ID_UDPHS);
 }

arch/arm/mach-at91/armv7/timer.c

@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <div64.h>
 

arch/arm/mach-at91/atmel_sfr.c

@@ -19,3 +19,10 @@ void redirect_int_from_saic_to_aic(void)
 		writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
 	}
 }
+
+void configure_2nd_sram_as_l2_cache(void)
+{
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	writel(1, &sfr->l2cc_hramc);
+}

arch/arm/mach-at91/clock.c

@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+
+#define EN_UPLL_TIMEOUT		500
+
+void at91_periph_clk_enable(int id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+#ifdef CPU_HAS_PCR
+	u32 regval;
+	u32 div_value;
+
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return;
+
+	writel(id, &pmc->pcr);
+
+	div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
+
+	regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
+
+	writel(regval, &pmc->pcr);
+#else
+	writel(0x01 << id, &pmc->pcer);
+#endif
+}
+
+void at91_periph_clk_disable(int id)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+#ifdef CPU_HAS_PCR
+	u32 regval;
+
+	if (id > AT91_PMC_PCR_PID_MASK)
+		return;
+
+	regval = AT91_PMC_PCR_CMD_WRITE | id;
+
+	writel(regval, &pmc->pcr);
+#else
+	writel(0x01 << id, &pmc->pcdr);
+#endif
+}
+
+void at91_system_clk_enable(int sys_clk)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(sys_clk, &pmc->scer);
+}
+
+void at91_system_clk_disable(int sys_clk)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(sys_clk, &pmc->scdr);
+}
+
+int at91_upll_clk_enable(void)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	if ((readl(&pmc->uckr) & AT91_PMC_UPLLEN) == AT91_PMC_UPLLEN)
+		return 0;
+
+	start_time = get_timer(0);
+	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
+			printf("ERROR: failed to enable UPLL\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int at91_upll_clk_disable(void)
+{
+	struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	ulong start_time, tmp_time;
+
+	start_time = get_timer(0);
+	writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
+	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
+		tmp_time = get_timer(0);
+		if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
+			printf("ERROR: failed to stop UPLL\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+void at91_usb_clk_init(u32 value)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(value, &pmc->usb);
+}
+
+void at91_pllicpr_init(u32 icpr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(icpr, &pmc->pllicpr);
+}

arch/arm/mach-at91/include/mach/at91_common.h

@@ -34,5 +34,6 @@ void at91_spl_board_init(void);
 void at91_disable_wdt(void);
 void matrix_init(void);
 void redirect_int_from_saic_to_aic(void);
+void configure_2nd_sram_as_l2_cache(void);
 
 #endif /* AT91_COMMON_H */

arch/arm/mach-at91/include/mach/at91_pmc.h

@@ -51,19 +51,15 @@ typedef struct at91_pmc {
 	u32	imr;		/* 0x6C Interrupt Mask Register */
 	u32	reserved4[4];
 	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
-	u32	reserved5[21];
+	u32	reserved5[24];
 	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
 	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CPU_HAS_PCR
+	u32	reserved6[5];
-	u32	reserved6[8];
 	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
 	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
 	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
 	u32	pcr;		/* 0x10c Periperial Control Register */
 	u32	ocr;		/* 0x110 Oscillator Calibration Register */
-#else
-	u32	reserved8[5];
-#endif
 } at91_pmc_t;
 
 #endif	/* end not assembly */
@@ -250,4 +246,11 @@ typedef struct at91_pmc {
 #define		AT91_PMC_GCKRDY		(1 << 24)
 
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
+
+/* PLL Charge Pump Current Register (PMC_PLLICPR) */
+#define AT91_PMC_ICP_PLLA(x)		(((x) & 0x3) << 0)
+#define AT91_PMC_IPLL_PLLA(x)		(((x) & 0x7) << 8)
+#define AT91_PMC_ICP_PLLU(x)		(((x) & 0x3) << 16)
+#define AT91_PMC_IVCO_PLLU(x)		(((x) & 0x3) << 24)
+
 #endif

arch/arm/mach-at91/include/mach/clk.h

@@ -128,5 +128,13 @@ void at91_periph_clk_enable(int id);
 void at91_periph_clk_disable(int id);
 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
 u32 at91_get_periph_generated_clk(u32 id);
+void at91_system_clk_enable(int sys_clk);
+void at91_system_clk_disable(int sys_clk);
+int at91_upll_clk_enable(void);
+int at91_upll_clk_disable(void);
+void at91_usb_clk_init(u32 value);
+int at91_pllb_clk_enable(u32 pllbr);
+int at91_pllb_clk_disable(void);
+void at91_pllicpr_init(u32 icpr);
 
 #endif /* __ASM_ARM_ARCH_CLK_H__ */

arch/arm/mach-at91/include/mach/sama5_sfr.h

@@ -25,6 +25,7 @@ struct atmel_sfr {
 	u32 sn0;		/* 0x4c */
 	u32 sn1;		/* 0x50 */
 	u32 aicredir;	/* 0x54 */
+	u32 l2cc_hramc;	/* 0x58 */
 };
 
 /* Bit field in DDRCFG */

arch/arm/mach-at91/phy.c

@@ -15,7 +15,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <watchdog.h>
 

arch/arm/mach-at91/sdram.c

@@ -13,7 +13,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/gpio.h>
 

arch/arm/mach-at91/spl_at91.c

@@ -14,7 +14,6 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_wdt.h>
 #include <asm/arch/clk.h>
@@ -77,8 +76,6 @@ void __weak spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	lowlevel_clock_init();
 	at91_disable_wdt();
 
@@ -86,7 +83,7 @@ void board_init_f(ulong dummy)
 	 * At this stage the main oscillator is supposed to be enabled
 	 * PCK = MCK = MOSC
 	 */
-	writel(0x00, &pmc->pllicpr);
+	at91_pllicpr_init(0x00);
 
 	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
 	at91_plla_init(CONFIG_SYS_AT91_PLLA);

arch/arm/mach-at91/spl_atmel.c

@@ -79,6 +79,10 @@ void board_init_f(ulong dummy)
 {
 	switch_to_main_crystal_osc();
 
+#ifdef CONFIG_SAMA5D2
+	configure_2nd_sram_as_l2_cache();
+#endif
+
 	/* disable watchdog */
 	at91_disable_wdt();
 

board/atmel/at91rm9200ek/at91rm9200ek.c

@@ -14,7 +14,6 @@
 #include <netdev.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/io.h>
 

board/atmel/at91rm9200ek/led.c

@@ -12,7 +12,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/at91_pio.h>
 #include <status_led.h>
 
@@ -59,11 +59,9 @@ void	red_led_off(void)
 
 void coloured_LED_init (void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
 	at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
 
-	/* Enable PIOB clock */
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
 	/* Disable peripherals on LEDs */
 	writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);

board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -11,7 +11,7 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <atmel_mci.h>
 
@@ -70,11 +70,9 @@ static void at91sam9260ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9260ek_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 
-	/* Enable EMAC clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -122,12 +120,9 @@ int board_mmc_init(bd_t *bd)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOC),
-		&pmc->pcer);
 
 	return 0;
 }

board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9261_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
@@ -35,7 +34,6 @@ static void at91sam9261ek_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
@@ -74,7 +72,7 @@ static void at91sam9261ek_nand_hw_init(void)
 		       AT91_SMC_MODE_TDF_CYCLE(2),
 		       &smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -161,8 +159,6 @@ void lcd_disable(void)
 
 static void at91sam9261ek_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
 	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
 	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
@@ -186,7 +182,7 @@ static void at91sam9261ek_lcd_hw_init(void)
 	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
 	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
 
-	writel(AT91_PMC_HCK1, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_HCK1);
 
 	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
 #ifdef CONFIG_AT91SAM9261EK

board/atmel/at91sam9261ek/led.c

@@ -8,17 +8,15 @@
 
 #include <common.h>
 #include <asm/arch/at91sam9261.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
 #include <asm/io.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable clock */
-	writel(ATMEL_ID_PIOA, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -11,7 +11,6 @@
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
@@ -39,7 +38,6 @@ static void at91sam9263ek_nand_hw_init(void)
 	unsigned long csa;
 	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
 	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
-	at91_pmc_t    *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	/* Enable CS3 */
 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -68,8 +66,8 @@ static void at91sam9263ek_nand_hw_init(void)
 		       AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-		&pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -82,11 +80,9 @@ static void at91sam9263ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -139,8 +135,6 @@ void lcd_disable(void)
 
 static void at91sam9263ek_lcd_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
 	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
 	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
@@ -164,7 +158,7 @@ static void at91sam9263ek_lcd_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
 	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 	gd->fb_base = ATMEL_BASE_SRAM0;
 }
 
@@ -226,12 +220,9 @@ int board_mmc_init(bd_t *bd)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOCDE),
-		&pmc->pcer);
 
 	at91_seriald_hw_init();
 	return 0;

board/atmel/at91sam9263ek/led.c

@@ -9,16 +9,13 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91sam9263.h>
+#include <asm/arch/clk.h>
 
 void coloured_LED_init(void)
 {
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-
-	writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE,
-		&pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
@@ -36,7 +35,6 @@ void at91sam9m10g45ek_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
@@ -63,7 +61,7 @@ void at91sam9m10g45ek_nand_hw_init(void)
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -130,13 +128,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable DDR2 clock */
+	at91_system_clk_enable(AT91_PMC_DDR);
-	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
@@ -146,9 +142,7 @@ void mem_init(void)
 #ifdef CONFIG_CMD_USB
 static void at91sam9m10g45ek_usb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
-
-	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 
 	at91_set_gpio_output(AT91_PIN_PD1, 0);
 	at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -158,11 +152,9 @@ static void at91sam9m10g45ek_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9m10g45ek_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -222,8 +214,6 @@ void lcd_disable(void)
 
 static void at91sam9m10g45ek_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
@@ -255,7 +245,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void)
 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 
 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 }

board/atmel/at91sam9m10g45ek/led.c

@@ -9,15 +9,12 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9g45.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

board/atmel/at91sam9n12ek/at91sam9n12ek.c

@@ -10,7 +10,6 @@
 #include <asm/arch/at91sam9x5_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
@@ -208,9 +207,8 @@ void at91sam9n12ek_usb_hw_init(void)
 
 int board_early_init_f(void)
 {
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOAB);
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
-	writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
 
 	at91_seriald_hw_init();
 	return 0;

board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9rl_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
@@ -36,7 +35,6 @@ static void at91sam9rlek_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
@@ -64,7 +62,7 @@ static void at91sam9rlek_nand_hw_init(void)
 		AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -106,8 +104,6 @@ void lcd_disable(void)
 }
 static void at91sam9rlek_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
 	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
 	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
@@ -130,7 +126,7 @@ static void at91sam9rlek_lcd_hw_init(void)
 	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
 	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 }
 
 #ifdef CONFIG_LCD_INFO
@@ -174,12 +170,10 @@ int board_mmc_init(bd_t *bis)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
-		(1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
-		&pmc->pcer);
 
 	return 0;
 }

board/atmel/at91sam9rlek/led.c

@@ -8,16 +8,13 @@
 
 #include <common.h>
 #include <asm/arch/at91sam9rl.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
-
-	/* Enable clock */
-	writel(ATMEL_ID_PIOD, &pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);

board/atmel/at91sam9x5ek/at91sam9x5ek.c

@@ -9,10 +9,9 @@
 #include <asm/arch/at91sam9x5_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
 #include <lcd.h>
 #include <atmel_hlcdc.h>
 #include <atmel_mci.h>
@@ -39,7 +38,6 @@ static void at91sam9x5ek_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */
@@ -72,7 +70,7 @@ static void at91sam9x5ek_nand_hw_init(void)
 		AT91_SMC_MODE_TDF_CYCLE(1),
 		&smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOCD);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -141,8 +139,6 @@ void lcd_disable(void)
 
 static void at91sam9x5ek_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	if (has_lcdc()) {
 		at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
 		at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
@@ -176,7 +172,7 @@ static void at91sam9x5ek_lcd_hw_init(void)
 		at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
 		at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
 
-		writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+		at91_periph_clk_enable(ATMEL_ID_LCDC);
 	}
 }
 

board/atmel/sama5d2_xplained/sama5d2_xplained.c

@@ -15,7 +15,6 @@
 #include <version.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/atmel_pio4.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/atmel_usba_udc.h>

board/atmel/sama5d3_xplained/sama5d3_xplained.c

@@ -10,7 +10,6 @@
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -184,14 +183,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
@@ -199,7 +197,6 @@ void mem_init(void)
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -208,7 +205,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x3 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 
 	tmp = AT91_PMC_MCKR_MDIV_4 |
 	      AT91_PMC_MCKR_CSS_PLLA;

board/atmel/sama5d3xek/sama5d3xek.c

@@ -10,7 +10,6 @@
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -443,14 +442,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
@@ -458,7 +456,6 @@ void mem_init(void)
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -467,7 +464,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x3 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 
 	tmp = AT91_PMC_MCKR_MDIV_4 |
 	      AT91_PMC_MCKR_CSS_PLLA;

board/atmel/sama5d4_xplained/sama5d4_xplained.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/atmel_usba_udc.h>
@@ -383,14 +382,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
@@ -398,7 +396,6 @@ void mem_init(void)
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -407,7 +404,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x0 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 
 	tmp = AT91_PMC_MCKR_H32MXDIV |
 	      AT91_PMC_MCKR_PLLADIV_2 |

board/atmel/sama5d4ek/sama5d4ek.c

@@ -8,7 +8,6 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/atmel_usba_udc.h>
@@ -379,14 +378,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable MPDDR clock */
+	/* Enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_DDR);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
@@ -394,7 +392,6 @@ void mem_init(void)
 
 void at91_pmc_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	u32 tmp;
 
 	tmp = AT91_PMC_PLLAR_29 |
@@ -403,7 +400,7 @@ void at91_pmc_init(void)
 	      AT91_PMC_PLLXR_DIV(1);
 	at91_plla_init(tmp);
 
-	writel(0x0 << 8, &pmc->pllicpr);
+	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 
 	tmp = AT91_PMC_MCKR_H32MXDIV |
 	      AT91_PMC_MCKR_PLLADIV_2 |

board/bluewater/snapper9260/snapper9260.c

@@ -15,7 +15,7 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/atmel_serial.h>
 #include <net.h>
@@ -31,11 +31,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void macb_hw_init(void)
 {
-	struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	/* Disable pull-ups to prevent PHY going into test mode */
 	writel(pin_to_mask(AT91_PIN_PA14) |
@@ -108,12 +106,9 @@ static void nand_hw_init(void)
 
 int board_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable PIO clocks */
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	writel((1 << ATMEL_ID_PIOA) |
-	       (1 << ATMEL_ID_PIOB) |
-	       (1 << ATMEL_ID_PIOC), &pmc->pcer);
 
 	/* The mach-type is the same for both Snapper 9260 and 9G20 */
 	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;

board/calao/usb_a9263/usb_a9263.c

@@ -12,7 +12,7 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm-generic/gpio.h>
 #include <asm/io.h>
@@ -43,7 +43,6 @@ static void usb_a9263_nand_hw_init(void)
 	unsigned long csa;
 	at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
 	at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
 
 	/* Enable CS3 */
 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -66,7 +65,8 @@ static void usb_a9263_nand_hw_init(void)
 	       AT91_SMC_MODE_DBW_8 |
 	       AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 
 	/* Configure RDY/BSY */
 	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
@@ -81,10 +81,7 @@ static void usb_a9263_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void usb_a9263_macb_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:

board/denx/ma5d4evk/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_MA5D4EVK
+
+config SYS_BOARD
+	default "ma5d4evk"
+
+config SYS_VENDOR
+	default "denx"
+
+config SYS_CONFIG_NAME
+	default "ma5d4evk"
+
+endif

board/denx/ma5d4evk/MAINTAINERS

@@ -0,0 +1,6 @@
+DENX MA5D4EVK BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Maintained
+F:	board/denx/ma5d4evk/
+F:	include/configs/ma5d4evk.h
+F:	configs/ma5d4evk_defconfig

board/denx/ma5d4evk/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ma5d4evk.o

board/denx/ma5d4evk/ma5d4evk.c

@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void ma5d4evk_spi0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_CMD_USB
+static void ma5d4evk_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col			= 800,
+	.vl_row			= 480,
+	.vl_clk			= 33500000,
+	.vl_bpix		= LCD_BPP,
+	.vl_tft			= 1,
+	.vl_hsync_len		= 10,
+	.vl_left_margin		= 89,
+	.vl_right_margin	= 164,
+	.vl_vsync_len		= 10,
+	.vl_upper_margin	= 23,
+	.vl_lower_margin	= 10,
+	.mmio			= ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)	{ /* Empty! */ }
+void lcd_disable(void)	{ /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+	return 1;
+}
+
+static void ma5d4evk_lcd_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTA, 24, 1);	/* LCDPWM */
+	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 29, 1);	/* LCDDEN */
+
+	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
+	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
+	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+/* On-SoM eMMC */
+void ma5d4evk_mci0_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI1 CDA */
+	at91_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI1 DA0 */
+	at91_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI1 DA1 */
+	at91_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI1 DA2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI1 DA3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI1 DA4 */
+	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI1 DA5 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI1 DA6 */
+	at91_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI1 DA7 */
+	at91_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the internal pull
+	 * down to save the power.
+	 */
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+
+/* On-board MicroSD slot */
+void ma5d4evk_mci1_hw_init(void)
+{
+	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
+	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
+	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
+	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
+	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
+	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the internal pull
+	 * down to save the power.
+	 */
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+	/* Deal with WP pin on the microSD slot. */
+	at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* De-assert reset on On-SoM eMMC */
+	at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
+	at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
+
+	ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
+	if (ret)	/* eMMC init failed, skip it. */
+		at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
+
+	/* Enable the power supply to On-board MicroSD */
+	at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
+
+	ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
+	if (ret)	/* uSD init failed, power it down. */
+		at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
+
+	return 0;
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void ma5d4evk_macb0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void ma5d4evk_serial_hw_init(void)
+{
+	/* USART0 */
+	at91_set_a_periph(AT91_PIO_PORTD, 13, 1);	/* TXD */
+	at91_set_a_periph(AT91_PIO_PORTD, 12, 0);	/* RXD */
+	at91_set_a_periph(AT91_PIO_PORTD, 11, 0);	/* RTS */
+	at91_set_a_periph(AT91_PIO_PORTD, 10, 0);	/* CTS */
+	at91_periph_clk_enable(ATMEL_ID_USART0);
+
+	/* USART1 */
+	at91_set_a_periph(AT91_PIO_PORTD, 17, 1);	/* TXD */
+	at91_set_a_periph(AT91_PIO_PORTD, 16, 0);	/* RXD */
+	at91_set_a_periph(AT91_PIO_PORTD, 15, 0);	/* RTS */
+	at91_set_a_periph(AT91_PIO_PORTD, 14, 0);	/* CTS */
+	at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	/* Configure LEDs as OFF */
+	at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
+
+	/* Reset CAN controllers */
+	at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
+	udelay(100);
+	at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
+	at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
+
+	ma5d4evk_serial_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	ma5d4evk_spi0_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	ma5d4evk_mci0_hw_init();
+	ma5d4evk_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	ma5d4evk_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	ma5d4evk_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	ma5d4evk_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	ma5d4evk_spi0_hw_init();
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x0 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif

board/egnite/ethernut5/ethernut5.c

@@ -67,8 +67,8 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_spi.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
@@ -151,12 +151,10 @@ static void ethernut5_nand_hw_init(void)
  */
 int board_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
-	/* Enable clocks for all PIOs */
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOC),
-		&pmc->pcer);
 	/* Set adress of boot parameters. */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 	/* Initialize UARTs and power management. */
@@ -179,10 +177,9 @@ int board_eth_init(bd_t *bis)
 {
 	const char *devname;
 	unsigned short mode;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
-	/* Enable on-chip EMAC clock. */
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
 	/* Need to reset PHY via power management. */
 	ethernut5_phy_reset();
 	/* Set peripheral pins. */
@@ -211,10 +208,8 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 int board_mmc_init(bd_t *bd)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_MCI);
 
-	/* Enable MCI clock. */
-	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
 	/* Initialize MCI hardware. */
 	at91_mci_hw_init();
 	/* Register the device. */
@@ -229,6 +224,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 #ifdef CONFIG_ATMEL_SPI
 /*
+
  * Note, that u-boot uses different code for SPI bus access. While
  * memory routines use automatic chip select control, the serial
  * flash support requires 'manual' GPIO control. Thus, we switch

board/esd/meesc/meesc.c

@@ -87,9 +87,8 @@ static void meesc_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void meesc_macb_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	/* Enable clock */
+
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 	at91_macb_hw_init();
 }
 #endif
@@ -244,12 +243,10 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* enable all clocks */
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+	at91_periph_clk_enable(ATMEL_ID_UHP);
-		(1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
-		&pmc->pcer);
 
 	at91_seriald_hw_init();
 

board/l+g/vinco/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_VINCO
+
+config SYS_BOARD
+	default "vinco"
+
+config SYS_VENDOR
+	default "l+g"
+
+config SYS_CONFIG_NAME
+	default "vinco"
+
+endif

board/l+g/vinco/MAINTAINERS

@@ -0,0 +1,6 @@
+VInCo Platform
+M:	Gregory CLEMENT <gregory.clement@free-electrons.com>
+S:	Maintained
+F:	board/l+g/vinco
+F:	include/configs/vinco.h
+F:	configs/vinco_defconfig

board/l+g/vinco/Makefile

@@ -0,0 +1 @@
+obj-y += vinco.o

board/l+g/vinco/vinco.c

@@ -0,0 +1,212 @@
+/*
+ * Board file for the VInCo platform
+ * Based on the the SAMA5-EK board file
+ * Configuration settings for the VInCo platform.
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ *		      Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void vinco_spi0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+
+#ifdef CONFIG_CMD_USB
+static void vinco_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void vinco_mci0_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI0 CDA */
+	at91_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI0 DA0 */
+	at91_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI0 DA1 */
+	at91_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI0 DA2 */
+	at91_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI0 DA3 */
+	at91_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI0 DA4 */
+	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI0 DA5 */
+	at91_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI0 DA6 */
+	at91_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI0 DA7 */
+	at91_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI0 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the interanl pull
+	 * down to save the power.
+	 */
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+	at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Enable power for MCI0 interface */
+	at91_set_pio_output(AT91_PIO_PORTE, 7, 1);
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void vinco_macb0_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+
+	/* Enable Phy*/
+	at91_set_pio_output(AT91_PIO_PORTE, 8, 1);
+}
+#endif
+
+static void vinco_serial3_hw_init(void)
+{
+	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	vinco_serial3_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	vinco_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	vinco_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	vinco_macb0_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	vinco_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}

board/mini-box/picosam9g45/led.c

@@ -9,15 +9,12 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9g45.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
 

board/mini-box/picosam9g45/picosam9g45.c

@@ -17,7 +17,6 @@
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
@@ -80,15 +79,13 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 	struct atmel_mpddrc_config ddr2;
 	unsigned long csa;
 
 	ddr2_conf(&ddr2);
 
-	/* enable DDR2 clock */
+	at91_system_clk_enable(AT91_PMC_DDR);
-	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* Chip select 1 is for DDR2/SDRAM */
 	csa = readl(&mat->ebicsa);
@@ -105,9 +102,7 @@ void mem_init(void)
 #ifdef CONFIG_CMD_USB
 static void picosam9g45_usb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
-
-	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 
 	at91_set_gpio_output(AT91_PIN_PD1, 0);
 	at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -117,11 +112,9 @@ static void picosam9g45_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void picosam9g45_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -181,8 +174,6 @@ void lcd_disable(void)
 
 static void picosam9g45_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
@@ -214,7 +205,7 @@ static void picosam9g45_lcd_hw_init(void)
 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 
 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 }

board/ronetix/pm9261/led.c

@@ -9,15 +9,12 @@
 
 #include <common.h>
 #include <asm/gpio.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
 	gpio_direction_output(CONFIG_RED_LED, 1);
 	gpio_direction_output(CONFIG_GREEN_LED, 1);

board/ronetix/pm9261/pm9261.c

@@ -14,7 +14,6 @@
 #include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/clk.h>
@@ -41,7 +40,6 @@ static void pm9261_nand_hw_init(void)
 	unsigned long csa;
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
 	/* Enable CS3 */
 	csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -69,9 +67,8 @@ static void pm9261_nand_hw_init(void)
 		AT91_SMC_MODE_TDF_CYCLE(2),
 		&smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOA |
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-		1 << ATMEL_ID_PIOC,
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-		&pmc->pcer);
 
 	/* Configure RDY/BSY */
 	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
@@ -89,7 +86,6 @@ static void pm9261_nand_hw_init(void)
 static void pm9261_dm9000_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
 	/* Configure SMC CS2 for DM9000 */
 	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
@@ -110,7 +106,7 @@ static void pm9261_dm9000_hw_init(void)
 		&smc->cs[2].mode);
 
 	/* Configure Interrupt pin as input, no pull-up */
-	writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
 	at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
 }
 #endif
@@ -145,8 +141,6 @@ void lcd_disable(void)
 
 static void pm9261_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
 	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
@@ -170,7 +164,7 @@ static void pm9261_lcd_hw_init(void)
 	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
 	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */
 
-	writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
+	at91_system_clk_enable(AT91_PMC_HCK1);
 
 	gd->fb_base = ATMEL_BASE_SRAM;
 }
@@ -224,12 +218,8 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	/* Enable clocks for some PIOs */
-	writel(1 << ATMEL_ID_PIOA |
-		1 << ATMEL_ID_PIOC,
-		&pmc->pcer);
 
 	at91_seriald_hw_init();
 

board/ronetix/pm9263/led.c

@@ -9,15 +9,12 @@
 
 #include <common.h>
 #include <asm/gpio.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 
 void coloured_LED_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-
-	/* Enable clock */
-	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
 	gpio_direction_output(CONFIG_RED_LED, 1);
 	gpio_direction_output(CONFIG_GREEN_LED, 1);

board/ronetix/pm9263/pm9263.c

@@ -14,7 +14,6 @@
 #include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/clk.h>
@@ -78,8 +77,6 @@ static void pm9263_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void pm9263_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/*
 	 * PB27 enables the 50MHz oscillator for Ethernet PHY
 	 * 1 - enable
@@ -88,8 +85,7 @@ static void pm9263_macb_hw_init(void)
 	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
 	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -231,8 +227,6 @@ static int pm9263_lcd_hw_psram_init(void)
 
 static void pm9263_lcd_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
 	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
@@ -257,7 +251,7 @@ static void pm9263_lcd_hw_init(void)
 	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
 	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
 
-	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
 
 	/* Power Control */
 	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
@@ -323,12 +317,9 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOCDE),
-		&pmc->pcer);
 
 	at91_seriald_hw_init();
 

board/ronetix/pm9g45/pm9g45.c

@@ -17,7 +17,6 @@
 #include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/gpio.h>
@@ -39,7 +38,6 @@ static void pm9g45_nand_hw_init(void)
 	unsigned long csa;
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 
 	/* Enable CS3 */
 	csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
@@ -63,7 +61,7 @@ static void pm9g45_nand_hw_init(void)
 		AT91_SMC_MODE_TDF_CYCLE(3),
 		&smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 #ifdef CONFIG_SYS_NAND_READY_PIN
 	/* Configure RDY/BSY */
@@ -78,8 +76,6 @@ static void pm9g45_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void pm9g45_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/*
 	 * PD2 enables the 50MHz oscillator for Ethernet PHY
 	 * 1 - enable
@@ -88,8 +84,7 @@ static void pm9g45_macb_hw_init(void)
 	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
 	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
 
-	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
 	/*
 	 * Disable pull-up on:
@@ -114,13 +109,10 @@ static void pm9g45_macb_hw_init(void)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
-
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	/* Enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	writel((1 << ATMEL_ID_PIOA) |
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
-		(1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOC) |
-		(1 << ATMEL_ID_PIODE), &pmc->pcer);
 
 	at91_seriald_hw_init();
 

board/siemens/corvus/board.c

@@ -17,7 +17,6 @@
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -147,13 +146,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 
 void mem_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct atmel_mpddrc_config ddr2;
 
 	ddr2_conf(&ddr2);
 
-	/* enable DDR2 clock */
+	at91_system_clk_enable(AT91_PMC_DDR);
-	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
@@ -210,10 +207,9 @@ int board_early_init_f(void)
 /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */
 void at91_udp_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable UPLL clock */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	at91_upll_clk_enable();
+
 	/* Enable UDPHS clock */
 	at91_periph_clk_enable(ATMEL_ID_UDPHS);
 }

board/siemens/smartweb/smartweb.c

@@ -22,7 +22,6 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_spi.h>
 #include <spi.h>
 #include <asm/arch/clk.h>
@@ -116,17 +115,13 @@ static void smartweb_macb_hw_init(void)
 
 void at91_udp_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	/* Enable PLLB */
-	writel(get_pllb_init(), &pmc->pllbr);
+	at91_pllb_clk_enable(get_pllb_init());
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
-		;
 
 	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
 	at91_periph_clk_enable(ATMEL_ID_UDP);
 
-	writel(AT91SAM926x_PMC_UDP, &pmc->scer);
+	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
 }
 
 struct at91_udc_data board_udc_data  = {

board/siemens/taurus/taurus.c

@@ -18,7 +18,6 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9_sdramc.h>
@@ -290,17 +289,13 @@ void spi_cs_deactivate(struct spi_slave *slave)
 
 void at91_udp_hw_init(void)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
 	/* Enable PLLB */
-	writel(get_pllb_init(), &pmc->pllbr);
+	at91_pllb_clk_enable(get_pllb_init());
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
-		;
 
 	/* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
 	at91_periph_clk_enable(ATMEL_ID_UDP);
 
-	writel(AT91SAM926x_PMC_UDP, &pmc->scer);
+	at91_system_clk_enable(AT91SAM926x_PMC_UDP);
 }
 
 struct at91_udc_data board_udc_data  = {

configs/ma5d4evk_defconfig

@@ -0,0 +1,11 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_MA5D4EVK=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y

configs/smartweb_defconfig

@@ -3,4 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SMARTWEB=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
-CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"

configs/vinco_defconfig

@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_VINCO=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_SYS_PROMPT="vinco => "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_ETH_DESIGNWARE=y

drivers/net/at91_emac.c

@@ -12,7 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_emac.h>
-#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/at91_pio.h>
 #include <net.h>
 #include <netdev.h>
@@ -321,7 +321,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
 	emac_device *dev;
 	at91_emac_t *emac;
 	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	emac = (at91_emac_t *) netdev->iobase;
 	dev = (emac_device *) netdev->priv;
@@ -347,7 +346,8 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
 	writel(value, &pio->piob.pdr);
 	writel(value, &pio->piob.bsr);
 
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
 	writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
 
 	/* Init Ethernet buffers */
@@ -452,10 +452,10 @@ static int at91emac_recv(struct eth_device *netdev)
 static int at91emac_write_hwaddr(struct eth_device *netdev)
 {
 	at91_emac_t *emac;
-	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
 	emac = (at91_emac_t *) netdev->iobase;
 
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
+
 	debug_cond(DEBUG_AT91EMAC,
 		"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
 		netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],

drivers/usb/host/ehci-atmel.c

@@ -7,44 +7,21 @@
  */
 
 #include <common.h>
-#include <watchdog.h>
 #include <usb.h>
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 
 #include "ehci.h"
 
-/* Enable UTMI PLL time out 500us
- * 10 times as datasheet specified
- */
-#define EN_UPLL_TIMEOUT	500UL
-
 int ehci_hcd_init(int index, enum usb_init_type init,
 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-	ulong start_time, tmp_time;
-
-	start_time = get_timer(0);
 	/* Enable UTMI PLL */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+	if (at91_upll_clk_enable())
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
-		WATCHDOG_RESET();
-		tmp_time = get_timer(0);
-		if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
-			printf("ERROR: failed to enable UPLL\n");
 		return -1;
-		}
-	}
 
 	/* Enable USB Host clock */
-#ifdef CPU_HAS_PCR
 	at91_periph_clk_enable(ATMEL_ID_UHPHS);
-#else
-	writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
-#endif
 
 	*hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
 	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
@@ -55,27 +32,12 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 int ehci_hcd_stop(int index)
 {
-	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-	ulong start_time, tmp_time;
-
 	/* Disable USB Host Clock */
-#ifdef CPU_HAS_PCR
 	at91_periph_clk_disable(ATMEL_ID_UHPHS);
-#else
-	writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr);
-#endif
 
-	start_time = get_timer(0);
 	/* Disable UTMI PLL */
-	writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
+	if (at91_upll_clk_disable())
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
-		WATCHDOG_RESET();
-		tmp_time = get_timer(0);
-		if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
-			printf("ERROR: failed to stop UPLL\n");
 		return -1;
-		}
-	}
 
 	return 0;
 }

drivers/usb/host/ohci-at91.c

@@ -9,45 +9,29 @@
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 
 int usb_cpu_init(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
 #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
-	/* Enable PLLB */
+	if (at91_pllb_clk_enable(get_pllb_init()))
-	writel(get_pllb_init(), &pmc->pllbr);
+		return -1;
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
+
-		;
 #ifdef CONFIG_AT91SAM9N12
-	writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb);
+	at91_usb_clk_init(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2);
 #endif
 #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
-	/* Enable UPLL */
+	if (at91_upll_clk_enable())
-	writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN,
+		return -1;
-		&pmc->uckr);
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU)
-		;
 
-	/* Select PLLA as input clock of OHCI */
+	at91_usb_clk_init(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10);
-	writel(AT91_PMC_USBS_USB_UPLL | AT91_PMC_USBDIV_10, &pmc->usb);
 #endif
 
-	/* Enable USB host clock. */
-#ifdef CPU_HAS_PCR
 	at91_periph_clk_enable(ATMEL_ID_UHP);
-#else
-	writel(1 << ATMEL_ID_UHP, &pmc->pcer);
-#endif
 
+	at91_system_clk_enable(ATMEL_PMC_UHP);
 #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
-	writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer);
+	at91_system_clk_enable(AT91_PMC_HCK0);
-#else
-	writel(ATMEL_PMC_UHP, &pmc->scer);
 #endif
 
 	return 0;
@@ -55,34 +39,24 @@ int usb_cpu_init(void)
 
 int usb_cpu_stop(void)
 {
-	at91_pmc_t *pmc	= (at91_pmc_t *)ATMEL_BASE_PMC;
-
-	/* Disable USB host clock. */
-#ifdef CPU_HAS_PCR
 	at91_periph_clk_disable(ATMEL_ID_UHP);
-#else
-	writel(1 << ATMEL_ID_UHP, &pmc->pcdr);
-#endif
 
+	at91_system_clk_disable(ATMEL_PMC_UHP);
 #if defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10)
-	writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr);
+	at91_system_clk_disable(AT91_PMC_HCK0);
-#else
-	writel(ATMEL_PMC_UHP, &pmc->scdr);
 #endif
 
 #ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB
 #ifdef CONFIG_AT91SAM9N12
-	writel(0, &pmc->usb);
+	at91_usb_clk_init(0);
 #endif
-	/* Disable PLLB */
+
-	writel(0, &pmc->pllbr);
+	if (at91_pllb_clk_disable())
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0)
+		return -1;
-		;
+
 #elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL)
-	/* Disable UPLL */
+	if (at91_upll_clk_disable())
-	writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr);
+		return -1;
-	while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU)
-		;
 #endif
 
 	return 0;

include/configs/ma5d4evk.h

@@ -0,0 +1,255 @@
+/*
+ * DENX MA5D4 configuration
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MA5D4EVK_CONFIG_H__
+#define __MA5D4EVK_CONFIG_H__
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_FIT
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#include "at91-sama5_common.h"
+#undef CONFIG_BOOTARGS
+#define CONFIG_SYS_USE_SERIALFLASH	1
+
+/*
+ * U-Boot Commands
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+/*#define CONFIG_LCD*/
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_USB
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET		0x8000
+#define CONFIG_ENV_SIZE			0x4000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		0x1000
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_USART0
+#define CONFIG_USART_ID			ATMEL_ID_USART0
+
+/*
+ * Ethernet
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_IP_DEFRAG
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP                  24
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/*
+ * SPI NOR (boot memory)
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_ATMEL_SPI0
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_STORAGE
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "DENX"
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"fitImage"
+#define CONFIG_BOOTARGS		"console=ttyS3,115200"
+#define CONFIG_LOADADDR		0x20800000
+#define CONFIG_BOOTCOMMAND	"run mmc_mmc"
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_PREBOOT		"run try_bootscript"
+#define CONFIG_HOSTNAME		ma5d4evk
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"consdev=ttyS3\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"bootdev=/dev/mmcblk1p1\0"					\
+	"bootpart=1:1\0"						\
+	"rootdev=/dev/mmcblk1p2\0"					\
+	"netdev=eth0\0"							\
+	"kernel_addr_r=0x22000000\0"					\
+	"update_spi_firmware_spl_addr=0x21000000\0"			\
+	"update_spi_firmware_spl_filename=boot.bin\0"			\
+	"update_spi_firmware_addr=0x22000000\0"				\
+	"update_spi_firmware_filename=u-boot.img\0"			\
+	"update_spi_firmware="	/* Update the SPI flash firmware */	\
+		"if sf probe ; then "					\
+		"if tftp ${update_spi_firmware_spl_addr} "		\
+			"${update_spi_firmware_spl_filename} ; then "	\
+		"setenv update_spi_firmware_spl_filesize ${filesize} ; "\
+		"if tftp ${update_spi_firmware_addr} "			\
+			"${update_spi_firmware_filename} ; then "	\
+		"setenv update_spi_firmware_filesize ${filesize} ; "	\
+		"sf update ${update_spi_firmware_spl_addr} 0x0 "	\
+			"${update_spi_firmware_spl_filesize} ; "	\
+		"sf update ${update_spi_firmware_addr} 0x10000 "	\
+			"${update_spi_firmware_filesize} ; "		\
+		"fi ; "							\
+		"fi ; "							\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc\0"					\
+	"mmcload="							\
+		"mmc rescan ; "						\
+		"load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0"	\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0"		\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"mmc_mmc="							\
+		"run mmcload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"mmc_nfs="							\
+		"run mmcload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_mmc="							\
+		"run netload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"try_bootscript="						\
+		"mmc rescan;"						\
+		"if test -e mmc ${bootpart} ${bootscript} ; then "	\
+		"if load mmc ${bootpart} ${kernel_addr_r} ${bootscript};"\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
+		"fi\0"
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x200000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x10000
+
+#endif	/* __MA5D4EVK_CONFIG_H__ */

include/configs/smartweb.h

@@ -49,10 +49,18 @@
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f() */
 #define CONFIG_DISPLAY_CPUINFO		/* display CPU Info at startup */
 
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS    32
+
 /* setting board specific options */
 #define CONFIG_MACH_TYPE		MACH_TYPE_SMARTWEB
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
+#define CONFIG_ENV_OVERWRITE    1 /* Overwrite ethaddr / serial# */
+#define CONFIG_SYS_HUSH_PARSER    /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2  "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_AUTOLOAD "yes"
+#define CONFIG_RESET_TO_RETRY
 
 /* The LED PINs */
 #define CONFIG_RED_LED			AT91_PIN_PA9
@@ -184,9 +192,7 @@
 /* General Boot Parameter */
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTCOMMAND		"run flashboot"
-#define CONFIG_BOOT_RETRY_TIME          30
 #define CONFIG_SYS_CBSIZE		512
-#define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_PBSIZE \
 	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_LONGHELP

include/configs/vinco.h

@@ -0,0 +1,167 @@
+/*
+ * Configuration settings for the VInCo platform.
+ *
+ * Based on the settings for the SAMA5-EK board
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ *		      Gregory CLEMENT gregory.clement@free-electrons.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should be put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* The value in the common file is too far away for the VInCo platform */
+#ifdef CONFIG_SYS_TEXT_BASE
+#undef CONFIG_SYS_TEXT_BASE
+#endif
+#define CONFIG_SYS_TEXT_BASE		0x20f00000
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_USART3
+#define	CONFIG_USART_ID			ATMEL_ID_USART3
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x4000000
+
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* SerialFlash */
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_ATMEL_SPI0
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define CONFIG_ENV_SPI_MAX_HZ		50000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+#define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
+#endif
+
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define ATMEL_BASE_MMCI			ATMEL_BASE_MCI1
+#define CONFIG_SYS_MMC_CLK_OD		500000
+
+/* For generating MMC partitions */
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_RANDOM_UUID
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_GPT
+
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "L+G VInCo"
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_SMSC
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_RNDIS
+
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+/* bootstrap + u-boot + env + linux in serial flash */
+#define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
+/* Use our own mapping for the VInCo platform */
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_OFFSET       0x10000
+#define CONFIG_ENV_SIZE         0x10000
+
+/* Update the bootcommand according to our mapping for the VInCo platform */
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND  "mmc dev 0 0;" \
+			    "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \
+			    "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \
+			    "bootz ${loadaddr} -  ${oftaddr}"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS	    "console=ttyS0,115200 earlyprintk rw root=/dev/mmcblk0p2 rootfstype=ext4 rootwait quiet lpj=1990656"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_start=0x20000\0" \
+	"kernel_size=0x800000\0" \
+	"mmcblksize=0x200\0" \
+	"oftaddr=0x21000000\0" \
+	"loadaddr=0x22000000\0" \
+	"update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \
+	"sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \
+	"create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \
+	"setexpr rootfs_start ${kernel_start} + ${kernel_size};" \
+	"setenv partitions 'name=kernel,size=${kernel_size}," \
+	"start=${kernel_start};name=rootfs,size=-';" \
+	"gpt write mmc 0 ${partitions} \0"\
+	"f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \
+	"setexpr fileblksize ${fileblksize} + 1\0" \
+	"store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \
+	"setexpr k_blksize ${fileblksize};" \
+	"setexpr k_offset ${kernel_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \
+	"store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \
+	"setexpr dtb_blksize ${fileblksize};" \
+	"setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \
+	"store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \
+	"setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \
+	"bootdelay=0\0"
+
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#endif