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fsl-layerscape: Add fsl_esdhc peripheral clock support 

Add esdhc peripheral clock support
for NXP layerscape platforms: LS1046ARDB, LS1043ARDB,
LS1012ARDB, LS1028ARDB, LS1088ARDB, LX2160ARDB

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Yinbo Zhu 2019-07-16 15:09:06 +08:00 committed by Priyanka Jain
parent 001c8ea94a
commit 24cb6f2295
4 changed files with 78 additions and 19 deletions
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49
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) void get_sys_info(struct sys_info *sys_info)
{ {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#if (defined(CONFIG_FSL_ESDHC) &&\ /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ * mux 2 clock for LS1043A/LS1046A.
defined(CONFIG_SYS_DPAA_FMAN) */
#if defined(CONFIG_SYS_DPAA_FMAN) || \
defined(CONFIG_TARGET_LS1046ARDB) || \
defined(CONFIG_TARGET_LS1043ARDB)
u32 rcw_tmp; u32 rcw_tmp;
#endif #endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info)
} }
#endif #endif
#ifdef CONFIG_FSL_ESDHC
#define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0 #define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]); rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1: case 1:
sys_info->freq_sdhc = freq_c_pll[1]; sys_info->freq_cga_m2 = freq_c_pll[1];
break; break;
#if defined(CONFIG_TARGET_LS1046ARDB)
case 2: case 2:
sys_info->freq_sdhc = freq_c_pll[1] / 2; sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break; break;
#endif
case 3: case 3:
sys_info->freq_sdhc = freq_c_pll[1] / 3; sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break; break;
#if defined(CONFIG_TARGET_LS1046ARDB)
case 6: case 6:
sys_info->freq_sdhc = freq_c_pll[0] / 2; sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break; break;
#endif
default: default:
printf("Error: Unknown ESDHC clock select!\n"); printf("Error: Unknown peripheral clock select!\n");
break; break;
} }
#else
sys_info->freq_sdhc = (sys_info->freq_systembus /
CONFIG_SYS_FSL_PCLK_DIV) /
CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif #endif
#endif #endif
@ -183,9 +185,22 @@ int get_clocks(void)
gd->mem_clk = sys_info.freq_ddrbus; gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC
gd->arch.sdhc_clk = sys_info.freq_sdhc; #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
#if defined(CONFIG_TARGET_LS1046ARDB)
gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
#endif
#if defined(CONFIG_TARGET_LS1043ARDB)
gd->arch.sdhc_clk = sys_info.freq_cga_m2;
#endif
#if defined(CONFIG_TARGET_LS1012ARDB)
gd->arch.sdhc_clk = sys_info.freq_systembus;
#endif
#else
gd->arch.sdhc_clk = (sys_info.freq_systembus /
CONFIG_SYS_FSL_PCLK_DIV) /
CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
#endif #endif
if (gd->cpu_clk != 0) if (gd->cpu_clk != 0)
return 0; return 0;
else else

45
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -64,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info)
}; };
uint i, cluster; uint i, cluster;
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
uint rcw_tmp;
#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ; unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
@ -127,8 +130,39 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_localbus = sys_info->freq_systembus / sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV; CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif #endif
}
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
#define HWA_CGA_M2_CLK_SEL 0x00380000
#define HWA_CGA_M2_CLK_SHIFT 19
rcw_tmp = in_le32(&gur->rcwsr[5]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
sys_info->freq_cga_m2 = freq_c_pll[1];
break;
case 2:
sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break;
case 3:
sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break;
case 4:
sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
break;
case 6:
sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break;
case 7:
sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
break;
default:
printf("Error: Unknown peripheral clock select!\n");
break;
}
#endif
#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
sys_info->freq_cga_m2 = sys_info->freq_systembus;
#endif
}
int get_clocks(void) int get_clocks(void)
{ {
@ -141,7 +175,16 @@ int get_clocks(void)
gd->arch.mem2_clk = sys_info.freq_ddrbus2; gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif #endif
#if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
#endif
#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
gd->arch.sdhc_clk = sys_info.freq_cga_m2;
#endif
#else
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */ #endif /* defined(CONFIG_FSL_ESDHC) */
if (gd->cpu_clk != 0) if (gd->cpu_clk != 0)

2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -180,7 +180,7 @@ struct sys_info {
unsigned long freq_systembus; unsigned long freq_systembus;
unsigned long freq_ddrbus; unsigned long freq_ddrbus;
unsigned long freq_localbus; unsigned long freq_localbus;
unsigned long freq_sdhc; unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
#endif #endif

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -278,6 +278,7 @@ struct sys_info {
/* frequency of platform PLL */ /* frequency of platform PLL */
unsigned long freq_systembus; unsigned long freq_systembus;
unsigned long freq_ddrbus; unsigned long freq_ddrbus;
unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2; unsigned long freq_ddrbus2;
#endif #endif