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arm, arm926ejs: Do cpu critical inits only for boards that require it 

This patch reverts commit ca4b55800e
"arm, arm926ejs: always do cpu critical inits" since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.

Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board configurations that need low level initialization.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Christian Riesch 2012-02-02 00:44:37 +00:00 committed by Albert ARIBAUD
parent eb93524224
commit 27b66622b5
4 changed files with 4 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/cpu/arm926ejs/start.S
View File

@ -194,7 +194,9 @@ reset:
* we do sys-critical inits only at reboot, * we do sys-critical inits only at reboot,
* not when booting from ram! * not when booting from ram!
*/ */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit bl cpu_init_crit
#endif
/* Set stackpointer in internal RAM to call board_init_f */ /* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f: call_board_init_f:
@ -353,6 +355,7 @@ _dynsym_start_ofs:
* *
************************************************************************* *************************************************************************
*/ */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit: cpu_init_crit:
/* /*
* flush v4 I/D caches * flush v4 I/D caches
@ -371,15 +374,14 @@ cpu_init_crit:
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* /*
* Go setup Memory and board specific bits prior to relocation. * Go setup Memory and board specific bits prior to relocation.
*/ */
mov ip, lr /* perserve link reg across call */ mov ip, lr /* perserve link reg across call */
bl lowlevel_init /* go setup pll,mux,memory */ bl lowlevel_init /* go setup pll,mux,memory */
mov lr, ip /* restore link */ mov lr, ip /* restore link */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
mov pc, lr /* back to my caller */ mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
/* /*

6
include/configs/cam_enc_4xx.h
View File

@ -275,12 +275,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
/*
* U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
* done in board_init_f from c code.
*/
#define CONFIG_SKIP_LOWLEVEL_INIT
/* for UBL header */ /* for UBL header */
#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)

1
include/configs/da850evm.h
View File

@ -42,7 +42,6 @@
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000 #define CONFIG_SYS_TEXT_BASE 0xc1080000
/* /*

1
include/configs/enbw_cmc.h
View File

@ -45,7 +45,6 @@
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ 1000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_DA850_LOWLEVEL #define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO #define CONFIG_DA8XX_GPIO