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x86: Add an option to control the position of SPL 

For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).

Add a Kconfig option for the ROM position.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-12-06 21:42:30 -07:00 committed by Bin Meng
parent b31129528e
commit 28d7d76a86
2 changed files with 7 additions and 2 deletions
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5
arch/x86/Kconfig
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@ -904,4 +904,9 @@ config X86_OFFSET_U_BOOT
depends on HAVE_SYS_TEXT_BASE depends on HAVE_SYS_TEXT_BASE
default SYS_TEXT_BASE default SYS_TEXT_BASE
config X86_OFFSET_SPL
hex "Offset of SPL in ROM image"
depends on SPL && X86
default SPL_TEXT_BASE
endmenu endmenu

4
arch/x86/dts/u-boot.dtsi
View File

@ -45,7 +45,7 @@
}; };
#endif #endif
u-boot-spl { u-boot-spl {
offset = <CONFIG_SPL_TEXT_BASE>; offset = <CONFIG_X86_OFFSET_SPL>;
}; };
u-boot-spl-dtb { u-boot-spl-dtb {
}; };
@ -54,7 +54,7 @@
}; };
#elif defined(CONFIG_SPL) #elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr { u-boot-spl-with-ucode-ptr {
offset = <CONFIG_SPL_TEXT_BASE>; offset = <CONFIG_X86_OFFSET_SPL>;
}; };
u-boot-dtb-with-ucode2 { u-boot-dtb-with-ucode2 {
type = "u-boot-dtb-with-ucode"; type = "u-boot-dtb-with-ucode";