LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: align mtvec on a 4-byte boundary 

The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Lukas Auer 2018-11-22 11:26:25 +01:00 committed by Andes
parent c55309c091
commit 2a23ac6107
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/riscv/cpu/start.S
View File

@ -42,7 +42,6 @@ nmi_vector:
trap_vector: trap_vector:
j trap_entry j trap_entry
.global trap_entry
handle_reset: handle_reset:
li t0, CONFIG_SYS_SDRAM_BASE li t0, CONFIG_SYS_SDRAM_BASE
SREG a2, 0(t0) SREG a2, 0(t0)
@ -208,6 +207,7 @@ call_board_init_r:
/* /*
* trap entry * trap entry
*/ */
.align 2
trap_entry: trap_entry:
addi sp, sp, -32*REGBYTES addi sp, sp, -32*REGBYTES
SREG x1, 1*REGBYTES(sp) SREG x1, 1*REGBYTES(sp)