arm: mvebu: Initial iEi Puzzle-M801 support
Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC. Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Luka Kovacic
Stefan Roese
parent
4684a7a43a
commit
2ae2b8a2f2
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@ -218,6 +218,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-8040-clearfog-gt-8k.dtb \
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armada-8040-db.dtb \
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armada-8040-mcbin.dtb \
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armada-8040-puzzle-m801.dtb \
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armada-xp-crs305-1g-4s.dtb \
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armada-xp-crs305-1g-4s-bit.dtb \
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armada-xp-crs326-24g-2s.dtb \
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@ -0,0 +1,389 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Marvell International Ltd.
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* Copyright (C) 2020 Sartura Ltd.
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*/
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#include "armada-8040.dtsi" /* include SoC device tree */
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/ {
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model = "iEi-Puzzle-M801";
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compatible = "marvell,armada8040-puzzle-m801",
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"marvell,armada8040";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &i2c0;
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i2c1 = &cpm_i2c0;
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i2c2 = &cpm_i2c1;
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i2c3 = &i2c_switch;
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spi0 = &spi0;
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gpio0 = &ap_gpio0;
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gpio1 = &cpm_gpio0;
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gpio2 = &cpm_gpio1;
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gpio3 = &sfpplus_gpio;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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simple-bus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb3h0_vbus: usb3-vbus0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_xhci_vbus_pins>;
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regulator-name = "reg-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <500000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
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};
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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rtc@32 {
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compatible = "epson,rx8010";
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reg = <0x32>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&ap_pinctl {
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/*
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* MPP Bus:
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* AP SPI0 [0-3]
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* AP I2C [4-5]
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* AP GPIO [6]
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* AP UART 1 RX/TX [7-8]
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* AP GPIO [9-10]
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* AP GPIO [12]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 3 3 3 3 3 3 3 3 3 0
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0 3 0 0 0 0 0 0 0 3 >;
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};
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&cpm_pinctl {
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/*
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* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] SMI
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* [33] MSS power down
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* [35-38] CP0 I2C1 and I2C0
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* [39] MSS CKE Enable
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* [40,41] CP0 UART1 TX/RX
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* [42,43] XSMI (controls two 10G phys)
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* [47] USB VBUS EN
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* [48] FAN PWM
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* [49] 10G port 1 interrupt
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* [50] 10G port 0 interrupt
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* [51] 2.5G SFP TX fault
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* [52] PCIe reset out
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* [53] 2.5G SFP mode
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* [54] 2.5G SFP LOS
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* [55] Micro SD card detect
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* [56-61] Micro SD
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* [62] CP1 SFI SFP FAULT
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0 7 0xa 7 2 2 2 2 0xa
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7 7 8 8 0 0 0 0 0 0
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0 0 0 0 0 0 0xe 0xe 0xe 0xe
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0xe 0xe 0 >;
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cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
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marvell,pins = < 47 >;
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marvell,function = <0>;
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};
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cpm_pcie_reset_pins: cpm-pcie-reset-pins {
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marvell,pins = < 52 >;
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marvell,function = <0>;
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};
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};
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&cpm_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_sdhci_pins>;
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bus-width= <4>;
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status = "okay";
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};
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&cpm_pcie0 {
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num-lanes = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_pcie_reset_pins>;
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marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
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status = "okay";
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};
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&cpm_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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sfpplus_gpio: gpio@21 {
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compatible = "nxp,pca9555";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&cpm_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cpm_i2c1_pins>;
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status = "okay";
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clock-frequency = <100000>;
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i2c_switch: i2c-switch@70 {
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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};
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};
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&cpm_sata0 {
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status = "okay";
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};
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&cpm_ethernet {
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pinctrl-names = "default";
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status = "okay";
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};
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&cpm_mdio {
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status = "okay";
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cpm_ge_phy0: ethernet-phy@1 {
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reg = <0>;
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};
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cpm_ge_phy1: ethernet-phy@2 {
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reg = <1>;
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};
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};
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&cpm_eth0 {
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status = "okay";
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phy-mode = "sfi";
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};
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&cpm_eth1 {
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status = "okay";
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phy-mode = "sgmii";
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phy = <&cpm_ge_phy0>;
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};
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&cpm_eth2 {
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status = "okay";
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phy-mode = "sgmii";
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phy = <&cpm_ge_phy1>;
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};
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&cpm_comphy {
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/*
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* CP0 Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: SGMII2
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* Lane 2: SATA0
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* Lane 3: SGMII1
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* Lane 4: SFI (10G)
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* Lane 5: SATA1
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*/
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phy0 {
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phy-type = <PHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <PHY_TYPE_SGMII2>;
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phy-speed = <PHY_SPEED_1_25G>;
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};
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phy2 {
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phy-type = <PHY_TYPE_SATA0>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SGMII1>;
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phy-speed = <PHY_SPEED_1_25G>;
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};
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phy4 {
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phy-type = <PHY_TYPE_SFI>;
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};
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phy5 {
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phy-type = <PHY_TYPE_SATA1>;
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};
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};
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&cps_mdio {
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status = "okay";
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cps_ge_phy0: ethernet-phy@3 {
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reg = <1>;
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};
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cps_ge_phy1: ethernet-phy@4 {
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reg = <0>;
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};
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};
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&cps_pcie0 {
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num-lanes = <2>;
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pinctrl-names = "default";
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status = "okay";
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};
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&cps_usb3_0 {
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vbus-supply = <®_usb3h0_vbus>;
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status = "okay";
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};
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&cps_utmi0 {
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status = "okay";
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};
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&cps_ethernet {
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status = "okay";
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};
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&cps_eth0 {
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status = "okay";
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phy-mode = "sfi";
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};
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&cps_eth1 {
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status = "okay";
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phy = <&cps_ge_phy0>;
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phy-mode = "sgmii";
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};
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&cps_eth2 {
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status = "okay";
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phy = <&cps_ge_phy1>;
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phy-mode = "sgmii";
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};
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&cps_pinctl {
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/*
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* MPP Bus:
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* [0-5] TDM
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* [6,7] CP1_UART 0
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* [8] CP1 10G SFP LOS
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* [9] CP1 10G PHY RESET
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* [10] CP1 10G SFP TX Disable
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* [11] CP1 10G SFP Mode
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* [12] SPI1 CS1n
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* [13] SPI1 MISO (TDM and SPI ROM shared)
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* [14] SPI1 CS0n
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* [15] SPI1 MOSI (TDM and SPI ROM shared)
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* [16] SPI1 CLK (TDM and SPI ROM shared)
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* [24] CP1 2.5G SFP TX Disable
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* [26] CP0 10G SFP TX Fault
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* [27] CP0 10G SFP Mode
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* [28] CP0 10G SFP LOS
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* [29] CP0 10G SFP TX Disable
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* [30] USB Over current indication
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* [31] 10G Port 0 phy reset
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0
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0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0
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0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff>;
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@u-boot {
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reg = <0x00000000 0x001f0000>;
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label = "u-boot";
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};
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partition@u-boot-env {
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reg = <0x001f0000 0x00010000>;
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label = "u-boot-env";
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};
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partition@ubi1 {
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reg = <0x00200000 0x03f00000>;
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label = "ubi1";
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};
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partition@ubi2 {
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reg = <0x04100000 0x03f00000>;
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label = "ubi2";
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};
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};
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};
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};
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&cps_comphy {
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/*
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* CP1 Serdes Configuration:
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* Lane 0: PCIe0 (x2)
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* Lane 1: PCIe0 (x2)
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* Lane 2: USB HOST 0
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* Lane 3: SGMII1
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* Lane 4: SFI (10G)
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* Lane 5: SGMII2
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*/
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phy0 {
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phy-type = <PHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <PHY_TYPE_PEX0>;
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};
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phy2 {
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phy-type = <PHY_TYPE_USB3_HOST0>;
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};
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phy3 {
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phy-type = <PHY_TYPE_SGMII1>;
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phy-speed = <PHY_SPEED_1_25G>;
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};
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phy4 {
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phy-type = <PHY_TYPE_SFI>;
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};
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phy5 {
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phy-type = <PHY_TYPE_SGMII2>;
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phy-speed = <PHY_SPEED_1_25G>;
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};
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};
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@ -10,3 +10,9 @@ MACCHIATOBin BOARD
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M: Konstantin Porotchkin <kostap@marvell.com>
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S: Maintained
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F: configs/mvebu_mcbin-88f8040_defconfig
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Puzzle-M801 BOARD
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M: Luka Kovacic <luka.kovacic@sartura.hr>
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S: Maintained
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F: configs/mvebu_puzzle-m801-88f8040_defconfig
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F: arch/arm/dts/armada-8040-puzzle-m801.dts
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@ -0,0 +1,91 @@
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CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_SYS_TEXT_BASE=0x00000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_TARGET_MVEBU_ARMADA_8K=y
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CONFIG_ENV_SIZE=0x10000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_ENV_OFFSET=0x1F0000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_DEBUG_UART_BASE=0xf0512000
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CONFIG_DEBUG_UART_CLOCK=200000000
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CONFIG_DEBUG_UART=y
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CONFIG_AHCI=y
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_USE_PREBOOT=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds, to stop use 's' key\n"
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CONFIG_AUTOBOOT_STOP_STR="s"
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CONFIG_AUTOBOOT_KEYED_CTRLC=y
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CONFIG_ARCH_EARLY_INIT_R=y
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CONFIG_BOARD_EARLY_INIT_F=y
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# CONFIG_EFI_LOADER is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_MVEBU_BUBT=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_MAC_PARTITION=y
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CONFIG_DEFAULT_DEVICE_TREE="armada-8040-puzzle-m801"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_AHCI_MVEBU=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_MVTWSI=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_RX8010SJ=y
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CONFIG_MISC=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_SDHCI=y
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||||
CONFIG_MMC_SDHCI_XENON=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
# CONFIG_SPI_FLASH_SPANSION is not set
|
||||
# CONFIG_SPI_FLASH_STMICRO is not set
|
||||
# CONFIG_SPI_FLASH_WINBOND is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MVPP2=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PCIE_DW_MVEBU=y
|
||||
CONFIG_MVEBU_COMPHY_SUPPORT=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_8K=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_HOST_ETHER is not set
|
||||
# CONFIG_USB_ETHER_ASIX is not set
|
||||
# CONFIG_USB_ETHER_MCS7830 is not set
|
||||
# CONFIG_USB_ETHER_RTL8152 is not set
|
||||
# CONFIG_USB_ETHER_SMSC95XX is not set
|
||||
Loading…
Reference in New Issue