LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Convert CONFIG_ESBC_HDR_LS et al to Kconfig 

This converts the following to Kconfig:
   CONFIG_ESBC_HDR_LS
   CONFIG_ESBC_ADDR_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-16 14:04:37 -04:00
parent d622b08923
commit 2b2817b5c8
4 changed files with 14 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/Kconfig.nxp
View File

@ -24,6 +24,15 @@ config CMD_ESBC_VALIDATE
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
config ESBC_HDR_LS
bool
config ESBC_ADDR_64BIT
def_bool y
depends on ESBC_HDR_LS && FSL_LAYERSCAPE
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A

5
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -26,6 +26,7 @@ config ARCH_LS1012A
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
@ -138,6 +139,7 @@ config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select ESBC_HDR_LS
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
@ -187,6 +189,7 @@ config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
select ESBC_HDR_LS
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
@ -239,6 +242,7 @@ config ARCH_LS2080A
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
@ -277,6 +281,7 @@ config ARCH_LX2162A
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE

12
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -63,9 +63,6 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
/* Secure Boot */
#define CONFIG_ESBC_HDR_LS
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
@ -168,9 +165,6 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
/* Secure Boot */
#define CONFIG_ESBC_HDR_LS
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
@ -223,9 +217,6 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
/* Secure Boot */
#define CONFIG_ESBC_HDR_LS
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE
@ -285,9 +276,6 @@
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
/* Secure Boot */
#define CONFIG_ESBC_HDR_LS
/* DCFG - GUR */
#define CONFIG_SYS_FSL_CCSR_GUR_LE

8
arch/arm/include/asm/fsl_secure_boot.h
View File

@ -25,14 +25,6 @@
#define CONFIG_KEY_REVOCATION
#if defined(CONFIG_FSL_LAYERSCAPE)
/*
* For fsl layerscape based platforms, ESBC image Address in Header
* is 64 bit.
*/
#define CONFIG_ESBC_ADDR_64BIT
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images