net: Remove ftmac110 driver
This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
acae10dc3e
commit
2e808fadf6
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@ -43,7 +43,6 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
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obj-$(CONFIG_FSL_PFE) += pfe_eth/
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obj-$(CONFIG_FTGMAC100) += ftgmac100.o
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obj-$(CONFIG_FTMAC100) += ftmac100.o
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obj-$(CONFIG_FTMAC110) += ftmac110.o
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obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
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obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
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obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
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@ -1,491 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Faraday 10/100Mbps Ethernet Controller
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*
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* (C) Copyright 2013 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <log.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/cache.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <linux/dma-mapping.h>
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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#endif
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#include "ftmac110.h"
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#define CFG_RXDES_NUM 8
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#define CFG_TXDES_NUM 2
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#define CFG_XBUF_SIZE 1536
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#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
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#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
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#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
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/*
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* FTMAC110 DMA design issue
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*
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* Its DMA engine has a weird restriction that its Rx DMA engine
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* accepts only 16-bits aligned address, 32-bits aligned is not
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* acceptable. However this restriction does not apply to Tx DMA.
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*
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* Conclusion:
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* (1) Tx DMA Buffer Address:
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* 1 bytes aligned: Invalid
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* 2 bytes aligned: O.K
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* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
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* (2) Rx DMA Buffer Address:
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* 1 bytes aligned: Invalid
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* 2 bytes aligned: O.K
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* 4 bytes aligned: Invalid
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*/
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struct ftmac110_chip {
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void __iomem *regs;
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uint32_t imr;
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uint32_t maccr;
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uint32_t lnkup;
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uint32_t phy_addr;
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struct ftmac110_desc *rxd;
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ulong rxd_dma;
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uint32_t rxd_idx;
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struct ftmac110_desc *txd;
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ulong txd_dma;
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uint32_t txd_idx;
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};
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static int ftmac110_reset(struct eth_device *dev);
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static uint16_t mdio_read(struct eth_device *dev,
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uint8_t phyaddr, uint8_t phyreg)
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{
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_regs *regs = chip->regs;
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uint32_t tmp, ts;
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uint16_t ret = 0xffff;
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tmp = PHYCR_READ
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| (phyaddr << PHYCR_ADDR_SHIFT)
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| (phyreg << PHYCR_REG_SHIFT);
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writel(tmp, ®s->phycr);
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for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
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tmp = readl(®s->phycr);
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if (tmp & PHYCR_READ)
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continue;
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break;
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}
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if (tmp & PHYCR_READ)
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printf("ftmac110: mdio read timeout\n");
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else
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ret = (uint16_t)(tmp & 0xffff);
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return ret;
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}
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static void mdio_write(struct eth_device *dev,
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uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
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{
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_regs *regs = chip->regs;
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uint32_t tmp, ts;
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tmp = PHYCR_WRITE
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| (phyaddr << PHYCR_ADDR_SHIFT)
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| (phyreg << PHYCR_REG_SHIFT);
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writel(phydata, ®s->phydr);
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writel(tmp, ®s->phycr);
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for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
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if (readl(®s->phycr) & PHYCR_WRITE)
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continue;
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break;
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}
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if (readl(®s->phycr) & PHYCR_WRITE)
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printf("ftmac110: mdio write timeout\n");
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}
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static uint32_t ftmac110_phyqry(struct eth_device *dev)
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{
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ulong ts;
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uint32_t maccr;
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uint16_t pa, tmp, bmsr, bmcr;
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struct ftmac110_chip *chip = dev->priv;
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/* Default = 100Mbps Full */
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maccr = MACCR_100M | MACCR_FD;
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/* 1. find the phy device */
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for (pa = 0; pa < 32; ++pa) {
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tmp = mdio_read(dev, pa, MII_PHYSID1);
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if (tmp == 0xFFFF || tmp == 0x0000)
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continue;
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chip->phy_addr = pa;
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break;
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}
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if (pa >= 32) {
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puts("ftmac110: phy device not found!\n");
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goto exit;
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}
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/* 2. wait until link-up & auto-negotiation complete */
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chip->lnkup = 0;
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bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
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ts = get_timer(0);
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do {
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bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
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chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
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if (!chip->lnkup)
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continue;
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if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
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break;
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} while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
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if (!chip->lnkup) {
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puts("ftmac110: link down\n");
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goto exit;
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}
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if (!(bmcr & BMCR_ANENABLE))
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puts("ftmac110: auto negotiation disabled\n");
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else if (!(bmsr & BMSR_ANEGCOMPLETE))
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puts("ftmac110: auto negotiation timeout\n");
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/* 3. derive MACCR */
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if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
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tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
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tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
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if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
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maccr = MACCR_100M | MACCR_FD;
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else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
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maccr = MACCR_100M;
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else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
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maccr = MACCR_FD;
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else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
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maccr = 0;
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} else {
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if (bmcr & BMCR_SPEED100)
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maccr = MACCR_100M;
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else
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maccr = 0;
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if (bmcr & BMCR_FULLDPLX)
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maccr |= MACCR_FD;
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}
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exit:
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printf("ftmac110: %d Mbps, %s\n",
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(maccr & MACCR_100M) ? 100 : 10,
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(maccr & MACCR_FD) ? "Full" : "half");
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return maccr;
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}
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static int ftmac110_reset(struct eth_device *dev)
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{
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uint8_t *a;
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uint32_t i, maccr;
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_regs *regs = chip->regs;
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/* 1. MAC reset */
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writel(MACCR_RESET, ®s->maccr);
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for (i = get_timer(0); get_timer(i) < 1000; ) {
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if (readl(®s->maccr) & MACCR_RESET)
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continue;
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break;
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}
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if (readl(®s->maccr) & MACCR_RESET) {
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printf("ftmac110: reset failed\n");
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return -ENXIO;
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}
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/* 1-1. Init tx ring */
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for (i = 0; i < CFG_TXDES_NUM; ++i) {
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/* owned by SW */
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chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
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}
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chip->txd_idx = 0;
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/* 1-2. Init rx ring */
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for (i = 0; i < CFG_RXDES_NUM; ++i) {
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/* owned by HW */
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chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
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chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
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}
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chip->rxd_idx = 0;
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/* 2. PHY status query */
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maccr = ftmac110_phyqry(dev);
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/* 3. Fix up the MACCR value */
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chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
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| MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
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/* 4. MAC address setup */
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a = dev->enetaddr;
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writel(a[1] | (a[0] << 8), ®s->mac[0]);
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writel(a[5] | (a[4] << 8) | (a[3] << 16)
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| (a[2] << 24), ®s->mac[1]);
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/* 5. MAC registers setup */
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writel(chip->rxd_dma, ®s->rxba);
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writel(chip->txd_dma, ®s->txba);
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/* interrupt at each tx/rx */
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writel(ITC_DEFAULT, ®s->itc);
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/* no tx pool, rx poll = 1 normal cycle */
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writel(APTC_DEFAULT, ®s->aptc);
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/* rx threshold = [6/8 fifo, 2/8 fifo] */
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writel(DBLAC_DEFAULT, ®s->dblac);
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/* disable & clear all interrupt status */
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chip->imr = 0;
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writel(ISR_ALL, ®s->isr);
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writel(chip->imr, ®s->imr);
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/* enable mac */
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writel(chip->maccr, ®s->maccr);
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return 0;
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}
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static int ftmac110_probe(struct eth_device *dev, struct bd_info *bis)
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{
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debug("ftmac110: probe\n");
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if (ftmac110_reset(dev))
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return -1;
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return 0;
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}
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static void ftmac110_halt(struct eth_device *dev)
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{
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_regs *regs = chip->regs;
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writel(0, ®s->imr);
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writel(0, ®s->maccr);
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debug("ftmac110: halt\n");
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}
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static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
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{
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_regs *regs = chip->regs;
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struct ftmac110_desc *txd;
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uint64_t ctrl;
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if (!chip->lnkup)
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return 0;
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if (len <= 0 || len > CFG_XBUF_SIZE) {
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printf("ftmac110: bad tx pkt len(%d)\n", len);
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return 0;
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}
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len = max(60, len);
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txd = &chip->txd[chip->txd_idx];
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ctrl = le64_to_cpu(txd->ctrl);
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if (ctrl & FTMAC110_TXD_OWNER) {
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/* kick-off Tx DMA */
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writel(0xffffffff, ®s->txpd);
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printf("ftmac110: out of txd\n");
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return 0;
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}
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memcpy(txd->vbuf, (void *)pkt, len);
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dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
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/* clear control bits */
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ctrl &= FTMAC110_TXD_CLRMASK;
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/* set len, fts and lts */
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ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
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/* set owner bit */
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ctrl |= FTMAC110_TXD_OWNER;
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/* write back to descriptor */
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txd->ctrl = cpu_to_le64(ctrl);
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/* kick-off Tx DMA */
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writel(0xffffffff, ®s->txpd);
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chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
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return len;
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}
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static int ftmac110_recv(struct eth_device *dev)
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{
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struct ftmac110_chip *chip = dev->priv;
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struct ftmac110_desc *rxd;
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uint32_t len, rlen = 0;
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uint64_t ctrl;
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uint8_t *buf;
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if (!chip->lnkup)
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return 0;
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do {
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rxd = &chip->rxd[chip->rxd_idx];
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ctrl = le64_to_cpu(rxd->ctrl);
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if (ctrl & FTMAC110_RXD_OWNER)
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break;
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len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
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buf = rxd->vbuf;
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if (ctrl & FTMAC110_RXD_ERRMASK) {
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printf("ftmac110: rx error\n");
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} else {
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dma_map_single(buf, len, DMA_FROM_DEVICE);
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net_process_received_packet(buf, len);
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rlen += len;
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}
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/* owned by hardware */
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ctrl &= FTMAC110_RXD_CLRMASK;
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ctrl |= FTMAC110_RXD_OWNER;
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rxd->ctrl |= cpu_to_le64(ctrl);
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chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
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} while (0);
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return rlen;
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}
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
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int reg)
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{
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uint16_t value = 0;
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int ret = 0;
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struct eth_device *dev;
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dev = eth_get_dev_by_name(bus->name);
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if (dev == NULL) {
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printf("%s: no such device\n", bus->name);
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ret = -1;
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} else {
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value = mdio_read(dev, addr, reg);
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}
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if (ret < 0)
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return ret;
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return value;
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}
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static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
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int reg, u16 value)
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{
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int ret = 0;
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struct eth_device *dev;
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dev = eth_get_dev_by_name(bus->name);
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if (dev == NULL) {
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printf("%s: no such device\n", bus->name);
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ret = -1;
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} else {
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mdio_write(dev, addr, reg, value);
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}
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return ret;
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}
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#endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
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int ftmac110_initialize(struct bd_info *bis)
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{
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int i, card_nr = 0;
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struct eth_device *dev;
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struct ftmac110_chip *chip;
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dev = malloc(sizeof(*dev) + sizeof(*chip));
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if (dev == NULL) {
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panic("ftmac110: out of memory 1\n");
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return -1;
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}
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chip = (struct ftmac110_chip *)(dev + 1);
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memset(dev, 0, sizeof(*dev) + sizeof(*chip));
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sprintf(dev->name, "FTMAC110#%d", card_nr);
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dev->iobase = CONFIG_FTMAC110_BASE;
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chip->regs = (void __iomem *)dev->iobase;
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dev->priv = chip;
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dev->init = ftmac110_probe;
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dev->halt = ftmac110_halt;
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dev->send = ftmac110_send;
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dev->recv = ftmac110_recv;
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/* allocate tx descriptors (it must be 16 bytes aligned) */
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chip->txd = dma_alloc_coherent(
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sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
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if (!chip->txd)
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panic("ftmac110: out of memory 3\n");
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memset(chip->txd, 0,
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sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
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for (i = 0; i < CFG_TXDES_NUM; ++i) {
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void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
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if (!va)
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panic("ftmac110: out of memory 4\n");
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chip->txd[i].vbuf = va;
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chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
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chip->txd[i].ctrl = 0; /* owned by SW */
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}
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chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
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chip->txd_idx = 0;
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/* allocate rx descriptors (it must be 16 bytes aligned) */
|
||||
chip->rxd = dma_alloc_coherent(
|
||||
sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
|
||||
if (!chip->rxd)
|
||||
panic("ftmac110: out of memory 4\n");
|
||||
memset((void *)chip->rxd, 0,
|
||||
sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
|
||||
for (i = 0; i < CFG_RXDES_NUM; ++i) {
|
||||
void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
|
||||
|
||||
if (!va)
|
||||
panic("ftmac110: out of memory 5\n");
|
||||
/* it needs to be exactly 2 bytes aligned */
|
||||
va = ((uint8_t *)va + 2);
|
||||
chip->rxd[i].vbuf = va;
|
||||
chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
|
||||
chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
|
||||
| FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
|
||||
}
|
||||
chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
|
||||
chip->rxd_idx = 0;
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
||||
int retval;
|
||||
struct mii_dev *mdiodev = mdio_alloc();
|
||||
if (!mdiodev)
|
||||
return -ENOMEM;
|
||||
strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
|
||||
mdiodev->read = ftmac110_mdio_read;
|
||||
mdiodev->write = ftmac110_mdio_write;
|
||||
|
||||
retval = mdio_register(mdiodev);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
#endif
|
||||
|
||||
card_nr++;
|
||||
|
||||
return card_nr;
|
||||
}
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Faraday 10/100Mbps Ethernet Controller
|
||||
*
|
||||
* (C) Copyright 2013 Faraday Technology
|
||||
* Dante Su <dantesu@faraday-tech.com>
|
||||
*/
|
||||
|
||||
#ifndef _FTMAC110_H
|
||||
#define _FTMAC110_H
|
||||
|
||||
struct ftmac110_regs {
|
||||
uint32_t isr; /* 0x00: Interrups Status Register */
|
||||
uint32_t imr; /* 0x04: Interrupt Mask Register */
|
||||
uint32_t mac[2]; /* 0x08: MAC Address */
|
||||
uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
|
||||
uint32_t txpd; /* 0x18: Tx Poll Demand Register */
|
||||
uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
|
||||
uint32_t txba; /* 0x20: Tx Ring Base Address Register */
|
||||
uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
|
||||
uint32_t itc; /* 0x28: Interrupt Timer Control Register */
|
||||
uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
|
||||
uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
|
||||
uint32_t revr; /* 0x34: Revision Register */
|
||||
uint32_t fear; /* 0x38: Feature Register */
|
||||
uint32_t rsvd[19];
|
||||
uint32_t maccr; /* 0x88: MAC Control Register */
|
||||
uint32_t macsr; /* 0x8C: MAC Status Register */
|
||||
uint32_t phycr; /* 0x90: PHY Control Register */
|
||||
uint32_t phydr; /* 0x94: PHY Data Register */
|
||||
uint32_t fcr; /* 0x98: Flow Control Register */
|
||||
uint32_t bpr; /* 0x9C: Back Pressure Register */
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt status/mask register(ISR/IMR) bits
|
||||
*/
|
||||
#define ISR_ALL 0x3ff
|
||||
#define ISR_PHYSTCHG (1 << 9) /* phy status change */
|
||||
#define ISR_AHBERR (1 << 8) /* bus error */
|
||||
#define ISR_RXLOST (1 << 7) /* rx lost */
|
||||
#define ISR_RXFIFO (1 << 6) /* rx to fifo */
|
||||
#define ISR_TXLOST (1 << 5) /* tx lost */
|
||||
#define ISR_TXOK (1 << 4) /* tx to ethernet */
|
||||
#define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
|
||||
#define ISR_TXFIFO (1 << 2) /* tx to fifo */
|
||||
#define ISR_NORXBUF (1 << 1) /* out of rx buffer */
|
||||
#define ISR_RXOK (1 << 0) /* rx to buffer */
|
||||
|
||||
/*
|
||||
* MACCR control bits
|
||||
*/
|
||||
#define MACCR_100M (1 << 18) /* 100Mbps mode */
|
||||
#define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
|
||||
#define MACCR_RXMCST (1 << 16) /* rx multicast packet */
|
||||
#define MACCR_FD (1 << 15) /* full duplex */
|
||||
#define MACCR_CRCAPD (1 << 14) /* tx crc append */
|
||||
#define MACCR_RXALL (1 << 12) /* rx all packets */
|
||||
#define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
|
||||
#define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
|
||||
#define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
|
||||
#define MACCR_RXEN (1 << 8) /* rx enable */
|
||||
#define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
|
||||
#define MACCR_TXEN (1 << 5) /* tx enable */
|
||||
#define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
|
||||
#define MACCR_LOOPBACK (1 << 3) /* loop-back */
|
||||
#define MACCR_RESET (1 << 2) /* reset */
|
||||
#define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
|
||||
#define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
|
||||
|
||||
/*
|
||||
* PHYCR control bits
|
||||
*/
|
||||
#define PHYCR_READ (1 << 26)
|
||||
#define PHYCR_WRITE (1 << 27)
|
||||
#define PHYCR_REG_SHIFT 21
|
||||
#define PHYCR_ADDR_SHIFT 16
|
||||
|
||||
/*
|
||||
* ITC control bits
|
||||
*/
|
||||
|
||||
/* Tx Cycle Length */
|
||||
#define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
|
||||
#define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
|
||||
/* Tx Threshold: Aggregate n interrupts as 1 interrupt */
|
||||
#define ITC_TX_THR(n) (((n) & 0x7) << 12)
|
||||
/* Tx Interrupt Timeout = n * Tx Cycle */
|
||||
#define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
|
||||
/* Rx Cycle Length */
|
||||
#define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
|
||||
#define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
|
||||
/* Rx Threshold: Aggregate n interrupts as 1 interrupt */
|
||||
#define ITC_RX_THR(n) (((n) & 0x7) << 4)
|
||||
/* Rx Interrupt Timeout = n * Rx Cycle */
|
||||
#define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
|
||||
|
||||
#define ITC_DEFAULT \
|
||||
(ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
|
||||
|
||||
/*
|
||||
* APTC contrl bits
|
||||
*/
|
||||
|
||||
/* Tx Cycle Length */
|
||||
#define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
|
||||
#define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
|
||||
/* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
|
||||
#define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
|
||||
/* Rx Cycle Length */
|
||||
#define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
|
||||
#define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
|
||||
/* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
|
||||
#define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
|
||||
|
||||
#define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
|
||||
|
||||
/*
|
||||
* DBLAC contrl bits
|
||||
*/
|
||||
#define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
|
||||
#define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
|
||||
#define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
|
||||
#define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
|
||||
#define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
|
||||
#define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
|
||||
#define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
|
||||
#define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
|
||||
#define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
|
||||
|
||||
#define DBLAC_DEFAULT \
|
||||
(DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
|
||||
|
||||
/*
|
||||
* descriptor structure
|
||||
*/
|
||||
struct ftmac110_desc {
|
||||
uint64_t ctrl;
|
||||
uint32_t pbuf;
|
||||
void *vbuf;
|
||||
};
|
||||
|
||||
#define FTMAC110_RXD_END ((uint64_t)1 << 63)
|
||||
#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32)
|
||||
|
||||
#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
|
||||
#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */
|
||||
#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */
|
||||
#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */
|
||||
#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */
|
||||
#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */
|
||||
#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */
|
||||
#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */
|
||||
#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18)
|
||||
#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */
|
||||
#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */
|
||||
#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff))
|
||||
|
||||
#define FTMAC110_RXD_CLRMASK \
|
||||
(FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff))
|
||||
|
||||
#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */
|
||||
#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */
|
||||
#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */
|
||||
#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */
|
||||
#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */
|
||||
#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32)
|
||||
|
||||
#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
|
||||
#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */
|
||||
|
||||
#define FTMAC110_TXD_CLRMASK \
|
||||
(FTMAC110_TXD_END)
|
||||
|
||||
#endif /* FTMAC110_H */
|
||||
Loading…
Reference in New Issue