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MIPS: mscc: ocelot: add switch reset support 

On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Gregory CLEMENT 2019-01-17 17:07:14 +01:00 committed by Daniel Schwierzeck
parent c8546163fa
commit 2f8d067736
1 changed files with 24 additions and 0 deletions
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24
board/mscc/ocelot/ocelot.c
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@ -10,6 +10,7 @@
#include <environment.h> #include <environment.h>
#include <spi.h> #include <spi.h>
#include <led.h> #include <led.h>
#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -18,6 +19,29 @@ enum {
BOARD_TYPE_PCB123, BOARD_TYPE_PCB123,
}; };
void mscc_switch_reset(bool enter)
{
/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
mscc_gpio_set_alternate(19, 2);
debug("applying SwC reset\n");
writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
pr_err("Tiemout while waiting for switch reset\n");
/*
* Reset GPIO19 mode back as regular GPIO, output, high (DDR
* not reset) (Order is important)
*/
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
mscc_gpio_set_alternate(19, 0);
}
void board_debug_uart_init(void) void board_debug_uart_init(void)
{ {
/* too early for the pinctrl driver, so configure the UART pins here */ /* too early for the pinctrl driver, so configure the UART pins here */