arm, davinci, am1808: add lowlevel functions for booting from NOR
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Heiko Schocher
Albert ARIBAUD
parent
337c433383
commit
310ae55efe
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@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS-y += cpu.o timer.o psc.o
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COBJS-$(CONFIG_AM18018_LOWLEVEL) += am1808_lowlevel.o
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COBJS-$(CONFIG_SOC_DM355) += dm355.o
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COBJS-$(CONFIG_SOC_DM365) += dm365.o
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COBJS-$(CONFIG_SOC_DM644X) += dm644x.o
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@ -0,0 +1,428 @@
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/*
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* SoC-specific lowlevel code for AM1808 and similar chips
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <nand.h>
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#include <ns16550.h>
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#include <post.h>
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#include <asm/arch/am1808_lowlevel.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ddr2_defs.h>
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#include <asm/arch/emif_defs.h>
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void am1808_waitloop(unsigned long loopcnt)
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{
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unsigned long i;
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for (i = 0; i < loopcnt; i++)
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asm(" NOP");
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}
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int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
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{
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if (reg == davinci_pllc0_regs)
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/* Unlock PLL registers. */
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clrbits_le32(&davinci_syscfg_regs->cfgchip0, 0x00000010);
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/*
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* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(®->pllctl, 0x00000020);
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/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
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clrbits_le32(®->pllctl, 0x00000200);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(®->pllctl, 0x00000001);
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am1808_waitloop(150);
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if (reg == davinci_pllc0_regs) {
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/*
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* Select the Clock Mode bit 8 as External Clock or On Chip
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* Oscilator
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*/
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dv_maskbits(®->pllctl, 0xFFFFFEFF);
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setbits_le32(®->pllctl, (CONFIG_SYS_DV_CLKMODE << 8));
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}
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/* Clear PLLRST bit to reset the PLL */
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clrbits_le32(®->pllctl, 0x00000008);
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/* Disable the PLL output */
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setbits_le32(®->pllctl, 0x00000010);
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/* PLL initialization sequence */
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/*
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* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
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* power down bit
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*/
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clrbits_le32(®->pllctl, 0x00000002);
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/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
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clrbits_le32(®->pllctl, 0x00000010);
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/* Program the required multiplier value in PLLM */
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writel(pllmult, ®->pllm);
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/* program the postdiv */
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if (reg == davinci_pllc0_regs)
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writel((0x8000 | CONFIG_SYS_AM1808_PLL0_POSTDIV),
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®->postdiv);
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else
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writel((0x8000 | CONFIG_SYS_AM1808_PLL1_POSTDIV),
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®->postdiv);
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/*
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* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
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* no GO operation is currently in progress
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*/
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while ((readl(®->pllstat) & 0x1) == 1)
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;
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if (reg == davinci_pllc0_regs) {
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV1, ®->plldiv1);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV2, ®->plldiv2);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV3, ®->plldiv3);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV4, ®->plldiv4);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV5, ®->plldiv5);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV6, ®->plldiv6);
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writel(CONFIG_SYS_AM1808_PLL0_PLLDIV7, ®->plldiv7);
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} else {
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writel(CONFIG_SYS_AM1808_PLL1_PLLDIV1, ®->plldiv1);
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writel(CONFIG_SYS_AM1808_PLL1_PLLDIV2, ®->plldiv2);
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writel(CONFIG_SYS_AM1808_PLL1_PLLDIV3, ®->plldiv3);
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}
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/*
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* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
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* transition.
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*/
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setbits_le32(®->pllcmd, 0x01);
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/*
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* Wait for the GOSTAT bit in PLLSTAT to clear to 0
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* (completion of phase alignment).
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*/
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while ((readl(®->pllstat) & 0x1) == 1)
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;
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/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
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am1808_waitloop(200);
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/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
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setbits_le32(®->pllctl, 0x00000008);
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/* Wait for PLL to lock. See PLL spec for PLL lock time */
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am1808_waitloop(2400);
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/*
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* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
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* mode
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*/
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setbits_le32(®->pllctl, 0x00000001);
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/*
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* clear EMIFA and EMIFB clock source settings, let them
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* run off SYSCLK
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*/
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if (reg == davinci_pllc0_regs)
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dv_maskbits(&davinci_syscfg_regs->cfgchip3, 0xFFFFFFF8);
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return 0;
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}
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void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
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unsigned char domain, unsigned char state)
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{
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struct davinci_psc_regs *reg;
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dv_reg_p mdstat, mdctl;
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if (pscnum == 0) {
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reg = davinci_psc0_regs;
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mdstat = ®->psc0.mdstat[module];
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mdctl = ®->psc0.mdctl[module];
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} else {
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reg = davinci_psc1_regs;
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mdstat = ®->psc1.mdstat[module];
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mdctl = ®->psc1.mdctl[module];
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}
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/* Wait for any outstanding transition to complete */
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while ((readl(®->ptstat) & (0x00000001 << domain)))
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;
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/* If we are already in that state, just return */
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if ((readl(mdstat) & 0x1F) == state)
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return;
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/* Perform transition */
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writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
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setbits_le32(®->ptcmd, (0x00000001 << domain));
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/* Wait for transition to complete */
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while (readl(®->ptstat) & (0x00000001 << domain))
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;
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/* Wait and verify the state */
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while ((readl(mdstat) & 0x1F) != state)
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;
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}
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int am1808_ddr_setup(unsigned int freq)
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{
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unsigned long tmp;
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/* Enable the Clock to DDR2/mDDR */
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am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
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/* Begin VTP Calibration */
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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/* Polling READY bit to see when VTP calibration is done */
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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while ((tmp & VTP_READY) != VTP_READY)
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
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}
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writel(CONFIG_SYS_AM1808_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
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clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
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(1 << DDR_SLEW_CMOSEN_BIT));
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setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
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writel((CONFIG_SYS_AM1808_DDR2_SDBCR & ~0xf0000000) |
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(readl(&dv_ddr2_regs_ctrl->sdbcr) & 0xf0000000), /*rsv Bytes*/
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&dv_ddr2_regs_ctrl->sdbcr);
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writel(CONFIG_SYS_AM1808_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
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writel(CONFIG_SYS_AM1808_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
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writel(CONFIG_SYS_AM1808_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
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clrbits_le32(&dv_ddr2_regs_ctrl->sdbcr,
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(1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT));
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/*
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* LPMODEN and MCLKSTOPEN must be set!
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* Without this bits set, PSC don;t switch states !!
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*/
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writel(CONFIG_SYS_AM1808_DDR2_SDRCR |
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(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
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(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
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&dv_ddr2_regs_ctrl->sdrcr);
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/* SyncReset the Clock to EMIF3A SDRAM */
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am1808_lpc_transition(1, 6, 0, PSC_SYNCRESET);
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/* Enable the Clock to EMIF3A SDRAM */
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am1808_lpc_transition(1, 6, 0, PSC_ENABLE);
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/* disable self refresh */
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clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);
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writel(0x30, &dv_ddr2_regs_ctrl->pbbpr);
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return 0;
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}
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static void am1808_set_mdctl(dv_reg_p mdctl)
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{
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if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
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writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
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}
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void am1808_psc_init(void)
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{
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struct davinci_psc_regs *reg;
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int i;
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/* PSC 0 domain 0 init */
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reg = davinci_psc0_regs;
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while ((readl(®->ptstat) & 0x00000001))
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;
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for (i = 3; i <= 4 ; i++)
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am1808_set_mdctl(®->psc0.mdctl[i]);
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for (i = 7; i <= 12 ; i++)
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am1808_set_mdctl(®->psc0.mdctl[i]);
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/* Do Always-On Power Domain Transitions */
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setbits_le32(®->ptcmd, 0x00000001);
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while (readl(®->ptstat) & 0x00000001)
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;
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/* PSC1, domain 1 init */
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reg = davinci_psc1_regs;
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while ((readl(®->ptstat) & 0x00000001))
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;
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am1808_set_mdctl(®->psc1.mdctl[3]);
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am1808_set_mdctl(®->psc1.mdctl[6]);
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/* UART1 + UART2 */
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for (i = 12 ; i <= 13 ; i++)
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am1808_set_mdctl(®->psc1.mdctl[i]);
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am1808_set_mdctl(®->psc1.mdctl[26]);
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am1808_set_mdctl(®->psc1.mdctl[31]);
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/* Do Always-On Power Domain Transitions */
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setbits_le32(®->ptcmd, 0x00000001);
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while (readl(®->ptstat) & 0x00000001)
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;
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}
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void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
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unsigned long value)
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{
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clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
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setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
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}
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__attribute__((weak))
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void board_gpio_init(void)
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{
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return;
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}
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#if defined(CONFIG_NAND_SPL)
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/* copy image from NOR to RAM */
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memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST,
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(void *)CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE);
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/* and jump to it ... */
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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(*uboot)();
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}
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#endif
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#if defined(CONFIG_NAND_SPL)
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void board_init_f(ulong bootflag)
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#else
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int arch_cpu_init(void)
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#endif
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{
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/*
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* copied from arch/arm/cpu/arm926ejs/start.S
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*
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* flush v4 I/D caches
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*/
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asm("mov r0, #0");
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asm("mcr p15, 0, r0, c7, c7, 0"); /* flush v3/v4 cache */
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asm("mcr p15, 0, r0, c8, c7, 0"); /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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asm("mrc p15, 0, r0, c1, c0, 0");
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/* clear bits 13, 9:8 (--V- --RS) */
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asm("bic r0, r0, #0x00002300");
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/* clear bits 7, 2:0 (B--- -CAM) */
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asm("bic r0, r0, #0x00000087");
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/* set bit 2 (A) Align */
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asm("orr r0, r0, #0x00000002");
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/* set bit 12 (I) I-Cache */
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asm("orr r0, r0, #0x00001000");
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asm("mcr p15, 0, r0, c1, c0, 0");
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/* Unlock kick registers */
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writel(0x83e70b13, &davinci_syscfg_regs->kick0);
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writel(0x95a4f1e0, &davinci_syscfg_regs->kick1);
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dv_maskbits(&davinci_syscfg_regs->suspsrc,
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((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) | (1 << 16)));
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/* System PSC setup - enable all */
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am1808_psc_init();
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/* Setup Pinmux */
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am1808_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX0);
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am1808_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX1);
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am1808_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX2);
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am1808_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX3);
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am1808_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX4);
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am1808_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX5);
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am1808_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX6);
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am1808_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX7);
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am1808_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX8);
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am1808_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX9);
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am1808_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX10);
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am1808_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX11);
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am1808_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX12);
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am1808_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX13);
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am1808_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX14);
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am1808_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX15);
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am1808_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX16);
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am1808_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX17);
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am1808_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX18);
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am1808_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_AM1808_PINMUX19);
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/* PLL setup */
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am1808_pll_init(davinci_pllc0_regs, CONFIG_SYS_AM1808_PLL0_PLLM);
|
||||
am1808_pll_init(davinci_pllc1_regs, CONFIG_SYS_AM1808_PLL1_PLLM);
|
||||
|
||||
/* GPIO setup */
|
||||
board_gpio_init();
|
||||
|
||||
/* setup CSn config */
|
||||
writel(CONFIG_SYS_AM1808_CS2CFG, &davinci_emif_regs->ab1cr);
|
||||
writel(CONFIG_SYS_AM1808_CS3CFG, &davinci_emif_regs->ab2cr);
|
||||
|
||||
am1808_lpc_transition(1, 13, 0, PSC_ENABLE);
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
/*
|
||||
* Fix Power and Emulation Management Register
|
||||
* see sprufw3a.pdf page 37 Table 24
|
||||
*/
|
||||
writel(readl((CONFIG_SYS_NS16550_COM1 + 0x30)) | 0x00006001,
|
||||
(CONFIG_SYS_NS16550_COM1 + 0x30));
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
puts("ddr init\n");
|
||||
am1808_ddr_setup(132);
|
||||
|
||||
puts("boot u-boot ...\n");
|
||||
|
||||
nand_boot();
|
||||
#else
|
||||
am1808_ddr_setup(132);
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* SoC-specific lowlevel code for AM1808 and similar chips
|
||||
*
|
||||
* Copyright (C) 2011
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __AM1808_LOWLEVEL_H
|
||||
#define __AM1808_LOWLEVEL_H
|
||||
|
||||
/* NOR Boot Configuration Word Field Descriptions */
|
||||
#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8)
|
||||
#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4)
|
||||
#define AM1808_NORBOOT_16BIT (1 << 0)
|
||||
|
||||
#define dv_maskbits(addr, val) \
|
||||
writel((readl(addr) & val), addr)
|
||||
|
||||
void am1808_waitloop(unsigned long loopcnt);
|
||||
int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
|
||||
void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
|
||||
unsigned char domain, unsigned char state);
|
||||
int am1808_ddr_setup(unsigned int freq);
|
||||
void am1808_psc_init(void);
|
||||
void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
|
||||
unsigned long value);
|
||||
|
||||
#endif /* #ifndef __AM1808_LOWLEVEL_H */
|
||||
Loading…
Reference in New Issue