LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.0 

Synchronize R-Car Gen3 device trees with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2019-03-04 22:53:28 +01:00 committed by Marek Vasut
parent 3abd800eb9
commit 317d13ac63
27 changed files with 4149 additions and 843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/dts/r8a7795-h3ulcb-u-boot.dts
View File

@ -19,19 +19,6 @@
}; };
}; };
&vcc_sdhi0 {
u-boot,off-on-delay-us = <20000>;
};
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

3
arch/arm/dts/r8a7795-h3ulcb.dts
View File

@ -41,11 +41,10 @@
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>, <&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>, <&versaclock5 1>,
<&versaclock5 3>, <&versaclock5 3>,
<&versaclock5 4>, <&versaclock5 4>,
<&versaclock5 2>; <&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
}; };

17
arch/arm/dts/r8a7795-salvator-x-u-boot.dts
View File

@ -8,23 +8,6 @@
#include "r8a7795-salvator-x.dts" #include "r8a7795-salvator-x.dts"
#include "r8a7795-u-boot.dtsi" #include "r8a7795-u-boot.dtsi"
&vcc_sdhi0 {
u-boot,off-on-delay-us = <20000>;
};
&vcc_sdhi3 {
u-boot,off-on-delay-us = <20000>;
};
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

5
arch/arm/dts/r8a7795-salvator-x.dts
View File

@ -40,12 +40,11 @@
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>, <&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>, <&versaclock5 1>,
<&x21_clk>, <&x21_clk>,
<&x22_clk>, <&x22_clk>,
<&versaclock5 2>; <&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0", clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
}; };
@ -113,6 +112,7 @@
ports { ports {
/* rsnd_port0 is on salvator-common */ /* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 { rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint { rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>; remote-endpoint = <&dw_hdmi0_snd_in>;
@ -124,6 +124,7 @@
}; };
}; };
rsnd_port2: port@2 { rsnd_port2: port@2 {
reg = <2>;
rsnd_endpoint2: endpoint { rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>; remote-endpoint = <&dw_hdmi1_snd_in>;

4
arch/arm/dts/r8a7795-u-boot.dtsi
View File

@ -11,7 +11,8 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a7795", "renesas,rpc"; compatible = "renesas,rpc-r8a7795", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -20,3 +21,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
};

461
arch/arm/dts/r8a7795.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7795 SoC * Device Tree Source for the R-Car H3 (R8A77950) SoC
* *
* Copyright (C) 2015 Renesas Electronics Corp. * Copyright (C) 2015 Renesas Electronics Corp.
*/ */
@ -116,8 +116,40 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a57_0>;
};
core1 {
cpu = <&a57_1>;
};
core2 {
cpu = <&a57_2>;
};
core3 {
cpu = <&a57_3>;
};
};
cluster1 {
core0 {
cpu = <&a53_0>;
};
core1 {
cpu = <&a53_1>;
};
core2 {
cpu = <&a53_2>;
};
core3 {
cpu = <&a53_3>;
};
};
};
a57_0: cpu@0 { a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0>; reg = <0x0>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU0>; power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
@ -125,11 +157,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU1>; power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
@ -137,11 +170,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a57_2: cpu@2 { a57_2: cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x2>; reg = <0x2>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU2>; power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
@ -149,11 +183,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a57_3: cpu@3 { a57_3: cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x3>; reg = <0x3>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU3>; power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
@ -161,11 +196,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a53_0: cpu@100 { a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x100>; reg = <0x100>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU0>; power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
@ -173,10 +209,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_1: cpu@101 { a53_1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x101>; reg = <0x101>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU1>; power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
@ -184,10 +221,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_2: cpu@102 { a53_2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x102>; reg = <0x102>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU2>; power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
@ -195,10 +233,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_3: cpu@103 { a53_3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x103>; reg = <0x103>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU3>; power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
@ -206,6 +245,7 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
L2_CA57: cache-controller-0 { L2_CA57: cache-controller-0 {
@ -455,7 +495,6 @@
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 522>; resets = <&cpg 522>;
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
status = "okay";
}; };
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
@ -525,15 +564,6 @@
status = "disabled"; status = "disabled";
}; };
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
};
i2c3: i2c@e66d0000 { i2c3: i2c@e66d0000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -705,9 +735,9 @@
hsusb: usb@e6590000 { hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7795", compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>; reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>; <&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3"; dma-names = "ch0", "ch1", "ch2", "ch3";
@ -715,16 +745,16 @@
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 704>; resets = <&cpg 704>, <&cpg 703>;
status = "disabled"; status = "disabled";
}; };
hsusb3: usb@e659c000 { hsusb3: usb@e659c000 {
compatible = "renesas,usbhs-r8a7795", compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-usbhs";
reg = <0 0xe659c000 0 0x100>; reg = <0 0xe659c000 0 0x200>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
<&usb_dmac3 0>, <&usb_dmac3 1>; <&usb_dmac3 0>, <&usb_dmac3 1>;
dma-names = "ch0", "ch1", "ch2", "ch3"; dma-names = "ch0", "ch1", "ch2", "ch3";
@ -732,7 +762,7 @@
phys = <&usb2_phy3>; phys = <&usb2_phy3>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 705>; resets = <&cpg 705>, <&cpg 700>;
status = "disabled"; status = "disabled";
}; };
@ -805,6 +835,15 @@
status = "disabled"; status = "disabled";
}; };
arm_cc630p: crypto@e6601000 {
compatible = "arm,cryptocell-630p-ree";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xe6601000 0 0x1000>;
clocks = <&cpg CPG_MOD 229>;
resets = <&cpg 229>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
};
dmac0: dma-controller@e6700000 { dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a7795", compatible = "renesas,dmac-r8a7795",
"renesas,rcar-dmac"; "renesas,rcar-dmac";
@ -1921,70 +1960,267 @@
}; };
}; };
rcar_sound,ssi { rcar_sound,ssiu {
ssi0: ssi-0 { ssiu00: ssiu-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x15>, <&audma1 0x16>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi1: ssi-1 { ssiu01: ssiu-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x35>, <&audma1 0x36>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi2: ssi-2 { ssiu02: ssiu-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x37>, <&audma1 0x38>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi3: ssi-3 { ssiu03: ssiu-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x47>, <&audma1 0x48>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi4: ssi-4 { ssiu04: ssiu-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x3F>, <&audma1 0x40>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi5: ssi-5 { ssiu05: ssiu-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x43>, <&audma1 0x44>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi6: ssi-6 { ssiu06: ssiu-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x4F>, <&audma1 0x50>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi7: ssi-7 { ssiu07: ssiu-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x53>, <&audma1 0x54>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi8: ssi-8 { ssiu10: ssiu-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x49>, <&audma1 0x4a>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi9: ssi-9 { ssiu11: ssiu-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x4B>, <&audma1 0x4C>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dma-names = "rx", "tx";
dma-names = "rx", "tx", "rxu", "txu"; };
ssiu12: ssiu-10 {
dmas = <&audma0 0x57>, <&audma1 0x58>;
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
dmas = <&audma0 0x59>, <&audma1 0x5A>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
dmas = <&audma0 0x5F>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dmas = <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx";
};
ssiu21: ssiu-17 {
dmas = <&audma0 0x67>, <&audma1 0x68>;
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
dmas = <&audma0 0xED>, <&audma1 0xEE>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dmas = <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx";
};
ssiu31: ssiu-25 {
dmas = <&audma0 0x21>, <&audma1 0x22>;
dma-names = "rx", "tx";
};
ssiu32: ssiu-26 {
dmas = <&audma0 0x23>, <&audma1 0x24>;
dma-names = "rx", "tx";
};
ssiu33: ssiu-27 {
dmas = <&audma0 0x25>, <&audma1 0x26>;
dma-names = "rx", "tx";
};
ssiu34: ssiu-28 {
dmas = <&audma0 0x27>, <&audma1 0x28>;
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
dmas = <&audma0 0x29>, <&audma1 0x2A>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
dmas = <&audma0 0x17>, <&audma1 0x18>;
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
dmas = <&audma0 0x19>, <&audma1 0x1A>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
dmas = <&audma0 0x1F>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dmas = <&audma0 0x31>, <&audma1 0x32>;
dma-names = "rx", "tx";
};
ssiu47: ssiu-39 {
dmas = <&audma0 0x33>, <&audma1 0x34>;
dma-names = "rx", "tx";
};
ssiu50: ssiu-40 {
dmas = <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx";
};
ssiu60: ssiu-41 {
dmas = <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx";
};
ssiu70: ssiu-42 {
dmas = <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx";
};
ssiu80: ssiu-43 {
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx";
};
ssiu90: ssiu-44 {
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
dmas = <&audma0 0x7F>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dmas = <&audma0 0x81>, <&audma1 0x82>;
dma-names = "rx", "tx";
};
ssiu93: ssiu-47 {
dmas = <&audma0 0x83>, <&audma1 0x84>;
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
dma-names = "rx", "tx";
}; };
}; };
ports { rcar_sound,ssi {
#address-cells = <1>; ssi0: ssi-0 {
#size-cells = <0>; interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
port@0 { dmas = <&audma0 0x01>, <&audma1 0x02>;
reg = <0>; dma-names = "rx", "tx";
}; };
port@1 { ssi1: ssi-1 {
reg = <1>; interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>;
dma-names = "rx", "tx";
}; };
port@2 { ssi2: ssi-2 {
reg = <2>; interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>;
dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>;
dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>;
dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>;
dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>;
dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>;
dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>;
dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>;
dma-names = "rx", "tx";
}; };
}; };
}; };
@ -2098,11 +2334,11 @@
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -2134,11 +2370,11 @@
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0 0xee0e0000 0 0x100>; reg = <0 0xee0e0000 0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 700>; clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
phys = <&usb2_phy3>; phys = <&usb2_phy3>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 700>; resets = <&cpg 700>, <&cpg 705>;
status = "disabled"; status = "disabled";
}; };
@ -2146,12 +2382,12 @@
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>; reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>; companion = <&ohci0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -2185,12 +2421,12 @@
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0 0xee0e0100 0 0x100>; reg = <0 0xee0e0100 0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 700>; clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
phys = <&usb2_phy3>; phys = <&usb2_phy3>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci3>; companion = <&ohci3>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 700>; resets = <&cpg 700>, <&cpg 705>;
status = "disabled"; status = "disabled";
}; };
@ -2199,9 +2435,9 @@
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>; reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -2233,9 +2469,9 @@
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0e0200 0 0x700>; reg = <0 0xee0e0200 0 0x700>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 700>; clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 700>; resets = <&cpg 700>, <&cpg 705>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -2782,9 +3018,7 @@
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7795"; compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>, reg = <0 0xfeb00000 0 0x80000>;
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@ -2792,9 +3026,8 @@
clocks = <&cpg CPG_MOD 724>, clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>, <&cpg CPG_MOD 721>;
<&cpg CPG_MOD 727>; clock-names = "du.0", "du.1", "du.2", "du.3";
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>; vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled"; status = "disabled";
@ -2822,6 +3055,33 @@
port@3 { port@3 {
reg = <3>; reg = <3>;
du_out_lvds0: endpoint { du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7795-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
}; };
}; };
}; };
@ -2855,7 +3115,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor1_passive>; trip = <&sensor1_passive>;
cooling-device = <&a57_0 4 4>; cooling-device = <&a57_0 4 4>,
<&a57_1 4 4>,
<&a57_2 4 4>,
<&a57_3 4 4>;
}; };
}; };
}; };
@ -2881,7 +3144,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor2_passive>; trip = <&sensor2_passive>;
cooling-device = <&a57_0 4 4>; cooling-device = <&a57_0 4 4>,
<&a57_1 4 4>,
<&a57_2 4 4>,
<&a57_3 4 4>;
}; };
}; };
}; };
@ -2907,7 +3173,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor3_passive>; trip = <&sensor3_passive>;
cooling-device = <&a57_0 4 4>; cooling-device = <&a57_0 4 4>,
<&a57_1 4 4>,
<&a57_2 4 4>,
<&a57_3 4 4>;
}; };
}; };
}; };

13
arch/arm/dts/r8a7796-m3ulcb-u-boot.dts
View File

@ -19,19 +19,6 @@
}; };
}; };
&vcc_sdhi0 {
u-boot,off-on-delay-us = <20000>;
};
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

3
arch/arm/dts/r8a7796-m3ulcb.dts
View File

@ -30,10 +30,9 @@
clocks = <&cpg CPG_MOD 724>, clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>, <&versaclock5 1>,
<&versaclock5 3>, <&versaclock5 3>,
<&versaclock5 2>; <&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };

17
arch/arm/dts/r8a7796-salvator-x-u-boot.dts
View File

@ -8,23 +8,6 @@
#include "r8a7796-salvator-x.dts" #include "r8a7796-salvator-x.dts"
#include "r8a7796-u-boot.dtsi" #include "r8a7796-u-boot.dtsi"
&vcc_sdhi0 {
u-boot,off-on-delay-us = <20000>;
};
&vcc_sdhi3 {
u-boot,off-on-delay-us = <20000>;
};
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

3
arch/arm/dts/r8a7796-salvator-x.dts
View File

@ -29,11 +29,10 @@
clocks = <&cpg CPG_MOD 724>, clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>, <&versaclock5 1>,
<&x21_clk>, <&x21_clk>,
<&versaclock5 2>; <&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };

4
arch/arm/dts/r8a7796-u-boot.dtsi
View File

@ -11,7 +11,8 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a7796", "renesas,rpc"; compatible = "renesas,rpc-r8a7796", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -20,3 +21,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
};

433
arch/arm/dts/r8a7796.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a7796 SoC * Device Tree Source for the R-Car M3-W (R8A77960) SoC
* *
* Copyright (C) 2016-2017 Renesas Electronics Corp. * Copyright (C) 2016-2017 Renesas Electronics Corp.
*/ */
@ -127,8 +127,34 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a57_0>;
};
core1 {
cpu = <&a57_1>;
};
};
cluster1 {
core0 {
cpu = <&a53_0>;
};
core1 {
cpu = <&a53_1>;
};
core2 {
cpu = <&a53_2>;
};
core3 {
cpu = <&a53_3>;
};
};
};
a57_0: cpu@0 { a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0>; reg = <0x0>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU0>; power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
@ -136,11 +162,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU1>; power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
@ -148,11 +175,12 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>; operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
a53_0: cpu@100 { a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x100>; reg = <0x100>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU0>; power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
@ -160,10 +188,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_1: cpu@101 { a53_1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x101>; reg = <0x101>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU1>; power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
@ -171,10 +200,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_2: cpu@102 { a53_2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x102>; reg = <0x102>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU2>; power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
@ -182,10 +212,11 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
a53_3: cpu@103 { a53_3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x103>; reg = <0x103>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU3>; power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
@ -193,6 +224,7 @@
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>; operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
}; };
L2_CA57: cache-controller-0 { L2_CA57: cache-controller-0 {
@ -259,7 +291,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
soc: soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
#address-cells = <2>; #address-cells = <2>;
@ -401,6 +433,76 @@
reg = <0 0xe6060000 0 0x50c>; reg = <0 0xe6060000 0 0x50c>;
}; };
cmt0: timer@e60f0000 {
compatible = "renesas,r8a7796-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a7796-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a7796-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a7796-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7796-cpg-mssr"; compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
@ -434,7 +536,6 @@
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 522>; resets = <&cpg 522>;
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
status = "okay";
}; };
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
@ -675,9 +776,9 @@
hsusb: usb@e6590000 { hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796", compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>; reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>; <&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3"; dma-names = "ch0", "ch1", "ch2", "ch3";
@ -685,7 +786,7 @@
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 704>; resets = <&cpg 704>, <&cpg 703>;
status = "disabled"; status = "disabled";
}; };
@ -1161,6 +1262,9 @@
<&cpg CPG_CORE R8A7796_CLK_S3D1>, <&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 310>; resets = <&cpg 310>;
status = "disabled"; status = "disabled";
@ -1795,56 +1899,267 @@
}; };
}; };
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx";
};
ssiu01: ssiu-1 {
dmas = <&audma0 0x35>, <&audma1 0x36>;
dma-names = "rx", "tx";
};
ssiu02: ssiu-2 {
dmas = <&audma0 0x37>, <&audma1 0x38>;
dma-names = "rx", "tx";
};
ssiu03: ssiu-3 {
dmas = <&audma0 0x47>, <&audma1 0x48>;
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
dmas = <&audma0 0x3F>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dmas = <&audma0 0x43>, <&audma1 0x44>;
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
dmas = <&audma0 0x4F>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dmas = <&audma0 0x53>, <&audma1 0x54>;
dma-names = "rx", "tx";
};
ssiu10: ssiu-8 {
dmas = <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
dmas = <&audma0 0x4B>, <&audma1 0x4C>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dmas = <&audma0 0x57>, <&audma1 0x58>;
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
dmas = <&audma0 0x59>, <&audma1 0x5A>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
dmas = <&audma0 0x5F>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dmas = <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx";
};
ssiu21: ssiu-17 {
dmas = <&audma0 0x67>, <&audma1 0x68>;
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
dmas = <&audma0 0xED>, <&audma1 0xEE>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dmas = <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx";
};
ssiu31: ssiu-25 {
dmas = <&audma0 0x21>, <&audma1 0x22>;
dma-names = "rx", "tx";
};
ssiu32: ssiu-26 {
dmas = <&audma0 0x23>, <&audma1 0x24>;
dma-names = "rx", "tx";
};
ssiu33: ssiu-27 {
dmas = <&audma0 0x25>, <&audma1 0x26>;
dma-names = "rx", "tx";
};
ssiu34: ssiu-28 {
dmas = <&audma0 0x27>, <&audma1 0x28>;
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
dmas = <&audma0 0x29>, <&audma1 0x2A>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
dmas = <&audma0 0x17>, <&audma1 0x18>;
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
dmas = <&audma0 0x19>, <&audma1 0x1A>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
dmas = <&audma0 0x1F>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dmas = <&audma0 0x31>, <&audma1 0x32>;
dma-names = "rx", "tx";
};
ssiu47: ssiu-39 {
dmas = <&audma0 0x33>, <&audma1 0x34>;
dma-names = "rx", "tx";
};
ssiu50: ssiu-40 {
dmas = <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx";
};
ssiu60: ssiu-41 {
dmas = <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx";
};
ssiu70: ssiu-42 {
dmas = <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx";
};
ssiu80: ssiu-43 {
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx";
};
ssiu90: ssiu-44 {
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
dmas = <&audma0 0x7F>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dmas = <&audma0 0x81>, <&audma1 0x82>;
dma-names = "rx", "tx";
};
ssiu93: ssiu-47 {
dmas = <&audma0 0x83>, <&audma1 0x84>;
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi { rcar_sound,ssi {
ssi0: ssi-0 { ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; dmas = <&audma0 0x01>, <&audma1 0x02>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi1: ssi-1 { ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dmas = <&audma0 0x03>, <&audma1 0x04>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi2: ssi-2 { ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; dmas = <&audma0 0x05>, <&audma1 0x06>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi3: ssi-3 { ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; dmas = <&audma0 0x07>, <&audma1 0x08>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi4: ssi-4 { ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; dmas = <&audma0 0x09>, <&audma1 0x0a>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi5: ssi-5 { ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; dmas = <&audma0 0x0b>, <&audma1 0x0c>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi6: ssi-6 { ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; dmas = <&audma0 0x0d>, <&audma1 0x0e>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi7: ssi-7 { ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; dmas = <&audma0 0x0f>, <&audma1 0x10>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi8: ssi-8 { ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; dmas = <&audma0 0x11>, <&audma1 0x12>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
ssi9: ssi-9 { ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; dmas = <&audma0 0x13>, <&audma1 0x14>;
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx";
}; };
}; };
@ -1970,11 +2285,11 @@
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -1994,12 +2309,12 @@
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>; reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>; companion = <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -2021,9 +2336,9 @@
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>; reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -2437,17 +2752,14 @@
du: display@feb00000 { du: display@feb00000 {
compatible = "renesas,du-r8a7796"; compatible = "renesas,du-r8a7796";
reg = <0 0xfeb00000 0 0x70000>, reg = <0 0xfeb00000 0 0x70000>;
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 722>;
<&cpg CPG_MOD 727>; clock-names = "du.0", "du.1", "du.2";
clock-names = "du.0", "du.1", "du.2", "lvds.0";
status = "disabled"; status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>; vsps = <&vspd0 &vspd1 &vspd2>;
@ -2470,6 +2782,33 @@
port@2 { port@2 {
reg = <2>; reg = <2>;
du_out_lvds0: endpoint { du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7796-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
}; };
}; };
}; };
@ -2503,7 +2842,7 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor1_passive>; trip = <&sensor1_passive>;
cooling-device = <&a57_0 5 5>; cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
}; };
}; };
}; };
@ -2529,7 +2868,7 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor2_passive>; trip = <&sensor2_passive>;
cooling-device = <&a57_0 5 5>; cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
}; };
}; };
}; };
@ -2555,7 +2894,7 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&sensor3_passive>; trip = <&sensor3_passive>;
cooling-device = <&a57_0 5 5>; cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
}; };
}; };
}; };

9
arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
View File

@ -19,15 +19,6 @@
}; };
}; };
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

17
arch/arm/dts/r8a77965-salvator-x-u-boot.dts
View File

@ -8,23 +8,6 @@
#include "r8a77965-salvator-x.dts" #include "r8a77965-salvator-x.dts"
#include "r8a77965-u-boot.dtsi" #include "r8a77965-u-boot.dtsi"
&vcc_sdhi0 {
u-boot,off-on-delay-us = <20000>;
};
&vcc_sdhi3 {
u-boot,off-on-delay-us = <20000>;
};
&sdhi2_pins {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
power-source = <1800>;
};
&sdhi2_pins_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
};
&sdhi0 { &sdhi0 {
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;

4
arch/arm/dts/r8a77965-u-boot.dtsi
View File

@ -11,7 +11,8 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77965", "renesas,rpc"; compatible = "renesas,rpc-r8a77965", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -20,3 +21,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
};

479
arch/arm/dts/r8a77965.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a77965 SoC * Device Tree Source for the R-Car M3-N (R8A77965) SoC
* *
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
* *
@ -12,7 +12,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77965-sysc.h> #include <dt-bindings/power/r8a77965-sysc.h>
#define CPG_AUDIO_CLK_I 10 #define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
/ { / {
compatible = "renesas,r8a77965"; compatible = "renesas,r8a77965";
@ -60,26 +60,70 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
a57_0: cpu@0 { a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0>; reg = <0x0>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A77965_PD_CA57_CPU0>; power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A77965_PD_CA57_CPU1>; power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
}; };
L2_CA57: cache-controller-0 { L2_CA57: cache-controller-0 {
@ -131,7 +175,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
soc: soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
#address-cells = <2>; #address-cells = <2>;
@ -306,7 +350,6 @@
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 522>; resets = <&cpg 522>;
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
status = "okay";
}; };
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
@ -545,11 +588,11 @@
}; };
hsusb: usb@e6590000 { hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796", compatible = "renesas,usbhs-r8a77965",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>; reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>; clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>; <&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3"; dma-names = "ch0", "ch1", "ch2", "ch3";
@ -557,7 +600,7 @@
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 704>; resets = <&cpg 704>, <&cpg 703>;
status = "disabled"; status = "disabled";
}; };
@ -634,6 +677,14 @@
resets = <&cpg 219>; resets = <&cpg 219>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
}; };
dmac1: dma-controller@e7300000 { dmac1: dma-controller@e7300000 {
@ -668,6 +719,14 @@
resets = <&cpg 218>; resets = <&cpg 218>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
}; };
dmac2: dma-controller@e7310000 { dmac2: dma-controller@e7310000 {
@ -702,6 +761,14 @@
resets = <&cpg 217>; resets = <&cpg 217>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
}; };
ipmmu_ds0: mmu@e6740000 { ipmmu_ds0: mmu@e6740000 {
@ -728,14 +795,6 @@
#iommu-cells = <1>; #iommu-cells = <1>;
}; };
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77965_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 { ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77965"; compatible = "renesas,ipmmu-r8a77965";
reg = <0 0xe67b0000 0 0x1000>; reg = <0 0xe67b0000 0 0x1000>;
@ -833,11 +892,69 @@
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>; resets = <&cpg 812>;
phy-mode = "rgmii"; phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
can0: can@e6c30000 {
compatible = "renesas,can-r8a77965",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a77965",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77965-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
pwm0: pwm@e6e30000 { pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>; reg = <0 0xe6e30000 0 8>;
@ -951,6 +1068,9 @@
<&cpg CPG_CORE R8A77965_CLK_S3D1>, <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 310>; resets = <&cpg 310>;
status = "disabled"; status = "disabled";
@ -1324,44 +1444,267 @@
}; };
rcar_sound: sound@ec500000 { rcar_sound: sound@ec500000 {
/*
* #sound-dai-cells is required
*
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
*/
/*
* #clock-cells is required for audio_clkout0/1/2/3
*
* clkout : #clock-cells = <0>; <&rcar_sound>;
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
*/
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */ reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */ <0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
/* placeholder */ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&audio_clk_b>,
<&audio_clk_c>,
<&cpg CPG_CORE R8A77965_CLK_S0D4>;
clock-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0",
"src.9", "src.8", "src.7", "src.6",
"src.5", "src.4", "src.3", "src.2",
"src.1", "src.0",
"mix.1", "mix.0",
"ctu.1", "ctu.0",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 1005>,
<&cpg 1006>, <&cpg 1007>,
<&cpg 1008>, <&cpg 1009>,
<&cpg 1010>, <&cpg 1011>,
<&cpg 1012>, <&cpg 1013>,
<&cpg 1014>, <&cpg 1015>;
reset-names = "ssi-all",
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
"ssi.1", "ssi.0";
status = "disabled";
rcar_sound,dvc { rcar_sound,dvc {
dvc0: dvc-0 { dvc0: dvc-0 {
dmas = <&audma1 0xbc>;
dma-names = "tx";
}; };
dvc1: dvc-1 { dvc1: dvc-1 {
dmas = <&audma1 0xbe>;
dma-names = "tx";
}; };
}; };
rcar_sound,mix {
mix0: mix-0 { };
mix1: mix-1 { };
};
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
ctu02: ctu-2 { };
ctu03: ctu-3 { };
ctu10: ctu-4 { };
ctu11: ctu-5 { };
ctu12: ctu-6 { };
ctu13: ctu-7 { };
};
rcar_sound,src { rcar_sound,src {
src0: src-0 { src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x85>, <&audma1 0x9a>;
dma-names = "rx", "tx";
}; };
src1: src-1 { src1: src-1 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x87>, <&audma1 0x9c>;
dma-names = "rx", "tx";
};
src2: src-2 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x89>, <&audma1 0x9e>;
dma-names = "rx", "tx";
};
src3: src-3 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
dma-names = "rx", "tx";
};
src4: src-4 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
dma-names = "rx", "tx";
};
src5: src-5 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
dma-names = "rx", "tx";
};
src6: src-6 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x91>, <&audma1 0xb4>;
dma-names = "rx", "tx";
};
src7: src-7 {
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x93>, <&audma1 0xb6>;
dma-names = "rx", "tx";
};
src8: src-8 {
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x95>, <&audma1 0xb8>;
dma-names = "rx", "tx";
};
src9: src-9 {
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x97>, <&audma1 0xba>;
dma-names = "rx", "tx";
}; };
}; };
rcar_sound,ssi { rcar_sound,ssi {
ssi0: ssi-0 { ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
}; };
ssi1: ssi-1 { ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
};
}; };
}; };
ports { audma0: dma-controller@ec700000 {
#address-cells = <1>; compatible = "renesas,dmac-r8a77965",
#size-cells = <0>; "renesas,rcar-dmac";
port@0 { reg = <0 0xec700000 0 0x10000>;
reg = <0>; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
}; GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
port@1 { GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
reg = <1>; GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
}; GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
}; };
audma1: dma-controller@ec720000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
}; };
xhci0: usb@ee000000 { xhci0: usb@ee000000 {
@ -1390,11 +1733,11 @@
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -1414,12 +1757,12 @@
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>; reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>; companion = <&ohci0>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -1441,9 +1784,9 @@
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>; reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1452,9 +1795,9 @@
compatible = "renesas,usb2-phy-r8a77965", compatible = "renesas,usb2-phy-r8a77965",
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>; reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 702>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 702>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -1507,6 +1850,17 @@
status = "disabled"; status = "disabled";
}; };
sata: sata@ee300000 {
compatible = "renesas,sata-r8a77965",
"renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
};
gic: interrupt-controller@f1010000 { gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;
@ -1578,6 +1932,16 @@
status = "disabled"; status = "disabled";
}; };
fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 119>;
renesas,fcp = <&fcpf0>;
};
fcpf0: fcp@fe950000 { fcpf0: fcp@fe950000 {
compatible = "renesas,fcpf"; compatible = "renesas,fcpf";
reg = <0 0xfe950000 0 0x200>; reg = <0 0xfe950000 0 0x200>;
@ -1832,6 +2196,33 @@
port@2 { port@2 {
reg = <2>; reg = <2>;
du_out_lvds0: endpoint { du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a77965-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
}; };
}; };
}; };
@ -1843,14 +2234,6 @@
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
thermal-zones { thermal-zones {
sensor_thermal1: sensor-thermal1 { sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>; polling-delay-passive = <250>;
@ -1895,6 +2278,14 @@
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the board */ /* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 { usb3s0_clk: usb3s0 {
compatible = "fixed-clock"; compatible = "fixed-clock";

4
arch/arm/dts/r8a77970-u-boot.dtsi
View File

@ -11,7 +11,8 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77970", "renesas,rpc"; compatible = "renesas,rpc-r8a77970", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -20,3 +21,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
};

325
arch/arm/dts/r8a77970.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a77970 SoC * Device Tree Source for the R-Car V3M (R8A77970) SoC
* *
* Copyright (C) 2016-2017 Renesas Electronics Corp. * Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc. * Copyright (C) 2017 Cogent Embedded, Inc.
@ -24,13 +24,20 @@
i2c4 = &i2c4; i2c4 = &i2c4;
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
a53_0: cpu@0 { a53_0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0>; reg = <0>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU0>; power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
@ -40,7 +47,7 @@
a53_1: cpu@1 { a53_1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <1>; reg = <1>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU1>; power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
@ -82,13 +89,6 @@
method = "smc"; method = "smc";
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External SCIF clock - to be overridden by boards that provide it */ /* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -96,7 +96,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
soc: soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@ -209,6 +209,76 @@
reg = <0 0xe6060000 0 0x504>; reg = <0 0xe6060000 0 0x504>;
}; };
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77970-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77970-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a77970-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a77970-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr"; compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
@ -230,6 +300,19 @@
#power-domain-cells = <1>; #power-domain-cells = <1>;
}; };
thermal: thermal@e6190000 {
compatible = "renesas,thermal-r8a77970";
reg = <0 0xe6190000 0 0x10
0 0xe6190100 0 0x120>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <0>;
};
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>; #interrupt-cells = <2>;
@ -246,6 +329,71 @@
resets = <&cpg 407>; resets = <&cpg 407>;
}; };
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 125>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 125>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 124>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 124>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 123>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 123>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 122>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 122>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 121>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 121>;
status = "disabled";
};
i2c0: i2c@e6500000 { i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77970", compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c"; "renesas,rcar-gen3-i2c";
@ -473,6 +621,56 @@
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
scif0: serial@e6e60000 { scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77970", compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif", "renesas,rcar-gen3-scif",
@ -544,6 +742,80 @@
status = "disabled"; status = "disabled";
}; };
tpu: pwm@e6e80000 {
compatible = "renesas,tpu-r8a77970", "renesas,tpu";
reg = <0 0xe6e80000 0 0x148>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 304>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 304>;
#pwm-cells = <3>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a77970",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x64>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a77970",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a77970",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 209>;
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
<&dmac2 0x45>, <&dmac2 0x44>;
dma-names = "tx", "rx", "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a77970",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 208>;
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
<&dmac2 0x47>, <&dmac2 0x46>;
dma-names = "tx", "rx", "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vin0: video@e6ef0000 { vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77970"; compatible = "renesas,vin-r8a77970";
@ -754,6 +1026,18 @@
#iommu-cells = <1>; #iommu-cells = <1>;
}; };
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77970",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
status = "disabled";
};
gic: interrupt-controller@f1010000 { gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;
@ -891,6 +1175,25 @@
}; };
}; };
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
};
};
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

157
arch/arm/dts/r8a77990-ebisu-u-boot.dts
View File

@ -8,181 +8,24 @@
#include "r8a77990-ebisu.dts" #include "r8a77990-ebisu.dts"
#include "r8a77990-u-boot.dtsi" #include "r8a77990-u-boot.dtsi"
/ {
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
u-boot,off-on-delay-us = <20000>;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
u-boot,off-on-delay-us = <20000>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>; pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
scif_clk_pins: scif_clk { scif_clk_pins: scif_clk {
groups = "scif_clk_a"; groups = "scif_clk_a";
function = "scif_clk"; function = "scif_clk";
}; };
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi3_pins: sd2 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
sdhi3_pins_uhs: sd2_uhs {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
}; };
&sdhi0 { &sdhi0 {
/* full size SD */
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>; max-frequency = <208000000>;
}; };
&sdhi1 { &sdhi1 {
/* microSD */
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr12; sd-uhs-sdr12;
sd-uhs-sdr25; sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
max-frequency = <208000000>; max-frequency = <208000000>;
}; };
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable;
status = "okay";
};

604
arch/arm/dts/r8a77990-ebisu.dts
View File

@ -28,6 +28,235 @@
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
audio_clkout: audio-clkout {
/*
* This is same as <&rcar_sound 0>
* but needed to avoid cs2000/rcar_sound probe dead-lock
*/
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
};
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vbus0_usb2: regulator-vbus0-usb2 {
compatible = "regulator-fixed";
regulator-name = "USB20_VBUS_CN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
rsnd_ak4613: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rsnd-ak4613";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
};
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
reg_12p0v: regulator2 {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
x13_clk: x13 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&audio_clk_a {
clock-frequency = <22579200>;
}; };
&avb { &avb {
@ -35,7 +264,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
renesas,no-ether-link; renesas,no-ether-link;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay"; status = "okay";
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
@ -47,7 +275,53 @@
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x13_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 { &ehci0 {
dr_mode = "otg";
status = "okay"; status = "okay";
}; };
@ -55,7 +329,151 @@
clock-frequency = <48000000>; clock-frequency = <48000000>;
}; };
&hsusb {
dr_mode = "otg";
status = "okay";
};
&i2c0 {
status = "okay";
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupt-names = "intrq1", "intrq2";
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
<17 IRQ_TYPE_LEVEL_LOW>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@a {
reg = <0xa>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi40_in>;
};
};
};
};
&i2c3 {
status = "okay";
ak4613: codec@10 {
compatible = "asahi-kasei,ak4613";
#sound-dai-cells = <0>;
reg = <0x10>;
clocks = <&rcar_sound 3>;
asahi-kasei,in1-single-end;
asahi-kasei,in2-single-end;
asahi-kasei,out1-single-end;
asahi-kasei,out2-single-end;
asahi-kasei,out3-single-end;
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
};
cs2000: clk-multiplier@4f {
#clock-cells = <0>;
compatible = "cirrus,cs2000-cp";
reg = <0x4f>;
clocks = <&audio_clkout>, <&x12_clk>;
clock-names = "clk_in", "ref_clk";
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24576000>; /* 1/1 divide */
};
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 { &ohci0 {
dr_mode = "otg";
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pciec0 {
status = "okay"; status = "okay";
}; };
@ -67,8 +485,74 @@
}; };
}; };
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
};
pwm5_pins: pwm5 {
groups = "pwm5_a";
function = "pwm5";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
sdhi3_pins: sd3 {
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
function = "sdhi3";
power-source = <1800>;
};
sound_pins: sound {
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
};
sound_clk_pins: sound_clk {
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
"audio_clkout_a", "audio_clkout1_a";
function = "audio_clk";
};
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
};
usb0_pins: usb { usb0_pins: usb {
groups = "usb0_b"; groups = "usb0_b", "usb0_id";
function = "usb0"; function = "usb0";
}; };
@ -78,19 +562,91 @@
}; };
}; };
&pwm3 {
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm5 {
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "default";
status = "okay";
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;
clkout-lr-synchronous;
status = "okay";
/* update <audio_clk_b> to <cs2000> */
clocks = <&cpg CPG_MOD 1005>,
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
};
};
&rwdt { &rwdt {
timeout-sec = <60>; timeout-sec = <60>;
status = "okay"; status = "okay";
}; };
&scif2 { &scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
&ssi1 {
shared-pin;
};
&usb2_phy0 { &usb2_phy0 {
pinctrl-0 = <&usb0_pins>; pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
vbus-supply = <&vbus0_usb2>;
status = "okay";
};
&usb3_peri0 {
companion = <&xhci0>;
status = "okay";
};
&vin4 {
status = "okay"; status = "okay";
}; };
@ -100,3 +656,47 @@
status = "okay"; status = "okay";
}; };
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&sdhi3 {
/* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi3_pins>;
pinctrl-1 = <&sdhi3_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};

26
arch/arm/dts/r8a77990-u-boot.dtsi
View File

@ -7,7 +7,8 @@
#include "r8a779x-u-boot.dtsi" #include "r8a779x-u-boot.dtsi"
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77990", "renesas,rpc"; compatible = "renesas,rpc-r8a77990", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -15,28 +16,5 @@
bank-width = <2>; bank-width = <2>;
status = "disabled"; status = "disabled";
}; };
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee100000 0 0x2000>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee120000 0 0x2000>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a77990";
reg = <0 0xee160000 0 0x2000>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
status = "disabled";
}; };
}; };

1442
arch/arm/dts/r8a77990.dtsi
View File

File diff suppressed because it is too large Load Diff

496
arch/arm/dts/r8a77995-draak.dts
View File

@ -2,7 +2,7 @@
/* /*
* Device Tree Source for the Draak board * Device Tree Source for the Draak board
* *
* Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba * Copyright (C) 2017 Glider bvba
*/ */
@ -24,6 +24,106 @@
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
default-brightness-level = <10>;
power-supply = <&reg_12p0v>;
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
};
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_12p0v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "D12.0V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
vga { vga {
compatible = "vga-connector"; compatible = "vga-connector";
@ -56,51 +156,6 @@
}; };
}; };
composite-in {
compatible = "composite-video-connector";
port {
composite_con_in: endpoint {
remote-endpoint = <&adv7180_in>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&adv7612_in>;
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
x12_clk: x12 { x12_clk: x12 {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
@ -108,10 +163,210 @@
}; };
}; };
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
dr_mode = "host";
status = "okay";
};
&extal_clk { &extal_clk {
clock-frequency = <48000000>; clock-frequency = <48000000>;
}; };
&hsusb {
dr_mode = "host";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, link it to
* VIN4 here.
*/
adv7180_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
reg-names = "main", "edid", "packet", "cec";
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
/* Depends on LVDS */
max-clock = <135000000>;
min-vrefresh = <50>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, leave HDMI
* not connected here.
*/
adv7612_out: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&lvds0 {
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&lvds1 {
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
clock-names = "fck", "dclkin.0", "extal";
};
&ohci0 {
dr_mode = "host";
status = "okay";
};
&pfc { &pfc {
avb0_pins: avb { avb0_pins: avb {
mux { mux {
@ -173,136 +428,23 @@
}; };
}; };
&i2c0 { &pwm0 {
pinctrl-0 = <&i2c0_pins>; pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
}; };
composite-in@20 { &pwm1 {
compatible = "adi,adv7180cp"; pinctrl-0 = <&pwm1_pins>;
reg = <0x20>;
port {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7180_in: endpoint {
remote-endpoint = <&composite_con_in>;
};
};
port@3 {
reg = <3>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, link it to
* VIN4 here.
*/
adv7180_out: endpoint {
remote-endpoint = <&vin4_in>;
};
};
};
};
hdmi-decoder@4c {
compatible = "adi,adv7612";
reg = <0x4c>;
default-input = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7612_in: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
port@2 {
reg = <2>;
/*
* The VIN4 video input path is shared between
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
* CVBS is the default selection, leave HDMI
* not connected here.
*/
adv7612_out: endpoint {
pclk-sample = <0>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
&du { &rwdt {
pinctrl-0 = <&du_pins>; timeout-sec = <60>;
pinctrl-names = "default";
status = "okay"; status = "okay";
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&x12_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&ehci0 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
}; };
&scif2 { &scif2 {
@ -330,25 +472,7 @@
pinctrl-0 = <&usb0_pins>; pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; renesas,no-otg-pins;
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay"; status = "okay";
}; };

4
arch/arm/dts/r8a77995-u-boot.dtsi
View File

@ -7,7 +7,8 @@
#include "r8a779x-u-boot.dtsi" #include "r8a779x-u-boot.dtsi"
&soc { / {
soc {
rpc: rpc@0xee200000 { rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77995", "renesas,rpc"; compatible = "renesas,rpc-r8a77995", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
@ -16,3 +17,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
};

131
arch/arm/dts/r8a77995.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Device Tree Source for the r8a77995 SoC * Device Tree Source for the R-Car D3 (R8A77995) SoC
* *
* Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba * Copyright (C) 2017 Glider bvba
@ -27,7 +27,7 @@
#size-cells = <0>; #size-cells = <0>;
a53_0: cpu@0 { a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0>; reg = <0x0>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A77995_PD_CA53_CPU0>; power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
@ -66,7 +66,7 @@
clock-frequency = <0>; clock-frequency = <0>;
}; };
soc: soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
#address-cells = <2>; #address-cells = <2>;
@ -344,6 +344,51 @@
status = "disabled"; status = "disabled";
}; };
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a77995",
"renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 704>, <&cpg 703>;
status = "disabled";
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a77995-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a77995-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
canfd: can@e66c0000 { canfd: can@e66c0000 {
compatible = "renesas,r8a77995-canfd", compatible = "renesas,r8a77995-canfd",
"renesas,rcar-gen3-canfd"; "renesas,rcar-gen3-canfd";
@ -391,6 +436,10 @@
resets = <&cpg 219>; resets = <&cpg 219>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <8>; dma-channels = <8>;
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
}; };
dmac1: dma-controller@e7300000 { dmac1: dma-controller@e7300000 {
@ -415,6 +464,10 @@
resets = <&cpg 218>; resets = <&cpg 218>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <8>; dma-channels = <8>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
}; };
dmac2: dma-controller@e7310000 { dmac2: dma-controller@e7310000 {
@ -439,6 +492,10 @@
resets = <&cpg 217>; resets = <&cpg 217>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <8>; dma-channels = <8>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
}; };
ipmmu_ds0: mmu@e6740000 { ipmmu_ds0: mmu@e6740000 {
@ -817,11 +874,11 @@
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -829,12 +886,12 @@
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>; reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>; companion = <&ohci0>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
@ -843,9 +900,9 @@
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>; reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -960,12 +1017,68 @@
port@1 { port@1 {
reg = <1>; reg = <1>;
du_out_lvds0: endpoint { du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
}; };
}; };
port@2 { port@2 {
reg = <2>; reg = <2>;
du_out_lvds1: endpoint { du_out_lvds1: endpoint {
remote-endpoint = <&lvds1_in>;
};
};
};
};
lvds0: lvds-encoder@feb90000 {
compatible = "renesas,r8a77995-lvds";
reg = <0 0xfeb90000 0 0x20>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
lvds1: lvds-encoder@feb90100 {
compatible = "renesas,r8a77995-lvds";
reg = <0 0xfeb90100 0 0x20>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds1_in: endpoint {
remote-endpoint = <&du_out_lvds1>;
};
};
port@1 {
reg = <1>;
lvds1_out: endpoint {
}; };
}; };
}; };

23
arch/arm/dts/salvator-common.dtsi
View File

@ -420,7 +420,10 @@
video-receiver@70 { video-receiver@70 {
compatible = "adi,adv7482"; compatible = "adi,adv7482";
reg = <0x70>; reg = <0x70 0x71 0x72 0x73 0x74 0x75
0x60 0x61 0x62 0x63 0x64 0x65>;
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -471,6 +474,8 @@
&i2c_dvfs { &i2c_dvfs {
status = "okay"; status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 { pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>; pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -600,12 +605,6 @@
}; };
sdhi2_pins: sd2 { sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2"; function = "sdhi2";
power-source = <1800>; power-source = <1800>;
@ -702,7 +701,10 @@
<&cpg CPG_CORE CPG_AUDIO_CLK_I>; <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
ports { ports {
#address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 { rsnd_port0: port@0 {
reg = <0>;
rsnd_endpoint0: endpoint { rsnd_endpoint0: endpoint {
remote-endpoint = <&ak4613_endpoint>; remote-endpoint = <&ak4613_endpoint>;
@ -748,19 +750,21 @@
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>; bus-width = <4>;
sd-uhs-sdr50; sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay"; status = "okay";
}; };
&sdhi2 { &sdhi2 {
/* used for on-board 8bit eMMC */ /* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>; pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>; pinctrl-1 = <&sdhi2_pins>;
pinctrl-names = "default", "state_uhs"; pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>; vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>; vqmmc-supply = <&reg_1p8v>;
bus-width = <8>; bus-width = <8>;
mmc-hs200-1_8v; mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable; non-removable;
fixed-emmc-driver-type = <1>; fixed-emmc-driver-type = <1>;
status = "okay"; status = "okay";
@ -777,6 +781,7 @@
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>; bus-width = <4>;
sd-uhs-sdr50; sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay"; status = "okay";
}; };
@ -807,6 +812,8 @@
phys = <&usb3_phy0>; phys = <&usb3_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&xhci0>;
status = "okay"; status = "okay";
}; };

79
arch/arm/dts/ulcb.dtsi
View File

@ -6,6 +6,14 @@
* Copyright (C) 2016 Cogent Embedded, Inc. * Copyright (C) 2016 Cogent Embedded, Inc.
*/ */
/*
* SSI-AK4613
* aplay -D plughw:0,0 xxx.wav
* arecord -D plughw:0,0 xxx.wav
* SSI-HDMI
* aplay -D plughw:0,1 xxx.wav
*/
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
@ -18,6 +26,7 @@
}; };
chosen { chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@ -82,20 +91,13 @@
regulator-always-on; regulator-always-on;
}; };
rsnd_ak4613: sound { sound_card: sound {
compatible = "simple-audio-card"; compatible = "audio-graph-card";
label = "rcar-sound";
simple-audio-card,format = "left_j"; dais = <&rsnd_port0 /* ak4613 */
simple-audio-card,bitclock-master = <&sndcpu>; &rsnd_port1 /* HDMI0 */
simple-audio-card,frame-master = <&sndcpu>; >;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4613>;
};
}; };
vcc_sdhi0: regulator-vcc-sdhi0 { vcc_sdhi0: regulator-vcc-sdhi0 {
@ -181,6 +183,12 @@
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_for_hdmi>;
};
};
}; };
}; };
@ -210,6 +218,12 @@
asahi-kasei,out4-single-end; asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end; asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end; asahi-kasei,out6-single-end;
port {
ak4613_endpoint: endpoint {
remote-endpoint = <&rsnd_for_ak4613>;
};
};
}; };
cs2000: clk-multiplier@4f { cs2000: clk-multiplier@4f {
@ -241,6 +255,8 @@
&i2c_dvfs { &i2c_dvfs {
status = "okay"; status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 { pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>; pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
@ -327,12 +343,6 @@
}; };
sdhi2_pins: sd2 { sdhi2_pins: sd2 {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2"; function = "sdhi2";
power-source = <1800>; power-source = <1800>;
@ -387,12 +397,35 @@
<&audio_clk_c>, <&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>; <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
rcar_sound,dai { ports {
dai0 { #address-cells = <1>;
#size-cells = <0>;
rsnd_port0: port@0 {
reg = <0>;
rsnd_for_ak4613: endpoint {
remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_for_ak4613>;
frame-master = <&rsnd_for_ak4613>;
playback = <&ssi0 &src0 &dvc0>; playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>; capture = <&ssi1 &src1 &dvc1>;
}; };
}; };
rsnd_port1: port@1 {
reg = <1>;
rsnd_for_hdmi: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_for_hdmi>;
frame-master = <&rsnd_for_hdmi>;
playback = <&ssi2>;
};
};
};
}; };
&scif2 { &scif2 {
@ -416,19 +449,21 @@
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>; bus-width = <4>;
sd-uhs-sdr50; sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay"; status = "okay";
}; };
&sdhi2 { &sdhi2 {
/* used for on-board 8bit eMMC */ /* used for on-board 8bit eMMC */
pinctrl-0 = <&sdhi2_pins>; pinctrl-0 = <&sdhi2_pins>;
pinctrl-1 = <&sdhi2_pins_uhs>; pinctrl-1 = <&sdhi2_pins>;
pinctrl-names = "default", "state_uhs"; pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>; vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>; vqmmc-supply = <&reg_1p8v>;
bus-width = <8>; bus-width = <8>;
mmc-hs200-1_8v; mmc-hs200-1_8v;
mmc-hs400-1_8v;
non-removable; non-removable;
status = "okay"; status = "okay";
}; };