MX35: factorize common assembly code
Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
Albert ARIBAUD
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d330883f03
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324a131e7c
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_MPR_CONFIG
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_OPACR_CONFIG
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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.endm
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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ldr r0, =MAX_BASE_ADDR
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =MAX_MPR_CONFIG
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =MAX_SGPCR_CONFIG
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =MAX_MGPCR_CONFIG
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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.endm
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/* M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =M3IF_BASE_ADDR
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =M3IF_CONFIG
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str r0, [r1] /* M3IF control reg */
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.endm
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.macro core_init
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mrc 15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11)
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/* Set unaligned access enable */
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orr r1, r1, #(1<<22)
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/* Set low int latency enable */
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orr r1, r1, #(1<<21)
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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/* Set branch prediction enable */
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mcr 15, 0, r0, c15, c2, 4
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/*
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* initializes very early AIPS
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF
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* Also setup the Peripheral Port Remap register inside the core
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*/
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ldr r0, =0x40000015 /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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.endm
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