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sun5i: Add NAND controller to the sun5i DTSI 

Add the NAND controller definition to sun5i.dtsi.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Maxime Ripard 2016-06-15 21:09:24 +02:00 committed by Scott Wood
parent 4ccae81cda
commit 32b18435de
1 changed files with 49 additions and 0 deletions
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49
arch/arm/dts/sun5i.dtsi
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@ -356,6 +356,17 @@
#dma-cells = <2>;
};
nfc: nand@01c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
clocks = <&ahb_gates 13>, <&nand_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
@ -548,6 +559,44 @@
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
nand_pins_a: nand_base0@0 {
allwinner,pins = "PC0", "PC1", "PC2",
"PC5", "PC8", "PC9", "PC10",
"PC11", "PC12", "PC13", "PC14",
"PC15";
allwinner,function = "nand0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
nand_cs0_pins_a: nand_cs@0 {
allwinner,pins = "PC4";
allwinner,function = "nand0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
nand_cs1_pins_a: nand_cs@1 {
allwinner,pins = "PC3";
allwinner,function = "nand0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
nand_rb0_pins_a: nand_rb@0 {
allwinner,pins = "PC6";
allwinner,function = "nand0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
nand_rb1_pins_a: nand_rb@1 {
allwinner,pins = "PC7";
allwinner,function = "nand0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart3_pins_a: uart3@0 {
allwinner,pins = "PG9", "PG10";
allwinner,function = "uart3";