MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton
Daniel Schwierzeck
parent
ace3be4f15
commit
372286217f
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@ -252,21 +252,27 @@ config SYS_DCACHE_SIZE
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help
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The total size of the L1 Dcache, if known at compile time.
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config SYS_DCACHE_LINE_SIZE
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hex
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default 0
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help
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The size of L1 Dcache lines, if known at compile time.
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config SYS_ICACHE_SIZE
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int
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default 0
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help
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The total size of the L1 ICache, if known at compile time.
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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int
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default 0
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help
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The size of L1 cache lines, if known at compile time.
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The size of L1 Icache lines, if known at compile time.
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config SYS_CACHE_SIZE_AUTO
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def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
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SYS_CACHELINE_SIZE = 0
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SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
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help
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Select this (or let it be auto-selected by not defining any cache
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sizes) in order to allow U-Boot to automatically detect the sizes
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@ -12,4 +12,11 @@
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#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
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/*
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* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
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* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
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* of ARCH_DMA_MINALIGN for now.
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*/
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#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
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#endif /* __MIPS_CACHE_H__ */
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@ -9,23 +9,13 @@
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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static inline unsigned long icache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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static inline unsigned long dcache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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#else /* !CONFIG_SYS_CACHELINE_SIZE */
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static inline unsigned long icache_line_size(void)
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{
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unsigned long conf1, il;
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if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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return CONFIG_SYS_ICACHE_LINE_SIZE;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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if (!il)
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@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
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static inline unsigned long dcache_line_size(void)
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{
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unsigned long conf1, dl;
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if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
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return CONFIG_SYS_DCACHE_LINE_SIZE;
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conf1 = read_c0_config1();
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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if (!dl)
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@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
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return 2 << dl;
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}
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#endif /* !CONFIG_SYS_CACHELINE_SIZE */
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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@ -101,14 +101,14 @@
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LEAF(mips_cache_reset)
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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li t2, CONFIG_SYS_ICACHE_SIZE
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li t8, CONFIG_SYS_CACHELINE_SIZE
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li t8, CONFIG_SYS_ICACHE_LINE_SIZE
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#else
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l1_info t2, t8, MIPS_CONF1_IA_SHF
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#endif
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#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
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li t3, CONFIG_SYS_DCACHE_SIZE
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li t9, CONFIG_SYS_CACHELINE_SIZE
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li t9, CONFIG_SYS_DCACHE_LINE_SIZE
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#else
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l1_info t3, t9, MIPS_CONF1_DA_SHF
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#endif
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@ -15,10 +15,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 16384
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 16384
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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menu "dbau1x00 board options"
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@ -15,10 +15,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 16384
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 16384
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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menu "vct board options"
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@ -15,10 +15,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 16384
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 16384
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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@ -15,10 +15,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 65536
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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@ -15,10 +15,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 65536
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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@ -14,10 +14,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 16384
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 16384
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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@ -18,10 +18,13 @@ config SYS_TEXT_BASE
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 65536
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config SYS_CACHELINE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 32
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endif
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@ -100,7 +100,6 @@
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* USB Configuration
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*/
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#define CONFIG_USB_MUSB_PIO_ONLY
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#define CONFIG_SYS_CACHELINE_SIZE 16
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/*-----------------------------------------------------------------------
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* File System Configuration
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