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video: ipu: avoid overflow issue 

Multiplication, as "clk->parent->rate * 16" may overflow. So use
do_div to avoid such issue.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Peng Fan 2016-03-09 16:07:21 +08:00 committed by Anatolij Gustschin
parent c87c30e3ba
commit 3cb4f25cc7
1 changed files with 54 additions and 19 deletions
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73
drivers/video/ipu_common.c
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@ -19,6 +19,7 @@
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h> #include <asm/arch/crm_regs.h>
#include <div64.h>
#include "ipu.h" #include "ipu.h"
#include "ipu_regs.h" #include "ipu_regs.h"
@ -275,50 +276,84 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
static void ipu_pixel_clk_recalc(struct clk *clk) static void ipu_pixel_clk_recalc(struct clk *clk)
{ {
u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); u32 div;
if (div == 0) u64 final_rate = (unsigned long long)clk->parent->rate * 16;
clk->rate = 0;
else div = __raw_readl(DI_BS_CLKGEN0(clk->id));
clk->rate = (clk->parent->rate * 16) / div; debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
div, final_rate, clk->parent->rate);
clk->rate = 0;
if (div != 0) {
do_div(final_rate, div);
clk->rate = final_rate;
}
} }
static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
unsigned long rate) unsigned long rate)
{ {
u32 div, div1; u64 div, final_rate;
u32 tmp; u32 remainder;
u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
/* /*
* Calculate divider * Calculate divider
* Fractional part is 4 bits, * Fractional part is 4 bits,
* so simply multiply by 2^4 to get fractional part. * so simply multiply by 2^4 to get fractional part.
*/ */
tmp = (clk->parent->rate * 16); div = parent_rate;
div = tmp / rate; remainder = do_div(div, rate);
/* Round the divider value */
if (remainder > (rate / 2))
div++;
if (div < 0x10) /* Min DI disp clock divider is 1 */ if (div < 0x10) /* Min DI disp clock divider is 1 */
div = 0x10; div = 0x10;
if (div & ~0xFEF) if (div & ~0xFEF)
div &= 0xFF8; div &= 0xFF8;
else { else {
div1 = div & 0xFE0; /* Round up divider if it gets us closer to desired pix clk */
if ((tmp/div1 - tmp/div) < rate / 4) if ((div & 0xC) == 0xC) {
div = div1; div += 0x10;
else div &= ~0xF;
div &= 0xFF8; }
} }
return (clk->parent->rate * 16) / div; final_rate = parent_rate;
do_div(final_rate, div);
return final_rate;
} }
static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
{ {
u32 div = (clk->parent->rate * 16) / rate; u64 div, parent_rate;
u32 remainder;
parent_rate = (unsigned long long)clk->parent->rate * 16;
div = parent_rate;
remainder = do_div(div, rate);
/* Round the divider value */
if (remainder > (rate / 2))
div++;
/* Round up divider if it gets us closer to desired pix clk */
if ((div & 0xC) == 0xC) {
div += 0x10;
div &= ~0xF;
}
if (div > 0x1000)
debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
__raw_writel(div, DI_BS_CLKGEN0(clk->id)); __raw_writel(div, DI_BS_CLKGEN0(clk->id));
/* Setup pixel clock timing */ /*
* Setup pixel clock timing
* Down time is half of period
*/
__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
clk->rate = (clk->parent->rate * 16) / div; clk->rate = (u64)(clk->parent->rate * 16) / div;
return 0; return 0;
} }