LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

armv8: layerscape: properly use CPU_RELEASE_ADDR 

The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Michael Walle 2020-06-01 21:53:26 +02:00 committed by Priyanka Jain
parent ae846a6119
commit 3d3fe8b12d
8 changed files with 18 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -208,8 +208,13 @@ ENTRY(lowlevel_init)
branch_if_master x0, x1, 2f branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func /*
blr x0 * Formerly, here was a jump to secondary_boot_func, but we just
* return early here and let the generic code in start.S handle
* the jump to secondary_boot_func.
*/
mov lr, x29 /* Restore LR */
ret
#endif #endif
2: 2:
@ -421,6 +426,11 @@ ENDPROC(__asm_flush_l3_dcache)
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP #ifdef CONFIG_MP
.align 3
.global secondary_boot_addr
secondary_boot_addr:
.quad secondary_boot_func
/* Keep literals not used by the secondary boot code outside it */ /* Keep literals not used by the secondary boot code outside it */
.ltorg .ltorg

1
arch/arm/include/asm/arch-fsl-layerscape/mp.h
View File

@ -43,7 +43,6 @@ static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
#endif #endif
void *get_spin_tbl_addr(void); void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void); phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id); int is_core_online(u64 cpu_id);
u32 cpu_pos_mask(void); u32 cpu_pos_mask(void);
#endif #endif

2
include/configs/ls1028a_common.h
View File

@ -28,7 +28,7 @@
/* /*
* SMP Definitinos * SMP Definitinos
*/ */
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ /* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */

2
include/configs/ls1043a_common.h
View File

@ -47,7 +47,7 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ /* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */

2
include/configs/ls1046a_common.h
View File

@ -48,7 +48,7 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ /* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */

2
include/configs/ls1088a_common.h
View File

@ -48,7 +48,7 @@
/* /*
* SMP Definitinos * SMP Definitinos
*/ */
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
/* Size of malloc() pool */ /* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)

2
include/configs/ls2080a_common.h
View File

@ -42,7 +42,7 @@
/* /*
* SMP Definitinos * SMP Definitinos
*/ */
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR #ifdef CONFIG_SYS_FSL_HAS_DP_DDR

2
include/configs/lx2160a_common.h
View File

@ -52,7 +52,7 @@
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
/* SMP Definitinos */ /* SMP Definitinos */
#define CPU_RELEASE_ADDR secondary_boot_func #define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */ /* Generic Timer Definitions */
/* /*