From 3f5bee91bbb9227ff27d962452ef0c295a1bd2ec Mon Sep 17 00:00:00 2001 From: straub Date: Fri, 6 Jul 2018 14:05:45 +0200 Subject: [PATCH] hancock: integration of sja1105 driver feature --- board/nm/hancock/board.c | 91 +++++++------ board/nm/hancock/sja1105.c | 265 +++++++++++++++++++++++-------------- board/nm/hancock/sja1105.h | 33 +++-- 3 files changed, 225 insertions(+), 164 deletions(-) diff --git a/board/nm/hancock/board.c b/board/nm/hancock/board.c index e41d423c23..4ef5e9a30a 100644 --- a/board/nm/hancock/board.c +++ b/board/nm/hancock/board.c @@ -485,48 +485,36 @@ static void init_ethernet_switch(void) if (spi == 0) { configure_module_pin_mux(spi1_pin_mux); - - /* TODO: Check whether bitrate can be increased to 5..10MHz */ spi_init(); + /*Maximum bitrate supported by switch is 17.8 MHz */ spi = spi_setup_slave(CONFIG_SJA1105_SPI_BUS /*bus*/, CONFIG_SJA1105_SPI_CS /*cs*/, - 1000000 /*max_hz*/, + 15000000 /* 15 MHz */, SPI_MODE_1 /*spi_mode*/); -/* spi_set_wordlen(spi,32);*/ + /* Takes and remembers SPI driver for later calls*/ + sja1105_init(spi); } spi_claim_bus(spi); + mdelay(1); + /* 1ms delay is required to have a first valid spi transaction after init*/ + /* Read Devide Id*/ + val = sja1105_read_reg( 0x000000); - /* TODO: Remove debug printout later on */ - val = sja1105_read_reg(spi, 0x000000); - /* printf("Device ID: %08x\n", val); */ - - val = sja1105_read_reg(spi, 0x000001); - /* printf("Status Reg: %08x\n", val); */ - - sja1105_static_init(spi, 0 /*dummy*/); + sja1105_configure_firmware(0); /* Check that config was properly loaded */ - val = sja1105_read_reg(spi, 0x000001); - /* printf("Status Reg: %08x\n", val); */ + val = sja1105_read_reg( 0x000001); if ((val & 0x80000000) != 0x80000000) { printf("ERROR: Switch configuration load failed\n"); } /* Configure clocks */ - sja1105_dynamic_init(spi); + sja1105_configure_mode_and_clocks(); - /* - val = sja1105_read_reg(spi, 0x000001); - printf("Status Reg: %08x\n", val); - */ + /* COnfigureIO pads */ + sja1105_configure_io(); - /* Enable pull down on CPU Port RX_ER etc. */ - sja1105_write_reg(spi, 0x100809, 0x03020313); -#if 0 - val = sja1105_read_reg(spi, 0x100809); - printf("CFG_PAD_MII4_RX Reg: %08x\n", val); -#endif spi_release_bus(spi); } @@ -849,6 +837,7 @@ static void check_reset_button(void) int board_late_init(void) { + #if !defined(CONFIG_SPL_BUILD) if (read_eeprom() < 0) { puts("Could not get board ID.\n"); @@ -1031,41 +1020,57 @@ int board_fit_config_name_match(const char *name) static int do_sjainfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + uint32_t p0_mac_stat; + uint32_t p0_txf; + uint32_t p0_rxf; + uint32_t p1_mac_stat; + uint32_t p1_txf; + uint32_t p1_rxf; + uint32_t p2_mac_stat; + uint32_t p2_rxf; + uint32_t p2_txf; uint32_t p3_mac_stat; uint32_t p3_txf; uint32_t p3_rxf; uint32_t p4_mac_stat; uint32_t p4_rxf; uint32_t p4_txf; - uint32_t conf_pad4_1; - uint32_t conf_pad4_2; spi_claim_bus(spi); - p3_mac_stat = sja1105_read_reg(spi, 0x00206); - p3_rxf = sja1105_read_reg(spi, 0x00436); - p3_txf = sja1105_read_reg(spi, 0x00432); + p0_mac_stat = sja1105_read_reg(0x00200); + p0_rxf = sja1105_read_reg(0x00406); + p0_txf = sja1105_read_reg(0x00402); - p4_mac_stat = sja1105_read_reg(spi, 0x00208); - p4_rxf = sja1105_read_reg(spi, 0x00446); - p4_txf = sja1105_read_reg(spi, 0x00442); + p1_mac_stat = sja1105_read_reg(0x00202); + p1_rxf = sja1105_read_reg(0x00416); + p1_txf = sja1105_read_reg(0x00412); - conf_pad4_1 = sja1105_read_reg(spi, 0x100809); - sja1105_write_reg(spi, 0x100809, 0x03020313); - conf_pad4_2 = sja1105_read_reg(spi, 0x100809); + p2_mac_stat = sja1105_read_reg(0x00204); + p2_rxf = sja1105_read_reg(0x00426); + p2_txf = sja1105_read_reg(0x00422); + + p3_mac_stat = sja1105_read_reg(0x00206); + p3_rxf = sja1105_read_reg(0x00436); + p3_txf = sja1105_read_reg(0x00432); + + p4_mac_stat = sja1105_read_reg(0x00208); + p4_rxf = sja1105_read_reg(0x00446); + p4_txf = sja1105_read_reg(0x00442); + + sja1105_read_io(); spi_release_bus(spi); - printf("port mac stat rx tx\n"); - printf("3 (PHY): %08x %d %d\n", p3_mac_stat, p3_rxf, p3_txf); - printf("4 (CPU): %08x %d %d\n", p4_mac_stat, p4_rxf, p4_txf); - - printf("pad: %08x\n", conf_pad4_1); - printf("pad: %08x\n", conf_pad4_2); + printf("port mac stat rx tx\n"); + printf("0 (UM) : %08x %d %d\n", p0_mac_stat, p0_rxf, p0_txf); + printf("1 (BRoadR0): %08x %d %d\n", p1_mac_stat, p1_rxf, p1_txf); + printf("2 (BRoadR1): %08x %d %d\n", p2_mac_stat, p2_rxf, p2_txf); + printf("3 (PHY) : %08x %d %d\n", p3_mac_stat, p3_rxf, p3_txf); + printf("4 (CPU) : %08x %d %d\n", p4_mac_stat, p4_rxf, p4_txf); return 0; } - U_BOOT_CMD( sjainfo, 1, 1, do_sjainfo, "display eth switch information", diff --git a/board/nm/hancock/sja1105.c b/board/nm/hancock/sja1105.c index 9c1d027f67..9d309576bf 100644 --- a/board/nm/hancock/sja1105.c +++ b/board/nm/hancock/sja1105.c @@ -8,35 +8,44 @@ #include #include #include - +#include #include "sja1105.h" - +#include #define SJA_OPCODE_WRITE 0x80 #define SJA_OPCODE_READ 0x00 +#define SJA_READ_CNT(x) (((x) & 0x3F) << 1) -/*#define SJA_READ_CNT(x) (((x) & 0x3F) << 1)*/ +static struct spi_slave *spisja1105 = 0; +/* + * Function: sja1105_init + * -------------------- + * Takes and remembers SPI driver for later calls. + * + */ +void sja1105_init(struct spi_slave *spi) +{ + spisja1105 = spi; +} + /* * Function: sja1105_write_reg * -------------------- - * perform the expected 64 bits access to write to a register into the switch + * perform the expected 64 bits access to write to a register into the sja1105 switch * - * spi_slave: spi instance created from sja1105_setup_spi - * address : expect to be max 21 bits (range 0x0 to 0x100BC3h) - * data : expect to be max 32 bits + * address : 21 bits (range 0x0 to 0x100BC3) + * data : 32 bits * - * Returns: 0 on success, not 0 on failure */ - -int sja1105_write_reg(struct spi_slave *spislave, uint32_t address, uint32_t data) +void sja1105_write_reg( uint32_t address, uint32_t data) { - uint8_t dataspi[8]; /* = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };*/ - int rc; + uint8_t dataspi[8]; + /* OPCODE: WRITE, address from bit 24 DOWNTO bit 4 */ - dataspi[0] = 0x80 | (address >> 20 & 0x01); /* read/write bit (bit 31) to write */ - dataspi[1] = (address >> 12) & 0xFF; + dataspi[0] = SJA_OPCODE_WRITE | (address >> 20 & 0x01); + dataspi[1] = (address >> 12) & 0xFF;/* */ dataspi[2] = (address >> 4) & 0xFF; dataspi[3] = (address << 4) & 0xF0; dataspi[4] = (data >> 24) & 0xFF; @@ -44,125 +53,59 @@ int sja1105_write_reg(struct spi_slave *spislave, uint32_t address, uint32_t dat dataspi[6] = (data >> 8) & 0xFF; dataspi[7] = data & 0xFF; - rc = spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, NULL /*din*/, SPI_XFER_BEGIN| SPI_XFER_END /*flags*/); + (void)spi_xfer(spisja1105, 8*sizeof(dataspi) /*bitlen*/, dataspi, NULL /*din*/, SPI_XFER_BEGIN| SPI_XFER_END /*flags*/); - return rc; } - /* * Function: sja1105_read_reg * -------------------- - * perform the expected 64 bits access to readout 1 register ( multiple register not possible with this function) + * Perform the expected 64 bits access to readout 1 register ( multiple register not possible with this function) * - * spi_slave: spi instance created from sja1105_setup_spi - * address : expect to be max 21 bits (range 0x0 to 0x100BC3h) + * Address : 21 bits (range 0x0 to 0x100BC3) * - * returns : 32 bits read on the address pass as argument + * returns : readback data : 32 bits * */ - -/* - * readout 1 register (multiple register not possible with this function) - * expect an address of 21 bits - */ - -int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress) +uint32_t sja1105_read_reg( uint32_t address) { uint8_t dataspi[8]; uint8_t datain[8]; -/* int rc; */ int return_value; - /* OPCODE: READ, READ CNT = 1 */ - dataspi[0] = 0x02 | ((adress >> 20) & 0x01); /* read/write bit(bit 31) to read, and rc ( read count) to 1 double work */ - dataspi[1] = (adress >> 12) & 0xFF; - dataspi[2] = (adress >> 4) & 0xFF; - dataspi[3] = (adress << 4) & 0xF0; + /* OPCODE: READ, READ CNT = 1,address from bit 24 DOWNTO bit 4 */ + dataspi[0] = (SJA_OPCODE_READ | SJA_READ_CNT(1)) | ((address >> 20) & 0x01);/*MSB*/ + dataspi[1] = (address >> 12) & 0xFF; + dataspi[2] = (address >> 4) & 0xFF; + dataspi[3] = (address << 4) & 0xF0; dataspi[4] = 0x00; /* ignore by slave, use to readout the register */ dataspi[5] = 0x00; dataspi[6] = 0x00; dataspi[7] = 0x00; -/* printf("%02x %02x %02x %02x\n", dataspi[0], dataspi[1], dataspi[2], dataspi[3]); */ + (void)spi_xfer(spisja1105, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); - memset(datain, 0xaa, 8); - (void)spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); -/* - printf("sja1105_read_reg %d\n", rc); - printf("%02x %02x %02x %02x\n", datain[0], datain[1], datain[2], datain[3]); - printf("%02x %02x %02x %02x\n", datain[4], datain[5], datain[6], datain[7]); -*/ return_value = (datain[4]<<24) | (datain[5]<<16) | (datain[6]<<8) | (datain[7]<<0); - /* Todo: check byte order */ return return_value; } /* - * Function: sja1105_dynamic_init + * Function: sja1105_configure_firmware * -------------------- - * Load the dynamic configuration of the switch after the static confiugration to configure the PLL and the CGU - * this configuration aims to set clocks and system for RMII operation on all ports PLL 1 setup for 50Mhz - * port 0 and 4: RMII (PHY mode = external REFCLK) - * port 1,2 and 3: RMII (MAC mode) - * spi_slave: spi instance created from sja1105_setup_spi - * - */ -/* NOTE: this configuration assume that the driver does automatically - * a multi-wods access CS deassert must only be done at the end of a conf block - */ -void sja1105_dynamic_init(struct spi_slave *spislave) -{ - int rc; - - rc = sja1105_write_reg(spislave, 0x10000A, 0x0A010141); /* PLL 1 setup for 50MHz */ - rc = sja1105_write_reg(spislave, 0x10000A, 0x0A010940); /* PLL 1 setup for 50MHz */ - - /* port 0: RMII (PHY mode = external REFCLK) */ - rc = sja1105_write_reg(spislave, 0x10000B, 0x0A000001);//Disable IDIV0 - rc = sja1105_write_reg(spislave, 0x100015, 0x00000800);//Setting CLKSRC of RMII_REF_CLK_0 to TX_CLK_0 - - /* port 1: RMII (MAC mode) */ - rc = sja1105_write_reg(spislave, 0x10000C, 0x0A000001); //Disable IDIV1 - rc = sja1105_write_reg(spislave, 0x10001C, 0x02000800); //Setting CLKSRC of RMII_REF_CLK_1 to TX_CLK_1 - rc = sja1105_write_reg(spislave, 0x10001F, 0x0E000800); //setting CLKSRC of EXT_TX_CLK1 to PLL1 (50 MHz) - - /* port 2: RMII (MAC mode) */ - rc = sja1105_write_reg(spislave, 0x10000D, 0x0A000001); //Disable IDIV2 - rc = sja1105_write_reg(spislave, 0x100023, 0x04000800); //Setting CLKSRC of RMII_REF_CLK_2 to TX_CLK_2 - rc = sja1105_write_reg(spislave, 0x100026, 0x0E000800); //setting CLKSRC of EXT_TX_CLK2 to PLL1 (50 MHz) - - // port 3: RMII (MAC mode) - rc = sja1105_write_reg(spislave, 0x10000E, 0x0A000001); //Disable IDIV3 - rc = sja1105_write_reg(spislave, 0x10002A, 0x06000800); //Setting CLKSRC of RMII_REF_CLK_3 to TX_CLK_3 - rc = sja1105_write_reg(spislave, 0x10002D, 0x0E000800); //setting CLKSRC of EXT_TX_CLK3 to PLL1 (50 MHz) - - // port 4: RMII (PHY mode = external REFCLK) - rc = sja1105_write_reg(spislave, 0x10000F, 0x0A000001); //Disable IDIV4 - rc = sja1105_write_reg(spislave, 0x100031, 0x08000800); //Setting CLKSRC of RMII_REF_CLK_4 to TX_CLK_4 - - /* TODO: remove */ - (void)rc; - -/* printf("%d\n", rc); */ -} - - -/* - * Function: sja1105_static_init - * -------------------- -* Load the static configuration of the switch that must be loaded at startup of the switch - * the config is generated by the Intel hex to C tools : Configuration is managed with sja1105_appboard_v14.exe * + * When the device is powered up, it expects to receive an input stream containing initial setup information over the + * configuration interface. The initial configuration data sets the port modes, sets up VLANs and defines other forwarding + * and quality-of-service rules + * This function take care of loading the configuration according to the SJA1105 user manual * * spi_slave: spi instance created from sja1105_setup_spi - * config : list of configuration to load + * config : list of configuration * 0: switch all port with no priority, with port 0 and 5 as PHY MODE , all other MAC Mode * ..: To be added */ -/*Notes: this configuration assume that the driver does automatically a multi-wods access CS deassert must only be done at the end of a conf block*/ -void sja1105_static_init(struct spi_slave *spislave, int config) + +void sja1105_configure_firmware(int config) { static const uint8_t config_data_0[] = { 0x80, 0x20, 0x00, 0x00, 0x9E, 0x00, 0x03, 0x0E, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x21, 0x6F, 0x25, 0x6B, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF }; static const uint8_t config_data_1[] = { 0x80, 0x20, 0x04, 0x00, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFA, 0x2E, 0x19, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xF2, 0x69, 0x5C, 0xA5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x02, 0x52, 0x13, 0x87, 0x7B, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1A, 0x6A, 0xF6, 0x23, 0x53, 0x10, 0x00, 0x00, 0x00, 0xF7, 0xBD, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xEF, 0x7B, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xDE, 0xF7, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xBD, 0xEF, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0x7B, 0xDF, 0xF5, 0x8D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x04, 0xA6, 0x06, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0xDA, 0xB5, 0xBD, 0xC8 }; @@ -172,20 +115,136 @@ void sja1105_static_init(struct spi_slave *spislave, int config) (void)config; - rc = spi_xfer(spislave, 8*sizeof(config_data_0) /*bitlen*/, config_data_0, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); + rc = spi_xfer(spisja1105, 8*sizeof(config_data_0) /*bitlen*/, config_data_0, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); if (rc != 0) printf ("spi_xfer fail for config data 0\n"); - rc = spi_xfer(spislave, 8*sizeof(config_data_1) /*bitlen*/, config_data_1, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); + rc = spi_xfer(spisja1105, 8*sizeof(config_data_1) /*bitlen*/, config_data_1, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); if (rc != 0) printf ("spi_xfer fail for config data 1\n"); - rc = spi_xfer(spislave, 8*sizeof(config_data_2) /*bitlen*/, config_data_2, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); + rc = spi_xfer(spisja1105, 8*sizeof(config_data_2) /*bitlen*/, config_data_2, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); if (rc != 0) printf ("spi_xfer fail for config data 2\n"); - rc = spi_xfer(spislave, 8*sizeof(config_data_3) /*bitlen*/, config_data_3, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); + rc = spi_xfer(spisja1105, 8*sizeof(config_data_3) /*bitlen*/, config_data_3, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/); if (rc != 0) printf ("spi_xfer fail for config data 3\n"); } +/* + * Function: sja1105_configure_mode_and_clocks + * -------------------- + * configure the PLL , the CGU and the Auxiliary Configuration Unit . + * Notes: the sja1105_configure_firmware must be called prior to this funciton + * + * Mode and clock description : + * RMII operation on all ports: PLL 1 setup for 50Mhz + * port 0 and 4: RMII (PHY mode = external REFCLK) + * port 1,2 and 3: RMII (MAC mode) + * + */ + +void sja1105_configure_mode_and_clocks() +{ + + sja1105_write_reg( 0x10000A, 0x0A010141); /* PLL 1 setup for 50MHz */ + sja1105_write_reg( 0x10000A, 0x0A010940); /* PLL 1 setup for 50MHz */ + + /* port 0: RMII (PHY mode = external REFCLK) */ + sja1105_write_reg( 0x10000B, 0x0A000001);//Disable IDIV0 + sja1105_write_reg( 0x100015, 0x00000800);//Setting CLKSRC of RMII_REF_CLK_0 to TX_CLK_0 + + /* port 1: RMII (MAC mode) */ + sja1105_write_reg( 0x10000C, 0x0A000001); //Disable IDIV1 + sja1105_write_reg( 0x10001C, 0x02000800); //Setting CLKSRC of RMII_REF_CLK_1 to TX_CLK_1 + sja1105_write_reg( 0x10001F, 0x0E000800); //setting CLKSRC of EXT_TX_CLK1 to PLL1 (50 MHz) + + /* port 2: RMII (MAC mode) */ + sja1105_write_reg( 0x10000D, 0x0A000001); //Disable IDIV2 + sja1105_write_reg( 0x100023, 0x04000800); //Setting CLKSRC of RMII_REF_CLK_2 to TX_CLK_2 + sja1105_write_reg( 0x100026, 0x0E000800); //setting CLKSRC of EXT_TX_CLK2 to PLL1 (50 MHz) + + // port 3: RMII (MAC mode) + sja1105_write_reg( 0x10000E, 0x0A000001); //Disable IDIV3 + sja1105_write_reg( 0x10002A, 0x06000800); //Setting CLKSRC of RMII_REF_CLK_3 to TX_CLK_3 + sja1105_write_reg( 0x10002D, 0x0E000800); //setting CLKSRC of EXT_TX_CLK3 to PLL1 (50 MHz) + + // port 4: RMII (PHY mode = external REFCLK) + sja1105_write_reg( 0x10000F, 0x0A000001); //Disable IDIV4 + sja1105_write_reg( 0x100031, 0x08000800); //Setting CLKSRC of RMII_REF_CLK_4 to TX_CLK_4 + +} + + +/* + * Function: sja1105_configure_io + * -------------------- + * configure IO pads (unused IOs): set pull down to unused pins and set drive strengths + * + * + */ +void sja1105_configure_io() +{ + + /* Port 0 and Port 4 RX*/ + /* Enable pull down on CPU Port RX_DV/CRS_DV/RX_CTL and RX_ER and RX_CLK/RXC and RXD2 RXD3 */ + sja1105_write_reg(0x100801, 0x03020313); + sja1105_write_reg(0x100809, 0x03020313); + /* Port 1 to Port 3 RX*/ + /* Enable pull down on CPU Port and RX_CLK/RXC and RXD2 RXD3 */ + sja1105_write_reg(0x100803, 0x03020213); + sja1105_write_reg(0x100805, 0x03020213); + sja1105_write_reg(0x100807, 0x03020213); + + /* Port 0 to Port 4 TX*/ + /* Enable pull down on CPU Port TX_ER and TXD2 TXD3 */ + sja1105_write_reg(0x100800, 0x13121312); + sja1105_write_reg(0x100802, 0x13121312); + sja1105_write_reg(0x100804, 0x13121312); + sja1105_write_reg(0x100806, 0x13121312); + sja1105_write_reg(0x100808, 0x13121312); +} + +#if 1 +/* + * Function: sja1105_read_io + * -------------------- + * readout and print the configured IO pads (unused IOs) + * + * + */ +void sja1105_read_io() +{ + + int val ; + val = sja1105_read_reg(0x100801); + printf("CFG_PAD_MII0_RX Reg: %08x\n", val); + val = sja1105_read_reg(0x100800); + printf("CFG_PAD_MII0_TX Reg: %08x\n", val); + + val = sja1105_read_reg(0x100803); + printf("CFG_PAD_MII1_RX Reg: %08x\n", val); + val = sja1105_read_reg(0x100802); + printf("CFG_PAD_MII1_TX Reg: %08x\n", val); + + val = sja1105_read_reg(0x100805); + printf("CFG_PAD_MII2_RX Reg: %08x\n", val); + val = sja1105_read_reg(0x100804); + printf("CFG_PAD_MII2_TX Reg: %08x\n", val); + + + val = sja1105_read_reg(0x100807); + printf("CFG_PAD_MII3_RX Reg: %08x\n", val); + val = sja1105_read_reg(0x100806); + printf("CFG_PAD_MII3_TX Reg: %08x\n", val); + + val = sja1105_read_reg(0x100809); + printf("CFG_PAD_MII4_RX Reg: %08x\n", val); + val = sja1105_read_reg(0x100808); + printf("CFG_PAD_MII4_TX Reg: %08x\n", val); + + +} +#endif + diff --git a/board/nm/hancock/sja1105.h b/board/nm/hancock/sja1105.h index 0c0d028335..7c6c575b3e 100644 --- a/board/nm/hancock/sja1105.h +++ b/board/nm/hancock/sja1105.h @@ -9,28 +9,25 @@ #ifndef _SJA1105_H_ #define _SJA1105_H_ -/* TODO: make return type uint32_t */ -int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress); -/* TODO: Remove return value, since ignored anyway */ -int sja1105_write_reg(struct spi_slave *spislave, uint32_t address, uint32_t data); +uint32_t sja1105_read_reg(uint32_t adress); -/* TODO: Find better name -> ... load_firmware / configure / setup ... */ -void sja1105_static_init(struct spi_slave *spislave, int config); -/* TODO: Find better name -> ... configure_mode_and_clocks ... */ -void sja1105_dynamic_init(struct spi_slave *spislave); +void sja1105_write_reg(uint32_t address, uint32_t data); -/* TODO: Add method to configure IO pads (unused IOs) - * Set pull downs where required. - * Drive strength settings... - * - * void sja1105_configure_io(void) - */ -/* TODO: Add sja1105_init(struct spi_slave *spi) - * Takes and remembers SPI driver for later calls. - * Remove spislave argument from other methods. - */ +void sja1105_configure_firmware(int config); + + +void sja1105_configure_mode_and_clocks(void); + + +void sja1105_configure_io(void); + + +void sja1105_read_io(void); + + +void sja1105_init(struct spi_slave *spi); #endif